CN209044408U - A kind of UVLO protection circuit - Google Patents
A kind of UVLO protection circuit Download PDFInfo
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- CN209044408U CN209044408U CN201821824056.9U CN201821824056U CN209044408U CN 209044408 U CN209044408 U CN 209044408U CN 201821824056 U CN201821824056 U CN 201821824056U CN 209044408 U CN209044408 U CN 209044408U
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Abstract
The utility model provides a kind of UVLO protection circuit, a NMOS tube is added between reference circuit and filter capacitor, the threshold voltage of UVLO is constituted using the sum of the threshold voltage of NMOS tube itself and reference voltage, only after the grid voltage of NMOS tube is greater than UVLO threshold voltage, circuit just has output, otherwise circuit is constantly in UVLO guard mode, after supply voltage is made up of the output stage of current mirror comparator pull-up current mirror and pull-down current mirror, since circuit pull-up current ability is much larger than pull-down current ability, current mirror comparative degree output voltage is almost close to power end voltage, grid of the voltage transmission to NMOS tube, to not influence the PSRR value of circuit.
Description
Technical field
The present invention relates to circuit field, especially a kind of protection circuit.
Background technique
Low pressure difference linear voltage regulator (Low Dropout Regulator, LDO) is at present in electronic product using most
Electric power management circuit.In order to make the work of LDO normal table, chip power voltage is started from scratch slow rising, reaches minimum
After operating voltage, chip starts to work normally.Due to the work of chip interior functional module in some special installations, chip
It exports electric current to increase, the supply voltage of chip can generate fluctuation.When supply voltage is too low, chip internal circuits can generate very big
Power consumption, output end when supply voltage is excessively high it is possible that overcharge phenomenon, will result in chip internal circuits burn and shadow
Ring the stability for arriving entire circuit system.So, in circuit design, needing to be added under-voltage lock to guarantee that LDO is worked normally
(Under Voltage Lock Out, UVLO) circuit is determined to guarantee that loop could be defeated only when power supply is higher than UVLO threshold value
Normal value out, that is, ensure that circuit is in guard mode when input voltage is lower than minimum.
At present the most commonly used scheme of UVLO circuit be using the partial pressure of input voltage as comparison voltage and reference voltage into
After going relatively, whether decision circuitry is in under-voltage, when comparison voltage is lower than reference voltage, turns off the circuit of rear end, reaches guarantor
The purpose of protection circuit.Although this method can be effectively protected circuit, there is also certain disadvantages: the structure inside circuit
It is excessively complicated, and because increasing UVLO module when circuit work, internal power consumption is larger, this just undoubtedly increases setting for circuit
Count cost and difficulty.
Summary of the invention
For overcome the deficiencies in the prior art, the present invention provides a kind of simple UVLO protection circuit, is mainly used for correlation
Protection circuit field, to solve the technical problem of related fields.
The technical solution adopted by the present invention to solve the technical problems is:
A kind of UVLO protection circuit, including P-channel enhancement type metal-oxide-semiconductor M1, P-channel enhancement type metal-oxide-semiconductor M2, N-channel enhancing
Type metal-oxide-semiconductor M3-M5, reference circuit module, filter capacitor C and the input port the Vcc and port Vout, the port Vcc and outer
The connection of portion's input supply terminal, the port Vout are that UVLO protects circuit reference output port.
The P-channel enhancement type metal-oxide-semiconductor M1 source electrode connects the end input power Vcc, and P-channel enhancement type metal-oxide-semiconductor M1 grid connects
Connect the grid of P-channel enhancement type metal-oxide-semiconductor M2, the grid of P-channel enhancement type metal-oxide-semiconductor M1 drain electrode connection itself, P-channel enhancement type
The grid of metal-oxide-semiconductor M2；The P-channel enhancement type metal-oxide-semiconductor M2 source electrode connects the end input power Vcc, P-channel enhancement type metal-oxide-semiconductor M2
Grid connects the grid of P-channel enhancement type metal-oxide-semiconductor M1, the P-channel enhancement type metal-oxide-semiconductor M2 drain electrode connection enhanced metal-oxide-semiconductor M4 of N-channel
Drain electrode and the enhanced metal-oxide-semiconductor M5 of N-channel grid.
The enhanced metal-oxide-semiconductor M3 source electrode ground connection of N-channel, the enhanced metal-oxide-semiconductor M3 grid connection N-channel of N-channel are enhanced
The grid of metal-oxide-semiconductor M4, the grid of the enhanced metal-oxide-semiconductor M3 drain electrode connection itself of N-channel and the grid of the enhanced metal-oxide-semiconductor M4 of N-channel；
The enhanced metal-oxide-semiconductor M4 source electrode ground connection of N-channel, the enhanced metal-oxide-semiconductor M4 grid connection enhanced metal-oxide-semiconductor M3's of N-channel of N-channel
Grid and drain electrode, the drain electrode of the drain electrode connection P-channel enhancement type metal-oxide-semiconductor M2 of the enhanced metal-oxide-semiconductor M4 of N-channel and N-channel are enhanced
The grid of metal-oxide-semiconductor M5.
Described P-channel enhancement type metal-oxide-semiconductor M1, M2 constitute pull-up current mirror module, and N-channel enhanced metal-oxide-semiconductor M3, M4 are constituted
Pull-down current mirror module, pull-up current mirror module and pull-down current mirror module collectively form the output stage of current mirror comparator.
The enhanced metal-oxide-semiconductor M5 grid connection P-channel enhancement type metal-oxide-semiconductor M2 drain electrode of N-channel and the enhanced MOS of N-channel
Pipe M4 drain electrode, the enhanced metal-oxide-semiconductor M5 drain electrode connection benchmark circuit output end of N-channel, the enhanced metal-oxide-semiconductor M5 source electrode connection of N-channel
The positive plate and integrated circuit of filter capacitor C exports the port Vout.
The drain electrode of the reference circuit module output end connection enhanced metal-oxide-semiconductor M5 of N-channel.
The source electrode of the filter capacitor C positive plate connection enhanced metal-oxide-semiconductor M5 of N-channel, filter capacitor C cathode plate earthing.
In conjunction with Fig. 1, the working mechanism of integrated circuit are as follows: the reference voltage VBG and N-channel that reference circuit generates are enhanced
The sum of threshold V T H5 of metal-oxide-semiconductor M5 constitutes the threshold voltage of UVLO, that is, the grid as the enhanced metal-oxide-semiconductor M5 of N-channel
When voltage reaches the threshold voltage of UVLO, the source and drain end of the enhanced metal-oxide-semiconductor M5 of N-channel is connected, and circuit output end Vout exports base
Quasi- voltage VBG, in order to avoid the grid that supply voltage is directly accessed the enhanced metal-oxide-semiconductor M5 of N-channel influenced the PSRR of circuit
Greatly, it is made up of under pull-up current mirror circuit and N-channel enhanced metal-oxide-semiconductor M3 and M4 composition P-channel enhancement type metal-oxide-semiconductor M1 and M2
The output end of sourcing current mirror, two current mirrors is compared again, forms the output stage of current mirror comparator, it is assumed that P-channel enhancing
The drain current of type metal-oxide-semiconductor M1 is IB1, the pipe of P-channel enhancement type metal-oxide-semiconductor M2 and the number ratio of P-channel enhancement type metal-oxide-semiconductor M1
For m:1, the drain current of the enhanced metal-oxide-semiconductor M3 of N-channel is IB2, the pipe of the enhanced metal-oxide-semiconductor M2 of N-channel and the number of M4 pipe
Than for n:1, since the pull-up current ability of P-channel enhancement type metal-oxide-semiconductor M2 in circuit is greater than the enhanced metal-oxide-semiconductor M4's of N-channel
Pull-down current ability, is expressed with formula:
mIB1> nIB2 (1)
IB1 is the leakage current of P-channel enhancement type M1 pipe in formula (1), and IB2 is the leakage current of the enhanced M3 pipe of N-channel, m P
Channel enhancement M2 pipe and M1 pipe number ratio, n are the enhanced M4 pipe of N-channel and M3 pipe number ratio；
Due to the source and drain end voltage VDS2 very little of the enhanced metal-oxide-semiconductor M2 of N-channel, so that reaching the enhanced metal-oxide-semiconductor M5 of N-channel
Grid voltage close to Vcc.It does so, on the one hand will not influence Vout voltage close to VBG voltage, it on the other hand will not be to Vout's
PSRR is influenced too much.
When the threshold value electricity of source-drain voltage VDS2 and UVLO of the input supply voltage Vcc greater than P-channel enhancement type metal-oxide-semiconductor M2
The sum of pressure, is expressed with publicity:
VCC> VDS2+VTH5+VBG (2)
At this point, integrated circuit reaches the threshold value of UVLO, entire circuit starts to start, the end Vout outputting reference voltage VBG.
The beneficial effects of the present invention are:
1. overall circuit design is simple, a NMOS tube only need to be added between reference circuit and filter capacitor, utilize
The sum of threshold voltage and reference voltage of NMOS tube itself constitute the threshold voltage of UVLO, only when the grid voltage of NMOS tube is greater than
After UVLO threshold voltage, circuit just has output, and otherwise circuit is constantly in UVLO guard mode.
After 2. supply voltage is made up of the output stage of current mirror comparator pull-up current mirror and pull-down current mirror, due to electricity
Road sourcing current ability is much larger than pull-down current ability, and current mirror comparative degree output voltage is almost close to power end voltage, the electricity
Pressure is transferred to the grid of NMOS tube, to not influence the PSRR value of circuit.
Detailed description of the invention
Fig. 1 is a kind of UVLO protection circuit schematic diagram of the invention.
Specific embodiment
Present invention will be further explained below with reference to the attached drawings and examples.
The present invention provides a kind of simple UVLO protection circuit, mainly uses in reference circuit output end and output in circuit
Increase an enhanced metal-oxide-semiconductor of N-channel between filter capacitor, using the threshold voltage of the enhanced metal-oxide-semiconductor of N-channel plus benchmark electricity
The sum of the reference voltage of road module output constitutes UVLO threshold voltage, only when input supply terminal is reached by internal damping circuit
To the enhanced metal-oxide-semiconductor of N-channel grid voltage be greater than UVLO threshold voltage after, entire circuit just has output voltage.This method is not only
Circuit design is simply low in cost, and circuit is crossed filled with good inhibiting effect, and circuit internal power consumption very little, for
LDO circuit has good under-voltage protection effect.
A kind of UVLO protection circuit specific technical solution is as follows:
A kind of UVLO protection circuit, including P-channel enhancement type metal-oxide-semiconductor M1, P-channel enhancement type metal-oxide-semiconductor M2, N-channel enhancing
Type metal-oxide-semiconductor M3-M5, reference circuit module, filter capacitor C and the input port the Vcc and port Vout, the port Vcc and outer
The connection of portion's input supply terminal, the port Vout are that UVLO protects circuit reference output port.
The P-channel enhancement type metal-oxide-semiconductor M1 source electrode connects the end input power Vcc, and P-channel enhancement type metal-oxide-semiconductor M1 grid connects
Connect the grid of P-channel enhancement type metal-oxide-semiconductor M2, the grid of P-channel enhancement type metal-oxide-semiconductor M1 drain electrode connection itself, P-channel enhancement type
The grid of metal-oxide-semiconductor M2；The P-channel enhancement type metal-oxide-semiconductor M2 source electrode connects the end input power Vcc, P-channel enhancement type metal-oxide-semiconductor M2
Grid connects the grid of P-channel enhancement type metal-oxide-semiconductor M1, the P-channel enhancement type metal-oxide-semiconductor M2 drain electrode connection enhanced metal-oxide-semiconductor M4 of N-channel
Drain electrode and the enhanced metal-oxide-semiconductor M5 of N-channel grid.
The enhanced metal-oxide-semiconductor M3 source electrode ground connection of N-channel, the enhanced metal-oxide-semiconductor M3 grid connection N-channel of N-channel are enhanced
The grid of metal-oxide-semiconductor M4, the grid of the enhanced metal-oxide-semiconductor M3 drain electrode connection itself of N-channel and the grid of the enhanced metal-oxide-semiconductor M4 of N-channel；
The enhanced metal-oxide-semiconductor M4 source electrode ground connection of N-channel, the enhanced metal-oxide-semiconductor M4 grid connection enhanced metal-oxide-semiconductor M3's of N-channel of N-channel
Grid and drain electrode, the drain electrode of the drain electrode connection P-channel enhancement type metal-oxide-semiconductor M2 of the enhanced metal-oxide-semiconductor M4 of N-channel and N-channel are enhanced
The grid of metal-oxide-semiconductor M5.
Described P-channel enhancement type metal-oxide-semiconductor M1, M2 constitute pull-up current mirror module, and N-channel enhanced metal-oxide-semiconductor M3, M4 are constituted
Pull-down current mirror module, pull-up current mirror module and pull-down current mirror module collectively form the output stage of current mirror comparator.
The enhanced metal-oxide-semiconductor M5 grid connection P-channel enhancement type metal-oxide-semiconductor M2 drain electrode of N-channel and the enhanced MOS of N-channel
Pipe M4 drain electrode, the enhanced metal-oxide-semiconductor M5 drain electrode connection benchmark circuit output end of N-channel, the enhanced metal-oxide-semiconductor M5 source electrode connection of N-channel
The positive plate and integrated circuit of filter capacitor C exports the port Vout.
The drain electrode of the reference circuit module output end connection enhanced metal-oxide-semiconductor M5 of N-channel.
The source electrode of the filter capacitor C positive plate connection enhanced metal-oxide-semiconductor M5 of N-channel, filter capacitor C cathode plate earthing.
In conjunction with Fig. 1, the working mechanism of integrated circuit are as follows: the reference voltage VBG and N-channel that reference circuit generates are enhanced
The sum of threshold V T H5 of metal-oxide-semiconductor M5 constitutes the threshold voltage of UVLO, that is, the grid as the enhanced metal-oxide-semiconductor M5 of N-channel
When voltage reaches the threshold voltage of UVLO, the source and drain end of the enhanced metal-oxide-semiconductor M5 of N-channel is connected, and circuit output end Vout exports base
Quasi- voltage VBG, in order to avoid the grid that supply voltage is directly accessed the enhanced metal-oxide-semiconductor M5 of N-channel influenced the PSRR of circuit
Greatly, it is made up of under pull-up current mirror circuit and N-channel enhanced metal-oxide-semiconductor M3 and M4 composition P-channel enhancement type metal-oxide-semiconductor M1 and M2
The output end of sourcing current mirror, two current mirrors is compared again, forms the output stage of current mirror comparator, it is assumed that P-channel enhancing
The drain current of type metal-oxide-semiconductor M1 is IB1, the pipe of P-channel enhancement type metal-oxide-semiconductor M2 and the number ratio of P-channel enhancement type metal-oxide-semiconductor M1
For m:1, the drain current of the enhanced metal-oxide-semiconductor M3 of N-channel is IB2, the pipe of the enhanced metal-oxide-semiconductor M2 of N-channel and the number of M4 pipe
Than for n:1, since the pull-up current ability of P-channel enhancement type metal-oxide-semiconductor M2 in circuit is greater than the enhanced metal-oxide-semiconductor M4's of N-channel
Pull-down current ability, is expressed with formula:
mIB1> nIB2 (1)
IB1 is the leakage current of P-channel enhancement type M1 pipe in formula (1), and IB2 is the leakage current of the enhanced M3 pipe of N-channel, m P
Channel enhancement M2 pipe and M1 pipe number ratio, n are the enhanced M4 pipe of N-channel and M3 pipe number ratio；
Due to the source and drain end voltage VDS2 very little of the enhanced metal-oxide-semiconductor M2 of N-channel, so that reaching the enhanced metal-oxide-semiconductor M5 of N-channel
Grid voltage close to Vcc.It does so, on the one hand will not influence Vout voltage close to VBG voltage, it on the other hand will not be to Vout's
PSRR is influenced too much.
When the threshold value electricity of source-drain voltage VDS2 and UVLO of the input supply voltage Vcc greater than P-channel enhancement type metal-oxide-semiconductor M2
The sum of pressure, is expressed with publicity:
VCC> VDS2+VTH5+VBG (2)
At this point, integrated circuit reaches the threshold value of UVLO, entire circuit starts to start, the end Vout outputting reference voltage VBG.
As shown in Figure 1, the invention mainly comprises P-channel enhancement type metal-oxide-semiconductor M1, M2, the enhanced metal-oxide-semiconductor M3-M5 of N-channel,
Reference circuit module, filter capacitor C and the input port Vcc and the port Vout.The port Vcc and external input power end connect
It connects, the port Vout is integrated circuit reference output mouth.
The P-channel enhancement type metal-oxide-semiconductor M1 source electrode connects the end input power Vcc, and grid connects P-channel enhancement type metal-oxide-semiconductor
The grid of M2, drain electrode connect the grid of the grid of itself, PMOS tube M2；The P-channel enhancement type metal-oxide-semiconductor M2 source electrode connection input
Power Vcc end, grid connect P-channel enhancement type metal-oxide-semiconductor M1 grid, drain electrode connection the enhanced metal-oxide-semiconductor M4 of N-channel drain electrode and
The grid of the enhanced metal-oxide-semiconductor M5 of N-channel.
The enhanced metal-oxide-semiconductor M3 source electrode ground connection of N-channel, grid connect the grid of the enhanced metal-oxide-semiconductor M4 of N-channel, drain electrode
Connect itself grid and M4 pipe grid；The enhanced metal-oxide-semiconductor M4 source electrode ground connection of the N-channel, grid connect M3 grid and
Drain electrode, the drain electrode of the drain electrode connection P-channel enhancement type metal-oxide-semiconductor M2 of M4 and the grid of the enhanced metal-oxide-semiconductor M5 of N-channel.
Described P-channel enhancement type metal-oxide-semiconductor M1, M2 constitute pull-up current mirror module, and N-channel enhanced metal-oxide-semiconductor M3, M4 are constituted
Pull-down current mirror module, pull-up current mirror module and pull-down current mirror module together constitute the output of current mirror comparator
Grade.
The enhanced metal-oxide-semiconductor M5 grid connection P-channel enhancement type metal-oxide-semiconductor M2 drain electrode of N-channel and the enhanced MOS of N-channel
Pipe M4 drain electrode, drain electrode connection benchmark circuit output end, source electrode connects the positive plate of filter capacitor C and integrated circuit exports the end Vout
Mouthful.
The drain electrode of the reference circuit module output end connection enhanced metal-oxide-semiconductor M5 of N-channel.
The source electrode of the filter capacitor C positive plate connection enhanced metal-oxide-semiconductor M5 of N-channel.
In conjunction with Fig. 1, the working mechanism of integrated circuit are as follows: the reference voltage V that reference circuit generatesBGWith the enhanced MOS of N-channel
The threshold voltage V of pipe M5TH5The sum of constitute the threshold voltage of UVLO, that is, the grid voltage as the enhanced metal-oxide-semiconductor M5 of N-channel
When reaching the threshold voltage of UVLO, the source and drain end of M5 pipe is connected, circuit output end Vout outputting reference voltage VBG.In order to avoid electricity
The grid that source voltage is directly accessed the enhanced metal-oxide-semiconductor M5 of N-channel is excessive on the PSRR of circuit influence, passes through P-channel enhancement type MOS
Pipe M1 and M2 constitute pull-up current mirror circuit and N-channel enhanced metal-oxide-semiconductor M3 and M4 constitute pull-down current mirror, the two current mirrors
Output end be compared again, formed current mirror comparator output stage.It is assumed that the drain current of P-channel enhancement type metal-oxide-semiconductor M1
For IB1, the pipe of P-channel enhancement type metal-oxide-semiconductor M2 and the number ratio of M1 pipe are m:1, the drain current of the enhanced metal-oxide-semiconductor M3 of N-channel
For IB2, the number ratio of the pipe of the enhanced metal-oxide-semiconductor M2 of N-channel and M4 pipe is n:1, due to P-channel enhancement type metal-oxide-semiconductor in circuit
The pull-up current ability of M2 is greater than the pull-down current ability of the enhanced metal-oxide-semiconductor M4 of N-channel, is expressed with formula:
mIB1> nIB2 (3)
I in formulaB1For the leakage current of P-channel enhancement type M1 pipe, IB2For the leakage current of the enhanced M3 pipe of N-channel, m is P-channel
Enhanced M2 pipe and M1 pipe number ratio, n are the enhanced M4 pipe of N-channel and M3 pipe number ratio.
Due to the source and drain end voltage V of the enhanced metal-oxide-semiconductor M2 of N-channelDS2Very little, so that reaching the enhanced metal-oxide-semiconductor M5 of N-channel
Grid voltage close to Vcc.It does so, on the one hand will not influence Vout voltage close to VBGVoltage, on the other hand will not be to Vout's
PSRR is influenced too much.
The above is namely when input supply voltage Vcc is greater than the source-drain voltage of the P-channel enhancement type metal-oxide-semiconductor M2
VDS2The sum of with the threshold voltage of the UVLO, expressed with publicity:
VCC> VDS2+VTH5+VBG (4)
At this moment, integrated circuit reaches the threshold value of UVLO, and entire circuit starts to start, the end Vout outputting reference voltage VBG。
To sum up, the technology of the present invention proposes a kind of simple UVLO protection circuit, and under-voltage protection can be effectively performed, and
Guarantee that the PSRR of circuit is unaffected.Circuit is protected relative to UVLO before, this method overall circuit design is simple, for
Circuit is crossed filled with good inhibiting effect, and circuit internal power consumption very little, has good under-voltage protection for other circuits
Effect.
Claims (1)
1. a kind of UVLO protects circuit, it is characterised in that:
The UVLO protects circuit, including P-channel enhancement type metal-oxide-semiconductor M1, P-channel enhancement type metal-oxide-semiconductor M2, the enhanced MOS of N-channel
Pipe M3-M5, reference circuit module, filter capacitor C and the input port Vcc and the port Vout, the port Vcc and external input
Power end connection, the port Vout are that UVLO protects circuit reference output port；
The P-channel enhancement type metal-oxide-semiconductor M1 source electrode connects the end input power Vcc, and P-channel enhancement type metal-oxide-semiconductor M1 grid connects P ditch
The grid of the enhanced metal-oxide-semiconductor M2 in road, grid, the P-channel enhancement type metal-oxide-semiconductor M2 of P-channel enhancement type metal-oxide-semiconductor M1 drain electrode connection itself
Grid；The P-channel enhancement type metal-oxide-semiconductor M2 source electrode connects the end input power Vcc, the connection of P-channel enhancement type metal-oxide-semiconductor M2 grid
The grid of P-channel enhancement type metal-oxide-semiconductor M1, P-channel enhancement type metal-oxide-semiconductor M2 drain electrode connection the enhanced metal-oxide-semiconductor M4 of N-channel drain electrode and
The grid of the enhanced metal-oxide-semiconductor M5 of N-channel；
The enhanced metal-oxide-semiconductor M3 source electrode ground connection of N-channel, the enhanced metal-oxide-semiconductor M3 grid of N-channel connect the enhanced metal-oxide-semiconductor of N-channel
The grid of M4, the grid of the enhanced metal-oxide-semiconductor M3 drain electrode connection itself of N-channel and the grid of the enhanced metal-oxide-semiconductor M4 of N-channel；The N
Channel enhancement metal-oxide-semiconductor M4 source electrode ground connection, the grid of the enhanced metal-oxide-semiconductor M4 grid connection enhanced metal-oxide-semiconductor M3 of N-channel of N-channel
And drain electrode, the drain electrode of the drain electrode connection P-channel enhancement type metal-oxide-semiconductor M2 of the enhanced metal-oxide-semiconductor M4 of N-channel and the enhanced metal-oxide-semiconductor of N-channel
The grid of M5；
Described P-channel enhancement type metal-oxide-semiconductor M1, M2 constitute pull-up current mirror module, under N-channel enhanced metal-oxide-semiconductor M3, M4 are constituted
Sourcing current mirror module, pull-up current mirror module and pull-down current mirror module collectively form the output stage of current mirror comparator；
The enhanced metal-oxide-semiconductor M5 grid connection P-channel enhancement type metal-oxide-semiconductor M2 drain electrode of N-channel and the enhanced metal-oxide-semiconductor M4 of N-channel
Drain electrode, the enhanced metal-oxide-semiconductor M5 drain electrode connection benchmark circuit output end of N-channel, the enhanced metal-oxide-semiconductor M5 source electrode connection filtering of N-channel
The positive plate and integrated circuit of capacitor C exports the port Vout；
The drain electrode of the reference circuit module output end connection enhanced metal-oxide-semiconductor M5 of N-channel；
The source electrode of the filter capacitor C positive plate connection enhanced metal-oxide-semiconductor M5 of N-channel, filter capacitor C cathode plate earthing；
The working mechanism of the UVLO protection circuit are as follows: the reference voltage VBG and the enhanced metal-oxide-semiconductor of N-channel that reference circuit generates
The sum of threshold V T H5 of M5 constitutes the threshold voltage of UVLO, that is, when the grid voltage of the enhanced metal-oxide-semiconductor M5 of N-channel reaches
To UVLO threshold voltage when, the enhanced metal-oxide-semiconductor M5 of N-channel source and drain end conducting, circuit output end Vout outputting reference voltage
VBG influences the PSRR of circuit excessive, passes through in order to avoid supply voltage is directly accessed the grid of the enhanced metal-oxide-semiconductor M5 of N-channel
P-channel enhancement type metal-oxide-semiconductor M1 and M2 constitute pull-up current mirror circuit and N-channel enhanced metal-oxide-semiconductor M3 and M4 constitute pull-down current
The output end of mirror, two current mirrors is compared again, forms the output stage of current mirror comparator, it is assumed that P-channel enhancement type metal-oxide-semiconductor
The drain current of M1 is IB1, and the pipe of P-channel enhancement type metal-oxide-semiconductor M2 and the number ratio of P-channel enhancement type metal-oxide-semiconductor M1 are m:1, N
The drain current of channel enhancement metal-oxide-semiconductor M3 is IB2, and the pipe of the enhanced metal-oxide-semiconductor M2 of N-channel and the number ratio of M4 pipe are n:1,
Since the pull-up current ability of P-channel enhancement type metal-oxide-semiconductor M2 in circuit is greater than the pull-down current of the enhanced metal-oxide-semiconductor M4 of N-channel
Ability is expressed with formula:
mIB1> nIB2(1)
IB1 is the leakage current of P-channel enhancement type M1 pipe in formula (1), and IB2 is the leakage current of the enhanced M3 pipe of N-channel, and m is P-channel
Enhanced M2 pipe and M1 pipe number ratio, n are the enhanced M4 pipe of N-channel and M3 pipe number ratio；
Due to the source and drain end voltage VDS2 very little of the enhanced metal-oxide-semiconductor M2 of N-channel, so that reaching the grid of the enhanced metal-oxide-semiconductor M5 of N-channel
Nearly Vcc is crimped, when the threshold value of source-drain voltage VDS2 and UVLO of the input supply voltage Vcc greater than P-channel enhancement type metal-oxide-semiconductor M2
The sum of voltage is expressed with publicity:
VCC> VDS2+VTH5+VBG(2)
At this point, integrated circuit reaches the threshold value of UVLO, entire circuit starts to start, the end Vout outputting reference voltage VBG.
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| CN201821824056.9U CN209044408U (en) | 2018-11-06 | 2018-11-06 | A kind of UVLO protection circuit |
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| CN201821824056.9U CN209044408U (en) | 2018-11-06 | 2018-11-06 | A kind of UVLO protection circuit |
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| CN209044408U true CN209044408U (en) | 2019-06-28 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109283963A (en) * | 2018-11-06 | 2019-01-29 | 西安拓尔微电子有限责任公司 | A kind of UVLO protection circuit |
| CN115202430A (en) * | 2021-04-13 | 2022-10-18 | 拓尔微电子股份有限公司 | Reference voltage generating circuit and oscillator |
-
2018
- 2018-11-06 CN CN201821824056.9U patent/CN209044408U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109283963A (en) * | 2018-11-06 | 2019-01-29 | 西安拓尔微电子有限责任公司 | A kind of UVLO protection circuit |
| CN109283963B (en) * | 2018-11-06 | 2024-06-14 | 拓尔微电子股份有限公司 | UVLO protection circuit |
| CN115202430A (en) * | 2021-04-13 | 2022-10-18 | 拓尔微电子股份有限公司 | Reference voltage generating circuit and oscillator |
| CN115202430B (en) * | 2021-04-13 | 2024-05-24 | 拓尔微电子股份有限公司 | Reference voltage generating circuit and oscillator |
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Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee after: Xi'an Tuoer Microelectronics Co.,Ltd. Address before: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee before: XI'AN TUOER MICROELECTRONICS Co.,Ltd. Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee after: Tuoer Microelectronics Co.,Ltd. Address before: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee before: Xi'an Tuoer Microelectronics Co.,Ltd. |
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Granted publication date: 20190628 Effective date of abandoning: 20240614 |
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