CN109283963B - UVLO protection circuit - Google Patents
UVLO protection circuit Download PDFInfo
- Publication number
- CN109283963B CN109283963B CN201811313209.8A CN201811313209A CN109283963B CN 109283963 B CN109283963 B CN 109283963B CN 201811313209 A CN201811313209 A CN 201811313209A CN 109283963 B CN109283963 B CN 109283963B
- Authority
- CN
- China
- Prior art keywords
- channel enhancement
- mos tube
- type mos
- enhancement type
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 18
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
The invention provides a UVLO protection circuit, an NMOS tube is added between a reference circuit and a filter capacitor, the threshold voltage of the UVLO is formed by the sum of the threshold voltage of the NMOS tube and the reference voltage, the circuit only outputs when the grid voltage of the NMOS tube is larger than the threshold voltage of the UVLO, otherwise, the circuit is always in a UVLO protection state, and after the power voltage forms an output stage of a current mirror comparator through a pull-up current mirror and a pull-down current mirror, the pull-up current capability of the circuit is far larger than the pull-down current capability, the output voltage of the current mirror comparator is almost close to the voltage of a power end, and the voltage is transmitted to the grid electrode of the NMOS tube, so that the PSRR value of the circuit is not affected.
Description
Technical Field
The invention relates to the field of circuits, in particular to a protection circuit.
Background
Low dropout linear regulators (Low Dropout Regulator, LDOs) are currently the most widely used power management circuits in electronic products. In order to make the LDO work normally and stably, the power supply voltage of the chip rises slowly from zero, and after the minimum working voltage is reached, the chip starts to work normally. In some special devices, the output current of the chip increases and the power supply voltage of the chip fluctuates due to the operation of the functional module inside the chip. When the power supply voltage is too low, the internal circuit of the chip can generate great power consumption, and when the power supply voltage is too high, the output end can be overcharged, so that the internal circuit of the chip is burnt out and the stability of the whole circuit system is affected. Therefore, in order to ensure that the LDO operates normally, an under-voltage lockout (Under Voltage Lock Out, UVLO) circuit needs to be added in the circuit design to ensure that the loop can only output a normal value when the power supply is above the UVLO threshold, i.e., to ensure that the circuit is in a protected state when the input voltage is below the minimum operating voltage.
The most used scheme of the prior UVLO circuit is to compare the divided voltage of the input voltage with the reference voltage, judge whether the circuit is under voltage or not, and shut off the circuit at the rear end when the comparison voltage is lower than the reference voltage, so as to achieve the purpose of protecting the circuit. Although this approach can effectively protect the circuit, it has certain drawbacks: the structure inside the circuit is too complex, and the internal power consumption is larger because the UVLO module is added when the circuit works, so that the design cost and difficulty of the circuit are obviously increased.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a simple UVLO protection circuit, which is mainly used in the related protection circuit field to solve the technical problems in the related field.
The technical scheme adopted for solving the technical problems is as follows:
The UVLO protection circuit comprises a P-channel enhancement type MOS tube M1, a P-channel enhancement type MOS tube M2, N-channel enhancement type MOS tubes M3-M5, a reference circuit module, a filter capacitor C, an input Vcc port and an Vout port, wherein the Vcc port is connected with an external input power supply end, and the Vout port is a reference output port of the UVLO protection circuit.
The source electrode of the P-channel enhancement type MOS tube M1 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode of the P-channel enhancement type MOS tube M2, and the drain electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode of the P-channel enhancement type MOS tube M2; the source electrode of the P-channel enhancement type MOS tube M2 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M2 is connected with the grid electrode of the P-channel enhancement type MOS tube M1, and the drain electrode of the P-channel enhancement type MOS tube M2 is connected with the drain electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the N-channel enhancement type MOS tube M5.
The source electrode of the N-channel enhancement type MOS tube M3 is grounded, the grid electrode of the N-channel enhancement type MOS tube M3 is connected with the grid electrode of the N-channel enhancement type MOS tube M4, and the drain electrode of the N-channel enhancement type MOS tube M3 is connected with the grid electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the N-channel enhancement type MOS tube M3; the source electrode of the N-channel enhancement type MOS tube M4 is grounded, the grid electrode of the N-channel enhancement type MOS tube M4 is connected with the grid electrode and the drain electrode of the N-channel enhancement type MOS tube M3, and the drain electrode of the N-channel enhancement type MOS tube M4 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the grid electrode of the N-channel enhancement type MOS tube M5.
The P-channel enhancement MOS transistors M1 and M2 form a pull-up current mirror module, the N-channel enhancement MOS transistors M3 and M4 form a pull-down current mirror module, and the pull-up current mirror module and the pull-down current mirror module jointly form an output stage of the current mirror comparator.
The grid electrode of the N-channel enhancement type MOS tube M5 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the drain electrode of the N-channel enhancement type MOS tube M4, the drain electrode of the N-channel enhancement type MOS tube M5 is connected with the output end of the reference circuit, and the source electrode of the N-channel enhancement type MOS tube M5 is connected with the positive plate of the filter capacitor C and the output Vout port of the whole circuit.
And the output end of the reference circuit module is connected with the drain electrode of the N-channel enhancement type MOS tube M5.
The positive plate of the filter capacitor C is connected with the source electrode of the N-channel enhancement type MOS tube M5, and the negative plate of the filter capacitor C is grounded.
With reference to fig. 1, the overall circuit has the following working mechanism: the sum of the reference voltage VBG generated by the reference circuit and the threshold voltage VTH5 of the N-channel enhancement MOS tube M5 forms the threshold voltage of UVLO, namely when the gate voltage of the N-channel enhancement MOS tube M5 reaches the threshold voltage of UVLO, the source-drain end of the N-channel enhancement MOS tube M5 is conducted, the circuit output end Vout outputs the reference voltage VBG, in order to avoid the over-influence of the power supply voltage directly connected to the grid of the N-channel enhancement MOS tube M5 on PSRR of the circuit, a pull-up current mirror circuit is formed by the P-channel enhancement MOS tube M1 and the N-channel enhancement MOS tube M2, a pull-down current mirror is formed by the N-channel enhancement MOS tube M3 and the N-channel enhancement MOS tube M4, the output ends of the two current mirrors are compared to form an output stage of a current mirror comparator, the number ratio of the P-channel enhancement MOS tube M1 to the P-channel enhancement MOS tube M2 is assumed to be M1, the drain current of the N-channel enhancement MOS tube M3 is IB2, and the number ratio of the N-channel enhancement MOS tube M2 to the N-channel enhancement MOS tube M4 is represented by the formula of the pull-down current capability of the N-channel enhancement MOS tube M2 in the pull-down current enhancement MOS tube 2:
mIB1＞nIB2 (1)
In the formula (1), IB1 is leakage current of a P-channel enhanced M1 tube, IB2 is leakage current of an N-channel enhanced M3 tube, M is the number ratio of the P-channel enhanced M2 tube to the M1 tube, and N is the number ratio of the N-channel enhanced M4 tube to the M3 tube;
Because the source-drain voltage VDS2 of the N-channel enhancement MOS tube M2 is very small, the gate voltage of the N-channel enhancement MOS tube M5 is close to Vcc. By doing so, on one hand, the voltage of Vout is not affected to approach the VBG voltage, and on the other hand, the PSRR of Vout is not greatly affected.
When the input power supply voltage Vcc is greater than the sum of the source-drain voltages VDS2 and UVLO of the P-channel enhancement MOS transistor M2, it is expressed by the following disclosure:
VCC＞VDS2+VTH5+VBG (2)
At this time, the whole circuit reaches the threshold of UVLO, the whole circuit starts to start, and the Vout end outputs the reference voltage VBG.
The invention has the beneficial effects that:
1. The whole circuit is simple in design, only one NMOS tube is needed to be added between the reference circuit and the filter capacitor, the threshold voltage of UVLO is formed by the sum of the threshold voltage of the NMOS tube and the reference voltage, the circuit only outputs after the grid voltage of the NMOS tube is larger than the threshold voltage of UVLO, and otherwise the circuit is always in a UVLO protection state.
2. After the power supply voltage forms the output stage of the current mirror comparator through the pull-up current mirror and the pull-down current mirror, the output voltage of the current mirror comparator is almost close to the voltage of the power supply terminal because the pull-up current capacity of the circuit is far greater than the pull-down current capacity, and the voltage is transmitted to the grid electrode of the NMOS tube, so that the PSRR value of the circuit is not affected.
Drawings
Fig. 1 is a schematic diagram of a UVLO protection circuit according to the present invention.
Detailed Description
The invention will be further described with reference to the drawings and examples.
The invention provides a simple UVLO protection circuit, which mainly adopts an N-channel enhancement type MOS tube added between the output end of a reference circuit and an output filter capacitor, wherein the UVLO threshold voltage is formed by the sum of the threshold voltage of the N-channel enhancement type MOS tube and the reference voltage output by a reference circuit module, and the whole circuit only has output voltage after the input power end reaches that the grid voltage of the N-channel enhancement type MOS tube is larger than the UVLO threshold voltage through an internal buffer circuit. The method is simple in circuit design and low in cost, has a good inhibition effect on circuit overcharge, is low in internal power consumption, and has a good undervoltage protection effect on an LDO circuit.
The specific technical scheme of the UVLO protection circuit is as follows:
The UVLO protection circuit comprises a P-channel enhancement type MOS tube M1, a P-channel enhancement type MOS tube M2, N-channel enhancement type MOS tubes M3-M5, a reference circuit module, a filter capacitor C, an input Vcc port and an Vout port, wherein the Vcc port is connected with an external input power supply end, and the Vout port is a reference output port of the UVLO protection circuit.
The source electrode of the P-channel enhancement type MOS tube M1 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode of the P-channel enhancement type MOS tube M2, and the drain electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode of the P-channel enhancement type MOS tube M2; the source electrode of the P-channel enhancement type MOS tube M2 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M2 is connected with the grid electrode of the P-channel enhancement type MOS tube M1, and the drain electrode of the P-channel enhancement type MOS tube M2 is connected with the drain electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the N-channel enhancement type MOS tube M5.
The source electrode of the N-channel enhancement type MOS tube M3 is grounded, the grid electrode of the N-channel enhancement type MOS tube M3 is connected with the grid electrode of the N-channel enhancement type MOS tube M4, and the drain electrode of the N-channel enhancement type MOS tube M3 is connected with the grid electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the N-channel enhancement type MOS tube M3; the source electrode of the N-channel enhancement type MOS tube M4 is grounded, the grid electrode of the N-channel enhancement type MOS tube M4 is connected with the grid electrode and the drain electrode of the N-channel enhancement type MOS tube M3, and the drain electrode of the N-channel enhancement type MOS tube M4 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the grid electrode of the N-channel enhancement type MOS tube M5.
The P-channel enhancement MOS transistors M1 and M2 form a pull-up current mirror module, the N-channel enhancement MOS transistors M3 and M4 form a pull-down current mirror module, and the pull-up current mirror module and the pull-down current mirror module jointly form an output stage of the current mirror comparator.
The grid electrode of the N-channel enhancement type MOS tube M5 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the drain electrode of the N-channel enhancement type MOS tube M4, the drain electrode of the N-channel enhancement type MOS tube M5 is connected with the output end of the reference circuit, and the source electrode of the N-channel enhancement type MOS tube M5 is connected with the positive plate of the filter capacitor C and the output Vout port of the whole circuit.
And the output end of the reference circuit module is connected with the drain electrode of the N-channel enhancement type MOS tube M5.
The positive plate of the filter capacitor C is connected with the source electrode of the N-channel enhancement type MOS tube M5, and the negative plate of the filter capacitor C is grounded.
With reference to fig. 1, the overall circuit has the following working mechanism: the sum of the reference voltage VBG generated by the reference circuit and the threshold voltage VTH5 of the N-channel enhancement MOS tube M5 forms the threshold voltage of UVLO, namely when the gate voltage of the N-channel enhancement MOS tube M5 reaches the threshold voltage of UVLO, the source-drain end of the N-channel enhancement MOS tube M5 is conducted, the circuit output end Vout outputs the reference voltage VBG, in order to avoid the over-influence of the power supply voltage directly connected to the grid of the N-channel enhancement MOS tube M5 on PSRR of the circuit, a pull-up current mirror circuit is formed by the P-channel enhancement MOS tube M1 and the N-channel enhancement MOS tube M2, a pull-down current mirror is formed by the N-channel enhancement MOS tube M3 and the N-channel enhancement MOS tube M4, the output ends of the two current mirrors are compared to form an output stage of a current mirror comparator, the number ratio of the P-channel enhancement MOS tube M1 to the P-channel enhancement MOS tube M2 is assumed to be M1, the drain current of the N-channel enhancement MOS tube M3 is IB2, and the number ratio of the N-channel enhancement MOS tube M2 to the N-channel enhancement MOS tube M4 is represented by the formula of the pull-down current capability of the N-channel enhancement MOS tube M2 in the pull-down current enhancement MOS tube 2:
mIB1＞nIB2 (1)
In the formula (1), IB1 is leakage current of a P-channel enhanced M1 tube, IB2 is leakage current of an N-channel enhanced M3 tube, M is the number ratio of the P-channel enhanced M2 tube to the M1 tube, and N is the number ratio of the N-channel enhanced M4 tube to the M3 tube;
Because the source-drain voltage VDS2 of the N-channel enhancement MOS tube M2 is very small, the gate voltage of the N-channel enhancement MOS tube M5 is close to Vcc. By doing so, on one hand, the voltage of Vout is not affected to approach the VBG voltage, and on the other hand, the PSRR of Vout is not greatly affected.
When the input power supply voltage Vcc is greater than the sum of the source-drain voltages VDS2 and UVLO of the P-channel enhancement MOS transistor M2, it is expressed by the following disclosure:
VCC＞VDS2+VTH5+VBG (2)
At this time, the whole circuit reaches the threshold of UVLO, the whole circuit starts to start, and the Vout end outputs the reference voltage VBG.
As shown in FIG. 1, the invention mainly comprises P-channel enhancement type MOS transistors M1 and M2, N-channel enhancement type MOS transistors M3-M5, a reference circuit module, a filter capacitor C, an input Vcc port and an output Vout port. The Vcc port is connected with an external input power supply end, and the Vout port is an integral circuit reference output port.
The source electrode of the P-channel enhancement type MOS tube M1 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M2 is connected with the grid electrode of the P-channel enhancement type MOS tube M2, and the drain electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode of the P-channel enhancement type MOS tube M2 and the grid electrode of the PMOS tube M2; the source electrode of the P-channel enhancement type MOS tube M2 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode, and the drain electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the N-channel enhancement type MOS tube M5 are connected with the drain electrode.
The source electrode of the N-channel enhancement type MOS tube M3 is grounded, the grid electrode of the N-channel enhancement type MOS tube M4 is connected with the grid electrode, and the drain electrode of the N-channel enhancement type MOS tube M3 is connected with the grid electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the M4 tube; the source electrode of the N-channel enhancement type MOS tube M4 is grounded, the grid electrode is connected with the grid electrode and the drain electrode of the M3, and the drain electrode of the M4 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the grid electrode of the N-channel enhancement type MOS tube M5.
The P-channel enhancement MOS transistors M1 and M2 form a pull-up current mirror module, the N-channel enhancement MOS transistors M3 and M4 form a pull-down current mirror module, and the pull-up current mirror module and the pull-down current mirror module form an output stage of the current mirror comparator together.
The grid electrode of the N-channel enhancement type MOS tube M5 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the drain electrode of the N-channel enhancement type MOS tube M4, the drain electrode is connected with the output end of the reference circuit, and the source electrode is connected with the positive plate of the filter capacitor C and the output Vout port of the whole circuit.
And the output end of the reference circuit module is connected with the drain electrode of the N-channel enhancement type MOS tube M5.
The positive plate of the filter capacitor C is connected with the source electrode of the N-channel enhancement type MOS tube M5.
With reference to fig. 1, the overall circuit has the following working mechanism: the sum of the reference voltage V BG generated by the reference circuit and the threshold voltage V TH5 of the N-channel enhancement MOS transistor M5 forms the threshold voltage of UVLO, namely when the gate voltage of the N-channel enhancement MOS transistor M5 reaches the threshold voltage of UVLO, the source-drain end of the M5 transistor is conducted, and the circuit output end Vout outputs the reference voltage V BG. In order to avoid the excessive influence of the power supply voltage directly connected to the grid electrode of the N-channel enhancement type MOS tube M5 on the PSRR of the circuit, a pull-up current mirror circuit is formed by the P-channel enhancement type MOS tubes M1 and M2, and a pull-down current mirror is formed by the N-channel enhancement type MOS tubes M3 and M4, and the output ends of the two current mirrors are compared to form an output stage of the current mirror comparator. Assuming that the drain current of the P-channel enhancement MOS tube M1 is I B1, the number ratio of the tube of the P-channel enhancement MOS tube M2 to the tube of the M1 is m:1, the drain current of the N-channel enhancement MOS tube M3 is I B2, and the number ratio of the tube of the N-channel enhancement MOS tube M2 to the tube of the M4 is n:1, because the pull-up current capacity of the P-channel enhancement MOS tube M2 is larger than the pull-down current capacity of the N-channel enhancement MOS tube M4 in the circuit, the formula is used for expression:
mIB1＞nIB2 (3)
wherein I B1 is leakage current of the P channel enhancement type M1 tube, I B2 is leakage current of the N channel enhancement type M3 tube, M is the number ratio of the P channel enhancement type M2 tube to the M1 tube, and N is the number ratio of the N channel enhancement type M4 tube to the M3 tube.
Because the source-drain voltage V DS2 of the N-channel enhancement MOS tube M2 is very small, the gate voltage of the N-channel enhancement MOS tube M5 is close to Vcc. By doing so, on one hand, the voltage of Vout is not affected to approach the voltage of V BG, and on the other hand, the PSRR of Vout is not affected too much.
The above is that when the input power voltage Vcc is greater than the sum of the source-drain voltage V DS2 of the P-channel enhancement MOS transistor M2 and the threshold voltage of the UVLO, expressed by the following general expression:
VCC＞VDS2+VTH5+VBG (4)
at this time, the whole circuit reaches the threshold of UVLO, the whole circuit starts to start, and the Vout end outputs the reference voltage V BG.
In summary, the technology of the invention provides a simple UVLO protection circuit which can effectively perform under-voltage protection and ensure that PSRR of the circuit is not affected. Compared with the prior UVLO protection circuit, the method has the advantages that the whole circuit design is simple, the circuit overcharge is well inhibited, the internal power consumption of the circuit is small, and the undervoltage protection effect on other circuits is well achieved.
Claims (1)
1. A UVLO protection circuit, characterized by:
the UVLO protection circuit comprises a P-channel enhancement type MOS tube M1, a P-channel enhancement type MOS tube M2, N-channel enhancement type MOS tubes M3-M5, a reference circuit module, a filter capacitor C, an input Vcc port and an Vout port, wherein the Vcc port is connected with an external input power supply end, and the Vout port is a reference output port of the UVLO protection circuit;
The source electrode of the P-channel enhancement type MOS tube M1 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode of the P-channel enhancement type MOS tube M2, and the drain electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode of the P-channel enhancement type MOS tube M2; the source electrode of the P-channel enhancement type MOS tube M2 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M2 is connected with the grid electrode of the P-channel enhancement type MOS tube M1, and the drain electrode of the P-channel enhancement type MOS tube M2 is connected with the drain electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the N-channel enhancement type MOS tube M5;
The source electrode of the N-channel enhancement type MOS tube M3 is grounded, the grid electrode of the N-channel enhancement type MOS tube M3 is connected with the grid electrode of the N-channel enhancement type MOS tube M4, and the drain electrode of the N-channel enhancement type MOS tube M3 is connected with the grid electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the N-channel enhancement type MOS tube M3; the source electrode of the N-channel enhancement type MOS tube M4 is grounded, the grid electrode of the N-channel enhancement type MOS tube M4 is connected with the grid electrode and the drain electrode of the N-channel enhancement type MOS tube M3, and the drain electrode of the N-channel enhancement type MOS tube M4 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the grid electrode of the N-channel enhancement type MOS tube M5;
The P-channel enhancement MOS transistors M1 and M2 form a pull-up current mirror module, the N-channel enhancement MOS transistors M3 and M4 form a pull-down current mirror module, and the pull-up current mirror module and the pull-down current mirror module form an output stage of the current mirror comparator together;
The grid electrode of the N-channel enhancement type MOS tube M5 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the drain electrode of the N-channel enhancement type MOS tube M4, the drain electrode of the N-channel enhancement type MOS tube M5 is connected with the output end of the reference circuit, and the source electrode of the N-channel enhancement type MOS tube M5 is connected with the positive plate of the filter capacitor C and the output Vout port of the whole circuit;
the output end of the reference circuit module is connected with the drain electrode of the N-channel enhancement MOS tube M5;
The positive plate of the filter capacitor C is connected with the source electrode of the N-channel enhancement type MOS tube M5, and the negative plate of the filter capacitor C is grounded;
The working mechanism of the UVLO protection circuit is as follows: the sum of a reference voltage V BG generated by a reference circuit and a threshold voltage V TH5 of an N-channel enhancement type MOS tube M5 forms a threshold voltage of UVLO, namely when the gate voltage of the N-channel enhancement type MOS tube M5 reaches the threshold voltage of UVLO, a source-drain end of the N-channel enhancement type MOS tube M5 is conducted, a circuit output end Vout outputs the reference voltage V BG, in order to avoid that the power supply voltage is directly connected to the gate of the N-channel enhancement type MOS tube M5 to greatly affect PSRR of the circuit, a pull-up current mirror circuit is formed by a P-channel enhancement type MOS tube M1 and a N-channel enhancement type MOS tube M4, the output ends of the two current mirrors are compared to form an output stage of a current mirror comparator, the number ratio of the P-channel enhancement type MOS tube M1 to the P-channel enhancement type MOS tube M1 is M B1, the drain current of the N-channel enhancement type MOS tube M3 is I B2, and the number of the N-channel enhancement type MOS tube M2 to the number of the P-channel enhancement type MOS tube M4 is M2, and the number of the N-channel enhancement type MOS tube M2 is expressed in the pull-down current can be larger than that of the N-channel enhancement type MOS tube M2 is in the pull-down current enhancement type MOS tube 2, and the number of the pull-up current can be expressed in the N-channel enhancement type MOS tube is represented by the formula:
mIB1＞nIB2 (1)
I B1 in the formula (1) is leakage current of a P-channel enhanced M1 pipe, I B2 is leakage current of an N-channel enhanced M3 pipe, M is the number ratio of the P-channel enhanced M2 pipe to the M1 pipe, and N is the number ratio of the N-channel enhanced M4 pipe to the M3 pipe;
Because the source-drain voltage V DS2 of the N-channel enhancement MOS tube M2 is very small, the gate voltage of the N-channel enhancement MOS tube M5 is close to Vcc, when the input power supply voltage Vcc is larger than the sum of the source-drain voltage V DS2 of the P-channel enhancement MOS tube M2 and the threshold voltage of UVLO, the voltage is expressed by the formula:
VCC＞VDS2+VTH5+VBG (2)
at this time, the whole circuit reaches the threshold of UVLO, the whole circuit starts to start, and the Vout terminal outputs the reference voltage V BG.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811313209.8A CN109283963B (en) | 2018-11-06 | 2018-11-06 | UVLO protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811313209.8A CN109283963B (en) | 2018-11-06 | 2018-11-06 | UVLO protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109283963A CN109283963A (en) | 2019-01-29 |
| CN109283963B true CN109283963B (en) | 2024-06-14 |
Family
ID=65174547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811313209.8A Active CN109283963B (en) | 2018-11-06 | 2018-11-06 | UVLO protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109283963B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110011526B (en) * | 2019-04-22 | 2024-03-12 | 拓尔微电子股份有限公司 | Voltage control-based UVLO protection circuit applied to EA circuit |
| CN117095635A (en) * | 2023-09-18 | 2023-11-21 | 欣瑞华微电子(上海)有限公司 | Display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN209044408U (en) * | 2018-11-06 | 2019-06-28 | 西安拓尔微电子有限责任公司 | A kind of UVLO protection circuit |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62274926A (en) * | 1986-05-23 | 1987-11-28 | Nec Corp | Cmos circuit |
| JPH0628012B2 (en) * | 1986-06-11 | 1994-04-13 | 日本電気株式会社 | Constant voltage generator |
| US5187389A (en) * | 1991-05-03 | 1993-02-16 | National Semiconductor Corporation | Noise resistant low voltage brownout detector with shut off option |
| CN101499644B (en) * | 2008-02-02 | 2013-10-02 | 华润矽威科技（上海）有限公司 | Under-voltage protection circuit with low starting current |
| CN101854163A (en) * | 2009-03-30 | 2010-10-06 | 登丰微电子股份有限公司 | Voltage detection starter and controller |
| KR20180072313A (en) * | 2016-12-21 | 2018-06-29 | 에스케이하이닉스 주식회사 | Capacitance sensing circuits |
| CN107066003A (en) * | 2016-12-30 | 2017-08-18 | 西南技术物理研究所 | Low-power-consumptioreference reference voltage source |
| CN106774595A (en) * | 2017-01-09 | 2017-05-31 | 电子科技大学 | A kind of current foldback circuit for low pressure difference linear voltage regulator |
| CN107967022B (en) * | 2018-01-19 | 2023-11-03 | 桂林电子科技大学 | Dual-output low-temperature drift reference voltage source |
| CN107992159B (en) * | 2018-01-19 | 2023-11-03 | 桂林电子科技大学 | Three-output low-temperature drift low-power consumption reference voltage source |
-
2018
- 2018-11-06 CN CN201811313209.8A patent/CN109283963B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN209044408U (en) * | 2018-11-06 | 2019-06-28 | 西安拓尔微电子有限责任公司 | A kind of UVLO protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109283963A (en) | 2019-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20230130733A1 (en) | Low dropout linear regulator and control circuit thereof | |
| US20130169246A1 (en) | Linear voltage regulating circuit adaptable to a logic system | |
| CN106873697B (en) | A kind of fast response circuit and method for low pressure difference linear voltage regulator | |
| CN109782838A (en) | A kind of fast transient response LDO regulator circuit based on phase inverter | |
| CN104914909A (en) | Power control device and method | |
| CN109283963B (en) | UVLO protection circuit | |
| CN113434002B (en) | High-voltage low dropout regulator (LDO) circuit with clamping current-limiting function | |
| US11522360B2 (en) | Control method of susceptible inrush currents passing through a load switch, and corresponding electronic circuit | |
| CN110568895A (en) | Circuit for LDO adaptive leakage compensation | |
| Li et al. | A fully on-chip digitally assisted LDO regulator with improved regulation and transient responses | |
| CN115903985A (en) | Current limiting circuit suitable for LDO circuit with wide input voltage range | |
| US20120049817A1 (en) | Current generator circuit | |
| CN102789255A (en) | Turn-threshold-adjustable under voltage lockout (UVLO) and reference voltage circuit | |
| CN209044408U (en) | A kind of UVLO protection circuit | |
| CN103955251A (en) | High-voltage linear voltage regulator | |
| CN103269217A (en) | Output buffer | |
| CN212586761U (en) | Easy-to-integrate voltage stabilizing circuit based on low-voltage amplifier | |
| CN115529029A (en) | Voltage comparator circuit | |
| CN105577165B (en) | A kind of I/O interface level shifting circuit and I/O interface level conversion method | |
| CN112947664A (en) | Temperature self-adaptive voltage source | |
| CN116169637B (en) | Low-power consumption undervoltage locking protection circuit suitable for high-voltage LDO | |
| CN110011526B (en) | Voltage control-based UVLO protection circuit applied to EA circuit | |
| CN113093853B (en) | Improved LDO circuit for realizing low input/output voltage difference in low-voltage starting process | |
| CN211830191U (en) | Under-voltage locking circuit | |
| US10148182B2 (en) | Voltage conversion circuit with bleed module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Applicant after: Xi'an Tuoer Microelectronics Co.,Ltd. Address before: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Applicant before: XI'AN TUOER MICROELECTRONICS Co.,Ltd. Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Applicant after: Tuoer Microelectronics Co.,Ltd. Address before: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Applicant before: Xi'an Tuoer Microelectronics Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |