Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a simple UVLO protection circuit, which is mainly used in the related protection circuit field to solve the technical problems in the related field.
The technical scheme adopted for solving the technical problems is as follows:
The UVLO protection circuit comprises a P-channel enhancement type MOS tube M1, a P-channel enhancement type MOS tube M2, N-channel enhancement type MOS tubes M3-M5, a reference circuit module, a filter capacitor C, an input Vcc port and an Vout port, wherein the Vcc port is connected with an external input power supply end, and the Vout port is a reference output port of the UVLO protection circuit.
The source electrode of the P-channel enhancement type MOS tube M1 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode of the P-channel enhancement type MOS tube M2, and the drain electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode of the P-channel enhancement type MOS tube M2; the source electrode of the P-channel enhancement type MOS tube M2 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M2 is connected with the grid electrode of the P-channel enhancement type MOS tube M1, and the drain electrode of the P-channel enhancement type MOS tube M2 is connected with the drain electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the N-channel enhancement type MOS tube M5.
The source electrode of the N-channel enhancement type MOS tube M3 is grounded, the grid electrode of the N-channel enhancement type MOS tube M3 is connected with the grid electrode of the N-channel enhancement type MOS tube M4, and the drain electrode of the N-channel enhancement type MOS tube M3 is connected with the grid electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the N-channel enhancement type MOS tube M3; the source electrode of the N-channel enhancement type MOS tube M4 is grounded, the grid electrode of the N-channel enhancement type MOS tube M4 is connected with the grid electrode and the drain electrode of the N-channel enhancement type MOS tube M3, and the drain electrode of the N-channel enhancement type MOS tube M4 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the grid electrode of the N-channel enhancement type MOS tube M5.
The P-channel enhancement MOS transistors M1 and M2 form a pull-up current mirror module, the N-channel enhancement MOS transistors M3 and M4 form a pull-down current mirror module, and the pull-up current mirror module and the pull-down current mirror module jointly form an output stage of the current mirror comparator.
The grid electrode of the N-channel enhancement type MOS tube M5 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the drain electrode of the N-channel enhancement type MOS tube M4, the drain electrode of the N-channel enhancement type MOS tube M5 is connected with the output end of the reference circuit, and the source electrode of the N-channel enhancement type MOS tube M5 is connected with the positive plate of the filter capacitor C and the output Vout port of the whole circuit.
And the output end of the reference circuit module is connected with the drain electrode of the N-channel enhancement type MOS tube M5.
The positive plate of the filter capacitor C is connected with the source electrode of the N-channel enhancement type MOS tube M5, and the negative plate of the filter capacitor C is grounded.
With reference to fig. 1, the overall circuit has the following working mechanism: the sum of the reference voltage VBG generated by the reference circuit and the threshold voltage VTH5 of the N-channel enhancement MOS tube M5 forms the threshold voltage of UVLO, namely when the gate voltage of the N-channel enhancement MOS tube M5 reaches the threshold voltage of UVLO, the source-drain end of the N-channel enhancement MOS tube M5 is conducted, the circuit output end Vout outputs the reference voltage VBG, in order to avoid the over-influence of the power supply voltage directly connected to the grid of the N-channel enhancement MOS tube M5 on PSRR of the circuit, a pull-up current mirror circuit is formed by the P-channel enhancement MOS tube M1 and the N-channel enhancement MOS tube M2, a pull-down current mirror is formed by the N-channel enhancement MOS tube M3 and the N-channel enhancement MOS tube M4, the output ends of the two current mirrors are compared to form an output stage of a current mirror comparator, the number ratio of the P-channel enhancement MOS tube M1 to the P-channel enhancement MOS tube M2 is assumed to be M1, the drain current of the N-channel enhancement MOS tube M3 is IB2, and the number ratio of the N-channel enhancement MOS tube M2 to the N-channel enhancement MOS tube M4 is represented by the formula of the pull-down current capability of the N-channel enhancement MOS tube M2 in the pull-down current enhancement MOS tube 2:
mIB1>nIB2 (1)
In the formula (1), IB1 is leakage current of a P-channel enhanced M1 tube, IB2 is leakage current of an N-channel enhanced M3 tube, M is the number ratio of the P-channel enhanced M2 tube to the M1 tube, and N is the number ratio of the N-channel enhanced M4 tube to the M3 tube;
Because the source-drain voltage VDS2 of the N-channel enhancement MOS tube M2 is very small, the gate voltage of the N-channel enhancement MOS tube M5 is close to Vcc. By doing so, on one hand, the voltage of Vout is not affected to approach the VBG voltage, and on the other hand, the PSRR of Vout is not greatly affected.
When the input power supply voltage Vcc is greater than the sum of the source-drain voltages VDS2 and UVLO of the P-channel enhancement MOS transistor M2, it is expressed by the following disclosure:
VCC>VDS2+VTH5+VBG (2)
At this time, the whole circuit reaches the threshold of UVLO, the whole circuit starts to start, and the Vout end outputs the reference voltage VBG.
The invention has the beneficial effects that:
1. The whole circuit is simple in design, only one NMOS tube is needed to be added between the reference circuit and the filter capacitor, the threshold voltage of UVLO is formed by the sum of the threshold voltage of the NMOS tube and the reference voltage, the circuit only outputs after the grid voltage of the NMOS tube is larger than the threshold voltage of UVLO, and otherwise the circuit is always in a UVLO protection state.
2. After the power supply voltage forms the output stage of the current mirror comparator through the pull-up current mirror and the pull-down current mirror, the output voltage of the current mirror comparator is almost close to the voltage of the power supply terminal because the pull-up current capacity of the circuit is far greater than the pull-down current capacity, and the voltage is transmitted to the grid electrode of the NMOS tube, so that the PSRR value of the circuit is not affected.
Detailed Description
The invention will be further described with reference to the drawings and examples.
The invention provides a simple UVLO protection circuit, which mainly adopts an N-channel enhancement type MOS tube added between the output end of a reference circuit and an output filter capacitor, wherein the UVLO threshold voltage is formed by the sum of the threshold voltage of the N-channel enhancement type MOS tube and the reference voltage output by a reference circuit module, and the whole circuit only has output voltage after the input power end reaches that the grid voltage of the N-channel enhancement type MOS tube is larger than the UVLO threshold voltage through an internal buffer circuit. The method is simple in circuit design and low in cost, has a good inhibition effect on circuit overcharge, is low in internal power consumption, and has a good undervoltage protection effect on an LDO circuit.
The specific technical scheme of the UVLO protection circuit is as follows:
The UVLO protection circuit comprises a P-channel enhancement type MOS tube M1, a P-channel enhancement type MOS tube M2, N-channel enhancement type MOS tubes M3-M5, a reference circuit module, a filter capacitor C, an input Vcc port and an Vout port, wherein the Vcc port is connected with an external input power supply end, and the Vout port is a reference output port of the UVLO protection circuit.
The source electrode of the P-channel enhancement type MOS tube M1 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode of the P-channel enhancement type MOS tube M2, and the drain electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode of the P-channel enhancement type MOS tube M2; the source electrode of the P-channel enhancement type MOS tube M2 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M2 is connected with the grid electrode of the P-channel enhancement type MOS tube M1, and the drain electrode of the P-channel enhancement type MOS tube M2 is connected with the drain electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the N-channel enhancement type MOS tube M5.
The source electrode of the N-channel enhancement type MOS tube M3 is grounded, the grid electrode of the N-channel enhancement type MOS tube M3 is connected with the grid electrode of the N-channel enhancement type MOS tube M4, and the drain electrode of the N-channel enhancement type MOS tube M3 is connected with the grid electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the N-channel enhancement type MOS tube M3; the source electrode of the N-channel enhancement type MOS tube M4 is grounded, the grid electrode of the N-channel enhancement type MOS tube M4 is connected with the grid electrode and the drain electrode of the N-channel enhancement type MOS tube M3, and the drain electrode of the N-channel enhancement type MOS tube M4 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the grid electrode of the N-channel enhancement type MOS tube M5.
The P-channel enhancement MOS transistors M1 and M2 form a pull-up current mirror module, the N-channel enhancement MOS transistors M3 and M4 form a pull-down current mirror module, and the pull-up current mirror module and the pull-down current mirror module jointly form an output stage of the current mirror comparator.
The grid electrode of the N-channel enhancement type MOS tube M5 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the drain electrode of the N-channel enhancement type MOS tube M4, the drain electrode of the N-channel enhancement type MOS tube M5 is connected with the output end of the reference circuit, and the source electrode of the N-channel enhancement type MOS tube M5 is connected with the positive plate of the filter capacitor C and the output Vout port of the whole circuit.
And the output end of the reference circuit module is connected with the drain electrode of the N-channel enhancement type MOS tube M5.
The positive plate of the filter capacitor C is connected with the source electrode of the N-channel enhancement type MOS tube M5, and the negative plate of the filter capacitor C is grounded.
With reference to fig. 1, the overall circuit has the following working mechanism: the sum of the reference voltage VBG generated by the reference circuit and the threshold voltage VTH5 of the N-channel enhancement MOS tube M5 forms the threshold voltage of UVLO, namely when the gate voltage of the N-channel enhancement MOS tube M5 reaches the threshold voltage of UVLO, the source-drain end of the N-channel enhancement MOS tube M5 is conducted, the circuit output end Vout outputs the reference voltage VBG, in order to avoid the over-influence of the power supply voltage directly connected to the grid of the N-channel enhancement MOS tube M5 on PSRR of the circuit, a pull-up current mirror circuit is formed by the P-channel enhancement MOS tube M1 and the N-channel enhancement MOS tube M2, a pull-down current mirror is formed by the N-channel enhancement MOS tube M3 and the N-channel enhancement MOS tube M4, the output ends of the two current mirrors are compared to form an output stage of a current mirror comparator, the number ratio of the P-channel enhancement MOS tube M1 to the P-channel enhancement MOS tube M2 is assumed to be M1, the drain current of the N-channel enhancement MOS tube M3 is IB2, and the number ratio of the N-channel enhancement MOS tube M2 to the N-channel enhancement MOS tube M4 is represented by the formula of the pull-down current capability of the N-channel enhancement MOS tube M2 in the pull-down current enhancement MOS tube 2:
mIB1>nIB2 (1)
In the formula (1), IB1 is leakage current of a P-channel enhanced M1 tube, IB2 is leakage current of an N-channel enhanced M3 tube, M is the number ratio of the P-channel enhanced M2 tube to the M1 tube, and N is the number ratio of the N-channel enhanced M4 tube to the M3 tube;
Because the source-drain voltage VDS2 of the N-channel enhancement MOS tube M2 is very small, the gate voltage of the N-channel enhancement MOS tube M5 is close to Vcc. By doing so, on one hand, the voltage of Vout is not affected to approach the VBG voltage, and on the other hand, the PSRR of Vout is not greatly affected.
When the input power supply voltage Vcc is greater than the sum of the source-drain voltages VDS2 and UVLO of the P-channel enhancement MOS transistor M2, it is expressed by the following disclosure:
VCC>VDS2+VTH5+VBG (2)
At this time, the whole circuit reaches the threshold of UVLO, the whole circuit starts to start, and the Vout end outputs the reference voltage VBG.
As shown in FIG. 1, the invention mainly comprises P-channel enhancement type MOS transistors M1 and M2, N-channel enhancement type MOS transistors M3-M5, a reference circuit module, a filter capacitor C, an input Vcc port and an output Vout port. The Vcc port is connected with an external input power supply end, and the Vout port is an integral circuit reference output port.
The source electrode of the P-channel enhancement type MOS tube M1 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M2 is connected with the grid electrode of the P-channel enhancement type MOS tube M2, and the drain electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode of the P-channel enhancement type MOS tube M2 and the grid electrode of the PMOS tube M2; the source electrode of the P-channel enhancement type MOS tube M2 is connected with the Vcc end of an input power supply, the grid electrode of the P-channel enhancement type MOS tube M1 is connected with the grid electrode, and the drain electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the N-channel enhancement type MOS tube M5 are connected with the drain electrode.
The source electrode of the N-channel enhancement type MOS tube M3 is grounded, the grid electrode of the N-channel enhancement type MOS tube M4 is connected with the grid electrode, and the drain electrode of the N-channel enhancement type MOS tube M3 is connected with the grid electrode of the N-channel enhancement type MOS tube M4 and the grid electrode of the M4 tube; the source electrode of the N-channel enhancement type MOS tube M4 is grounded, the grid electrode is connected with the grid electrode and the drain electrode of the M3, and the drain electrode of the M4 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the grid electrode of the N-channel enhancement type MOS tube M5.
The P-channel enhancement MOS transistors M1 and M2 form a pull-up current mirror module, the N-channel enhancement MOS transistors M3 and M4 form a pull-down current mirror module, and the pull-up current mirror module and the pull-down current mirror module form an output stage of the current mirror comparator together.
The grid electrode of the N-channel enhancement type MOS tube M5 is connected with the drain electrode of the P-channel enhancement type MOS tube M2 and the drain electrode of the N-channel enhancement type MOS tube M4, the drain electrode is connected with the output end of the reference circuit, and the source electrode is connected with the positive plate of the filter capacitor C and the output Vout port of the whole circuit.
And the output end of the reference circuit module is connected with the drain electrode of the N-channel enhancement type MOS tube M5.
The positive plate of the filter capacitor C is connected with the source electrode of the N-channel enhancement type MOS tube M5.
With reference to fig. 1, the overall circuit has the following working mechanism: the sum of the reference voltage V BG generated by the reference circuit and the threshold voltage V TH5 of the N-channel enhancement MOS transistor M5 forms the threshold voltage of UVLO, namely when the gate voltage of the N-channel enhancement MOS transistor M5 reaches the threshold voltage of UVLO, the source-drain end of the M5 transistor is conducted, and the circuit output end Vout outputs the reference voltage V BG. In order to avoid the excessive influence of the power supply voltage directly connected to the grid electrode of the N-channel enhancement type MOS tube M5 on the PSRR of the circuit, a pull-up current mirror circuit is formed by the P-channel enhancement type MOS tubes M1 and M2, and a pull-down current mirror is formed by the N-channel enhancement type MOS tubes M3 and M4, and the output ends of the two current mirrors are compared to form an output stage of the current mirror comparator. Assuming that the drain current of the P-channel enhancement MOS tube M1 is I B1, the number ratio of the tube of the P-channel enhancement MOS tube M2 to the tube of the M1 is m:1, the drain current of the N-channel enhancement MOS tube M3 is I B2, and the number ratio of the tube of the N-channel enhancement MOS tube M2 to the tube of the M4 is n:1, because the pull-up current capacity of the P-channel enhancement MOS tube M2 is larger than the pull-down current capacity of the N-channel enhancement MOS tube M4 in the circuit, the formula is used for expression:
mIB1>nIB2 (3)
wherein I B1 is leakage current of the P channel enhancement type M1 tube, I B2 is leakage current of the N channel enhancement type M3 tube, M is the number ratio of the P channel enhancement type M2 tube to the M1 tube, and N is the number ratio of the N channel enhancement type M4 tube to the M3 tube.
Because the source-drain voltage V DS2 of the N-channel enhancement MOS tube M2 is very small, the gate voltage of the N-channel enhancement MOS tube M5 is close to Vcc. By doing so, on one hand, the voltage of Vout is not affected to approach the voltage of V BG, and on the other hand, the PSRR of Vout is not affected too much.
The above is that when the input power voltage Vcc is greater than the sum of the source-drain voltage V DS2 of the P-channel enhancement MOS transistor M2 and the threshold voltage of the UVLO, expressed by the following general expression:
VCC>VDS2+VTH5+VBG (4)
at this time, the whole circuit reaches the threshold of UVLO, the whole circuit starts to start, and the Vout end outputs the reference voltage V BG.
In summary, the technology of the invention provides a simple UVLO protection circuit which can effectively perform under-voltage protection and ensure that PSRR of the circuit is not affected. Compared with the prior UVLO protection circuit, the method has the advantages that the whole circuit design is simple, the circuit overcharge is well inhibited, the internal power consumption of the circuit is small, and the undervoltage protection effect on other circuits is well achieved.