CN208654282U - A kind of chip-detecting apparatus - Google Patents
A kind of chip-detecting apparatus Download PDFInfo
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- CN208654282U CN208654282U CN201821192438.4U CN201821192438U CN208654282U CN 208654282 U CN208654282 U CN 208654282U CN 201821192438 U CN201821192438 U CN 201821192438U CN 208654282 U CN208654282 U CN 208654282U
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Abstract
The utility model provides a kind of chip-detecting apparatus, comprising: simulated battery circuit, slowdown monitoring circuit to be checked, charging chip and charging current measuring circuit；Simulated battery circuit includes: supply port, the first control port, the first PMOS tube, the first NMOS tube, first resistor, second resistance, 3rd resistor, rectifier diode, simulated battery internal resistance and first capacitor；Slowdown monitoring circuit to be checked includes: the second control port, testing resistance, the second PMOS tube, the second NMOS tube, the 4th resistance, the 5th resistance, the 6th resistance and second output terminal；Charging chip is connected between second output terminal and ground；First detection incoming end of charging current measurement chip and the second detection incoming end are electrically connected to the both ends of circuit under test；The output end output voltage measured value of charging current measurement chip.It is whether normal that charging chip work can be monitored by the voltage measuring value of output.
Description
Technical field
The utility model relates to a kind of electronic technology field more particularly to a kind of chip-detecting apparatus.
Background technique
In order to guarantee the network bank business safety of user, bank can also issue intelligence to user when handling bank card for user
Energy encryption device, assists user to handle network bank business.User only uses intelligent cipher equipment ability when carrying out network bank business
Various pecuniary exchanges are completed, otherwise, client can prompt user to be inserted into intelligent cipher equipment.
Dependence with the fast development and network bank business of intelligent cipher equipment to intelligent cipher equipment, intelligent cipher are set
It is standby frequently to be used by user, especially often handle the user of wholesale network bank business.But since intelligent cipher equipment can not
Disassembly in order to which that improves intelligent cipher equipment uses cruise duration, mostly uses in the industry charging chip therefore, it is impossible to replace battery
To realize that the battery to intelligent cipher equipment charges.
And charging chip is produced in enormous quantities by the production line of factory, before coming into operation, in order to guarantee using
Charging chip in intelligent cipher equipment can achieve good charging ability, be badly in need of a kind of simply to charging chip work
Whether normal test mode.
Utility model content
The utility model aim to solve the problem that the above problem/one of.
The main purpose of the utility model is to provide a kind of chip-detecting apparatus.
In order to achieve the above objectives, the technical solution of the utility model is specifically achieved in that
On the one hand the utility model provides a kind of chip-detecting apparatus, comprising: simulated battery circuit, slowdown monitoring circuit to be checked,
Charging chip and charging current measure chip；Wherein, the simulated battery circuit includes at least: supply port, the first control terminal
Mouth, the first PMOS tube, the first NMOS tube, first resistor, second resistance, 3rd resistor, rectifier diode, simulated battery internal resistance and
First capacitor；Wherein: the supply port is electrically connected with power supply；The source electrode of first PMOS tube and the supply port
Electrical connection, the drain electrode of first PMOS tube are electrically connected with the positive incoming end of the rectifier diode, first PMOS tube
Grid be electrically connected with the drain electrode of first NMOS tube；The source electrode of first NMOS tube and the ground terminal electricity of the power supply
Connection, the grid of first NMOS tube are electrically connected with one end of the 3rd resistor, the other end connection of the 3rd resistor
Extremely first control port, under the control of the control signal of first control port output first described on or off
PMOS tube；The first resistor is connected electrically between the supply port and the grid of first PMOS tube；Second electricity
Resistance is connected electrically between the grid of first NMOS tube and the ground terminal of the power supply；The simulated battery internal resistance with it is described
First capacitor is in parallel, and is connected electrically between the reversed incoming end of the rectifier diode and the ground terminal of the power supply；Institute
It states slowdown monitoring circuit to be checked to include at least: the second control port, testing resistance, the second PMOS tube, the 2nd NMOS pipe, the 4th resistance,
Five resistance, the 6th resistance and second output terminal；Wherein: the reversed access of one end of the testing resistance and the rectifier diode
End electrical connection, the other end of the testing resistance are electrically connected with the drain electrode of second PMOS tube, the source of second PMOS tube
Pole is electrically connected with the second output terminal, and the grid of second PMOS tube is electrically connected with the drain electrode of second NMOS tube；Institute
The source electrode for stating the second NMOS tube is electrically connected with the ground terminal of the power supply, the grid of second NMOS tube and the described 6th
One end of resistance is electrically connected, and the other end of the 6th resistance is connected to second control port, in second control terminal
Second PMOS tube described on or off under the control of the control signal of mouth output；4th resistance is connected electrically in described second
Between the grid of NMOS tube and the ground terminal of the power supply；5th resistance is connected electrically in the grid of second PMOS tube
Between the second output terminal；The charging chip be connected to the second output terminal and the power supply ground terminal it
Between, when the charging chip is that the simulated battery circuit charges, to generate electric current stream for simulated battery circuit charging
Through the testing resistance；First detection incoming end of the charging current measurement chip and the second detection incoming end are electrically connected to institute
State the both ends of circuit under test；The output end output voltage measured value of the charging current measurement chip, the voltage measuring value are
It is obtained according to the electric current for flowing through the testing resistance.
Optionally, chip-detecting apparatus further include: the first gain setting resistor and the second gain setting resistor；
First gain setting resistor is connected electrically in the output end and charging electricity of the charging current measurement chip
Between the feedback end of flow measurement chip, second gain setting resistor is connected electrically in the feedback of the charging current measurement chip
Between end and the reference end of charging current measurement chip, the reference end is electrically connected with the ground terminal of the power supply.
Optionally, chip-detecting apparatus further include: the second capacitor；Second capacitor and first gain adjustment electricity
Resistance is in parallel, is connected between the output end of the charging current measurement chip and the feedback end of charging current measurement chip.
Optionally,Wherein, VOUTFor the voltage measuring value, IsampleFor
Flow through the electric current of the testing resistance, R22For the testing resistance, Ra1For first gain setting resistor, Ra2It is described
Two gain setting resistors.
Optionally, the charging current measurement chip uses MAX9922 chip.
The utility model provides a kind of chip detection dress it can be seen from above-mentioned technical solution provided by the utility model
It sets, the voltage measuring value exported by charging current measuring circuit, can monitor whether charging chip is in normal work shape
State, to find problematic charging chip in time.
Detailed description of the invention
It, below will be to required in embodiment description in order to illustrate more clearly of the technical solution of the utility model embodiment
The attached drawing used is briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the utility model
Example, for those of ordinary skill in the art, without creative efforts, can also be according to these attached drawings
Obtain other accompanying drawings.
Fig. 1 is the structural schematic diagram for the chip-detecting apparatus that the utility model embodiment 1 provides.
Specific embodiment
Below with reference to the attached drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out clear
Chu is fully described by, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole realities
Apply example.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without making creative work
The every other embodiment obtained, belongs to the protection scope of the utility model.
In the description of the present invention, it should be understood that term " center ", " longitudinal direction ", " transverse direction ", "upper", "lower",
The orientation or positional relationship of the instructions such as "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside" is
It is based on the orientation or positional relationship shown in the drawings, is merely for convenience of describing the present invention and simplifying the description, rather than indicate
Or imply that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore cannot understand
For limitations of the present invention.In addition, term " first ", " second " are used for description purposes only, and should not be understood as instruction or
Imply relative importance or quantity or position.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " is pacified
Dress ", " connected ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integrally
Connection；It can be mechanical connection, be also possible to be electrically connected；Can be directly connected, can also indirectly connected through an intermediary,
It can be the connection inside two elements.For the ordinary skill in the art, above-mentioned art can be understood with concrete condition
The concrete meaning of language in the present invention.
The utility model embodiment is described in further detail below in conjunction with attached drawing.
Embodiment 1
Present embodiments provide a kind of chip-detecting apparatus.Fig. 1 is the structure of chip-detecting apparatus provided in this embodiment
Schematic diagram, as shown in Figure 1, the test circuit includes: simulated battery circuit 10, slowdown monitoring circuit to be checked 20, charging chip 30 and charging
Current measurement circuit 40；Wherein:
Simulated battery circuit 10 includes: supply port VBAT-OUT, the first control port CHAR-TEST_EN, the first PMOS
Pipe Q1, the first NMOS tube Q2, first resistor R1, second resistance R2,3rd resistor R3, rectifier diode D1, simulated battery internal resistance
R11, first capacitor C1；Wherein, the first PMOS tube Q1, the first NMOS tube Q2, first resistor R1, second resistance R2,3rd resistor
R3 constitutes first switch circuit, and the first PMOS tube Q1 is first switch unit, and the first NMOS tube Q2 is second switch unit.Its
In: supply port VBAT-OUT is electrically connected to power supply；The source electrode (S) of first PMOS tube Q1 is electrically connected with supply port, the
The drain electrode (D) of one PMOS tube Q1 is electrically connected with the positive incoming end (1) of rectifier diode D1, the grid (G) of the first PMOS tube Q1
It is electrically connected with the drain electrode (D) of the first NMOS tube Q2；The source electrode (S) of first NMOS tube Q2 is electrically connected with the ground terminal GND of power supply,
The grid (G) of first NMOS pipe Q2 is electrically connected with one end of 3rd resistor R3, and the other end of 3rd resistor R3 is connected to the first control
Port CHAR-TEST_EN processed, the on or off under the control of the control signal of the first control port CHAR-TEST_EN output
First PMOS tube Q1；First resistor R1 is connected electrically between supply port VBAT-OUT and the grid (G) of the first PMOS tube；The
Two resistance R2 are connected electrically between the grid (G) of the first NMOS tube Q2 and the ground terminal GND of power supply；Rectifier diode D1's is anti-
One end of testing resistance R22 is electrically connected to incoming end (2)；Simulated battery internal resistance R11 is in parallel with first capacitor C1, and is electrically connected
Between the reversed incoming end (2) of rectifier diode D1 and the ground terminal GND of power supply；Need to charging chip to be measured into
When row test, simulated battery circuit 10 just needs work, so, when controlling signal is high level, the first NMOS tube Q2 and the
One PMOS tube Q1 conducting, the conducting of first switch circuit, simulated battery circuit 10 are working properly.When controlling signal is low level,
First NMOS tube Q2 and the first PMOS tube Q1 is turned off, and first switch circuit shutdown, simulated battery circuit 10 stops working.It is being not required to
When being tested, simulated battery circuit can be controlled by control signal and stopped working, so as to reduce the damage to circuit
Consumption.
Slowdown monitoring circuit 20 to be checked includes: the second control port CHAR-TEST_EN, testing resistance R22, the second PMOS tube Q3,
Two NMOS tube Q4, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 and second output terminal VBAT-OUT1；Wherein: rectification two
The reversed incoming end (2) of pole pipe D1 is electrically connected to one end of testing resistance R22；The other end of testing resistance R22 and the 2nd PMOS
The drain electrode (D) of pipe Q3 is electrically connected, and the source electrode (S) of the second PMOS tube Q3 is electrically connected with second output terminal VBAT-OUT1, and second
The grid (G) of PMOS tube Q3 is electrically connected with the drain electrode (D) of the second NMOS tube Q4；The source electrode (S) and power supply electricity of second NMOS tube Q4
The ground terminal GND in source is electrically connected, and the grid (G) of the second NMOS tube Q4 is electrically connected with one end of the 6th resistance R6, the 6th resistance R6's
The other end is connected to the second control port CHAR- TEST_EN, in the control letter of the second control port CHAR-TEST_EN output
Number control under the 2nd PMOS of on or off manage；4th resistance R4 is connected electrically in grid (G) and the power supply of the second NMOS tube Q4
Between the ground terminal GND of power supply；5th resistance electricity R5 is connected to the grid (G) and second output terminal VBAT- of the second PMOS tube Q3
Between OUT1.Only when needing to test charging chip to be measured, slowdown monitoring circuit 20 to be checked just needs work, so, when
When the control signal of second control port CHAR- TEST_EN output is high level, the second NMOS tube Q4 and the second PMOS tube Q3
Conducting, the conducting of second switch circuit, slowdown monitoring circuit 20 to be checked are working properly.When controlling signal is low level, the second NMOS tube Q4
It is turned off with the second PMOS tube Q3, second switch circuit shutdown, slowdown monitoring circuit 20 to be checked stops working.When not needing to be tested,
Slowdown monitoring circuit 20 to be checked can be controlled by control signal to stop working, so as to reduce the loss to circuit.
Charging chip 30 is connected between second output terminal VBAT-OUT1 and the ground terminal GND of power supply, for simulation electricity
Pond circuit 10 charges, and when charging chip 30 is that simulated battery circuit 10 charges, generates electric current and flows through testing resistance R22.Such as Fig. 1
It is shown, the ground terminal GND forming circuit of charging chip 30 and testing resistance R22, simulated battery internal resistance R11, power supply.It is charging
When chip 30 detects that the voltage value of simulated battery circuit 10 is less than preset value, charge mode is opened, electric current is from VBAT-OUT1
R22, R11 are flowed through, ground terminal GND is finally flowed into.At this point, there is electric current to flow through testing resistance R22, charging current measuring circuit 40 passes through
The electric current of detection circuit under test R22 obtains output voltage measured value, exists by the way that whether detection voltage measuring value meets charging chip
The voltage range worked normally to the internal cell charging of product, so that it may test out whether the charging chip is qualified core
Piece.
Charging current measures chip and includes the first detection incoming end RS+, the second detection incoming end RS- and output end OUT, the
One detection incoming end RS+ and the second detection incoming end RS- is connected electrically in the both ends of testing resistance R22, output end OUT output voltage
Measured value, voltage measuring value are obtained according to the electric current for flowing through testing resistance.
Chip-detecting apparatus provided by the embodiment of the utility model as a result, the electricity exported by charging current measuring circuit
Measured value is pressed, can monitor whether charging chip is in normal working condition, to find problematic charging chip in time.
As an alternative embodiment, the test circuit further include: the first gain setting resistor Ra1With the second gain
Adjust resistance Ra2；Wherein, the first gain setting resistor Ra1It is connected electrically in output end OUT and the charging of charging current measurement chip
Between the feedback end FB of current measurement chip, the second gain setting resistor Ra2It is connected electrically in the feedback end of charging current measurement chip
Between FB and the reference end REF of charging current measurement chip, the ground terminal electricity GND connection of reference end REF and power supply.At this
In embodiment, optionally, high side current detection amplifier can use MAX9922 chip.Voltage is obtained by following formula to survey
Magnitude:Wherein, VOUTFor voltage measuring value, IsampleTo flow through testing resistance
Electric current, R22For testing resistance, Ra1For the first gain setting resistor, Ra2For the second gain setting resistor.Pass through the first gain adjustment
Resistance and the second gain setting resistor determine the amplification factor of output voltageSo that the voltage of output end OUT output
Measured value is convenient for observation.
As an alternative embodiment, the test circuit further include: the second capacitor C2, in which: the second capacitor C2 with
First gain setting resistor Ra1Parallel connection, the output end OUT and charging current for being connected to charging current measurement chip measure chip
Between feedback end FB, isolated DC signal is played, remaining exchange and harmonic wave in the power supply that supply port VBAT-OUT is inputted
Composition circuit enters the effect on ground.
In the present embodiment, when normal work, by control terminal CHAR-TEST_EN export high level so that Q1, Q2, Q3,
Q4 is both turned on, charging chip detect need for simulated battery circuit charging when, for simulated battery circuit charge, circuit under test
Electric current is flowed through on R22, measurement chip, should for technical staff's analysis with this according to the current output voltage measured value flowed through on R22
Whether charging chip works in normal charge voltage range.It is defeated by control terminal CHAR-TEST_EN when not needing work
Low level out, so that Q1, Q2, Q3, Q4 are turned off, the voltage measuring value of measurement chip output is zero.
Any process described otherwise above or method description are construed as in flow chart or herein, and expression includes
It is one or more for realizing specific logical function or process the step of executable instruction code module, segment or portion
Point, and the range of preferred embodiments of the present invention includes other realization, wherein can not be by shown or discussion
Sequence, including according to related function by it is basic simultaneously in the way of or in the opposite order, Lai Zhihang function, this should be by this
The embodiment person of ordinary skill in the field of utility model is understood.
It should be appreciated that each section of the utility model can be realized with hardware, software, firmware or their combination.?
In above embodiment, what multiple steps or method can be executed in memory and by suitable instruction execution system with storage
Software or firmware are realized.It, and in another embodiment, can be with known in this field for example, if realized with hardware
Any one of following technology or their combination realize: there is the logic gate for realizing logic function to data-signal
The discrete logic of circuit, the specific integrated circuit with suitable combinational logic gate circuit, programmable gate array (PGA),
Field programmable gate array (FPGA) etc..
Those skilled in the art are understood that realize all or part of step that above-described embodiment method carries
It suddenly is that relevant hardware can be instructed to complete by program, the program can store in a kind of computer-readable storage medium
In matter, which when being executed, includes the steps that one or a combination set of embodiment of the method.
In addition, can integrate in a processing module in each functional unit in each embodiment of the utility model,
It can be each unit to physically exist alone, can also be integrated in two or more units in a module.It is above-mentioned integrated
Module both can take the form of hardware realization, can also be realized in the form of software function module.The integrated mould
If block is realized and when sold or used as an independent product in the form of software function module, it also can store and counted at one
In calculation machine read/write memory medium.
Storage medium mentioned above can be read-only memory, disk or CD etc..
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is contained at least one embodiment or example of the utility model.In the present specification, to the schematic table of above-mentioned term
Stating may not refer to the same embodiment or example.
Although the embodiments of the present invention have been shown and described above, it is to be understood that above-described embodiment is
Illustratively, it should not be understood as limiting the present invention, those skilled in the art are not departing from the utility model
Principle and objective in the case where above-described embodiment can be changed in the scope of the utility model, modify, replace and
Modification.The scope of the utility model is by appended claims and its equivalent limits.
Claims (5)
1. a kind of chip-detecting apparatus characterized by comprising simulated battery circuit, slowdown monitoring circuit to be checked, charging chip and charging
Current measurement chip；Wherein,
The simulated battery circuit includes at least: supply port, the first control port, the first PMOS tube, the first NMOS tube, first
Resistance, second resistance, 3rd resistor, rectifier diode, simulated battery internal resistance and first capacitor；Wherein: the supply port with
Power supply electrical connection；The source electrode of first PMOS tube is electrically connected with the supply port, the drain electrode of first PMOS tube
It is electrically connected with the positive incoming end of the rectifier diode, the drain electrode of the grid of first PMOS tube and first NMOS tube
Electrical connection；The source electrode of first NMOS tube is electrically connected with the ground terminal of the power supply, the grid of first NMOS tube with
One end of the 3rd resistor is electrically connected, and the other end of the 3rd resistor is connected to first control port；Described first
Resistance is connected electrically between the supply port and the grid of first PMOS tube；The second resistance is connected electrically in described
Between the grid of one NMOS tube and the ground terminal of the power supply；The simulated battery internal resistance is in parallel with the first capacitor, and
It is connected electrically between the reversed incoming end of the rectifier diode and the ground terminal of the power supply；
The slowdown monitoring circuit to be checked includes at least: the second control port, testing resistance, the second PMOS tube, the second NMOS tube, the 4th electricity
Resistance, the 5th resistance, the 6th resistance and second output terminal；Wherein: one end of the testing resistance is anti-with the rectifier diode
It is electrically connected to incoming end, the other end of the testing resistance is electrically connected with the drain electrode of second PMOS tube, the 2nd PMOS
The source electrode of pipe is electrically connected with the second output terminal, and the grid of second PMOS tube and the drain electrode of second NMOS tube are electrically connected
It connects；The source electrode of second NMOS tube is electrically connected with the ground terminal of the power supply, the grid of second NMOS tube with it is described
One end of 6th resistance is electrically connected, and the other end of the 6th resistance is connected to second control port；4th resistance
It is connected electrically between the grid of second NMOS tube and the ground terminal of the power supply；5th resistance is connected electrically in described
Between the grid of second PMOS tube and the second output terminal；
The charging chip is connected between the second output terminal and the ground terminal of the power supply；
First detection incoming end of the charging current measurement chip and the second detection incoming end are electrically connected to the circuit under test
Both ends；The output end output voltage measured value of the charging current measurement chip.
2. chip-detecting apparatus according to claim 1, which is characterized in that further include: the first gain setting resistor and
Two gain setting resistors；
First gain setting resistor is connected electrically in the output end of the charging current measurement chip and the charging current is surveyed
Between the feedback end for measuring chip, second gain setting resistor be connected electrically in the feedback end of charging current measurement chip with
Between the reference end of the charging current measurement chip, the reference end is electrically connected with the ground terminal of the power supply.
3. chip-detecting apparatus according to claim 2, which is characterized in that further include: the second capacitor；
Second capacitor is in parallel with first gain setting resistor, is connected to the output end of the charging current measurement chip
Between the feedback end of charging current measurement chip.
4. chip-detecting apparatus according to claim 2 or 3, which is characterized in that
Wherein, VOUTFor the voltage measuring value, IsampleIt is described to be measured to flow through
The electric current of resistance, R22For the testing resistance, Ra1For first gain setting resistor, Ra2For the second gain adjustment electricity
Resistance.
5. chip-detecting apparatus according to claim 4, which is characterized in that
The charging current measurement chip uses MAX9922 chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821192438.4U CN208654282U (en) | 2018-07-25 | 2018-07-25 | A kind of chip-detecting apparatus |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821192438.4U CN208654282U (en) | 2018-07-25 | 2018-07-25 | A kind of chip-detecting apparatus |
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| CN208654282U true CN208654282U (en) | 2019-03-26 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109031097A (en) * | 2018-07-25 | 2018-12-18 | 天地融电子（天津）有限公司 | A kind of chip-detecting apparatus |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109031097A (en) * | 2018-07-25 | 2018-12-18 | 天地融电子（天津）有限公司 | A kind of chip-detecting apparatus |
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