CN109031097A - A kind of chip-detecting apparatus - Google Patents
A kind of chip-detecting apparatus Download PDFInfo
- Publication number
- CN109031097A CN109031097A CN201810827085.9A CN201810827085A CN109031097A CN 109031097 A CN109031097 A CN 109031097A CN 201810827085 A CN201810827085 A CN 201810827085A CN 109031097 A CN109031097 A CN 109031097A
- Authority
- CN
- China
- Prior art keywords
- resistance
- chip
- electrically connected
- charging current
- charging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The present invention provides a kind of chip-detecting apparatus, comprising: simulated battery circuit, slowdown monitoring circuit to be checked, charging chip and charging current measuring circuit；Simulated battery circuit includes: supply port, the first control port, the first PMOS tube, the first NMOS tube, first resistor, second resistance, 3rd resistor, rectifier diode, simulated battery internal resistance and first capacitor；Slowdown monitoring circuit to be checked includes: the second control port, testing resistance, the second PMOS tube, the second NMOS tube, the 4th resistance, the 5th resistance, the 6th resistance and second output terminal；Charging chip is connected between second output terminal and ground, is charged for simulated battery circuit；First detection incoming end of charging current measurement chip and the second detection incoming end are electrically connected to the both ends of circuit under test；The output end output voltage measured value of charging current measurement chip.It is whether normal that charging chip work can be monitored by the voltage measuring value of output.
Description
Technical field
The present invention relates to a kind of electronic technology field more particularly to a kind of chip-detecting apparatus.
Background technique
In order to guarantee the network bank business safety of user, bank can also issue intelligence to user when handling bank card for user
Energy encryption device, assists user to handle network bank business.User only uses intelligent cipher equipment ability when carrying out network bank business
Various pecuniary exchanges are completed, otherwise, client can prompt user to be inserted into intelligent cipher equipment.
Dependence with the fast development and network bank business of intelligent cipher equipment to intelligent cipher equipment, intelligent cipher are set
It is standby frequently to be used by user, especially often handle the user of wholesale network bank business.But since intelligent cipher equipment can not
Disassembly in order to which that improves intelligent cipher equipment uses cruise duration, mostly uses in the industry charging chip therefore, it is impossible to replace battery
To realize that the battery to intelligent cipher equipment charges.
And charging chip is produced in enormous quantities by the production line of factory, before coming into operation, in order to guarantee using
Charging chip in intelligent cipher equipment can achieve good charging ability, be badly in need of a kind of simply to charging chip work
Whether normal test mode.
Summary of the invention
One of present invention seek to address that the above problem/.
The main purpose of the present invention is to provide a kind of chip-detecting apparatus.
In order to achieve the above objectives, technical solution of the present invention is specifically achieved in that
One aspect of the present invention provides a kind of chip-detecting apparatus, comprising: simulated battery circuit, slowdown monitoring circuit to be checked, charging
Chip and charging current measure chip；Wherein, the simulated battery circuit includes at least: supply port, the first control port,
One PMOS tube, the first NMOS tube, first resistor, second resistance, 3rd resistor, rectifier diode, simulated battery internal resistance and first
Capacitor；Wherein: the supply port is electrically connected with power supply；The source electrode of first PMOS tube is electrically connected with the supply port
It connects, the drain electrode of first PMOS tube is electrically connected with the positive incoming end of the rectifier diode, the grid of first PMOS tube
Pole is electrically connected with the drain electrode of first NMOS tube；The ground terminal of the source electrode and the power supply of first NMOS tube is electrically connected
It connects, the grid of first NMOS tube is electrically connected with one end of the 3rd resistor, and the other end of the 3rd resistor is connected to
First control port, under the control of the control signal of first control port output first described on or off
PMOS tube；The first resistor is connected electrically between the supply port and the grid of first PMOS tube；Second electricity
Resistance is connected electrically between the grid of first NMOS tube and the ground terminal of the power supply；The simulated battery internal resistance with it is described
First capacitor is in parallel, and is connected electrically between the reversed incoming end of the rectifier diode and the ground terminal of the power supply；Institute
It states slowdown monitoring circuit to be checked to include at least: the second control port, testing resistance, the second PMOS tube, the second NMOS tube, the 4th resistance,
Five resistance, the 6th resistance and second output terminal；Wherein: the reversed access of one end of the testing resistance and the rectifier diode
End electrical connection, the other end of the testing resistance are electrically connected with the drain electrode of second PMOS tube, the source of second PMOS tube
Pole is electrically connected with the second output terminal, and the grid of second PMOS tube is electrically connected with the drain electrode of second NMOS tube；Institute
The source electrode for stating the second NMOS tube is electrically connected with the ground terminal of the power supply, the grid of second NMOS tube and the 6th electricity
One end of resistance is electrically connected, and the other end of the 6th resistance is connected to second control port, in second control port
Second PMOS tube described on or off under the control of the control signal of output；4th resistance is connected electrically in described second
Between the grid of NMOS tube and the ground terminal of the power supply；5th resistance is connected electrically in the grid of second PMOS tube
Between the second output terminal；The charging chip be connected to the second output terminal and the power supply ground terminal it
Between, when the charging chip is that the simulated battery circuit charges, to generate electric current stream for simulated battery circuit charging
Through the testing resistance；First detection incoming end of the charging current measurement chip and the second detection incoming end are electrically connected to institute
State the both ends of circuit under test；The output end output voltage measured value of the charging current measurement chip, the voltage measuring value are
It is obtained according to the electric current for flowing through the testing resistance.
Optionally, chip-detecting apparatus further include: the first gain setting resistor and the second gain setting resistor；
First gain setting resistor is connected electrically in the output end and charging electricity of the charging current measurement chip
Between the feedback end of flow measurement chip, second gain setting resistor is connected electrically in the feedback of the charging current measurement chip
Between end and the reference end of charging current measurement chip, the reference end is electrically connected with the ground terminal of the power supply.
Optionally, chip-detecting apparatus further include: the second capacitor；Second capacitor and first gain adjustment electricity
Resistance is in parallel, is connected between the output end of the charging current measurement chip and the feedback end of charging current measurement chip.
Optionally,Wherein, VOUTFor the voltage measuring value, IsampleFor
Flow through the electric current of the testing resistance, R22For the testing resistance, Ra1For first gain setting resistor, Ra2It is described
Two gain setting resistors.
Optionally, the charging current measurement chip uses MAX9922 chip.
As seen from the above technical solution provided by the invention, the present invention provides a kind of chip-detecting apparatus, pass through
The voltage measuring value of charging current measuring circuit output, can monitor whether charging chip is in normal working condition, and
The problematic charging chip of Shi Faxian.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill in field, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the structural schematic diagram for the chip-detecting apparatus that the embodiment of the present invention 1 provides.
Specific embodiment
With reference to the attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on this
The embodiment of invention, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, belongs to protection scope of the present invention.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", "upper", "lower",
The orientation or positional relationship of the instructions such as "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside" is
It is based on the orientation or positional relationship shown in the drawings, is merely for convenience of description of the present invention and simplification of the description, rather than instruction or dark
Show that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as pair
Limitation of the invention.In addition, term " first ", " second " are used for description purposes only, it is not understood to indicate or imply opposite
Importance or quantity or position.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also can be indirectly connected through an intermediary
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
The embodiment of the present invention is described in further detail below in conjunction with attached drawing.
Embodiment 1
Present embodiments provide a kind of chip-detecting apparatus.Fig. 1 is the structure of chip-detecting apparatus provided in this embodiment
Schematic diagram, as shown in Figure 1, the test circuit includes: simulated battery circuit 10, slowdown monitoring circuit to be checked 20, charging chip 30 and charging
Current measurement circuit 40；Wherein:
Simulated battery circuit 10 includes: supply port VBAT-OUT, the first control port CHAR-TEST_EN, the first PMOS
Pipe Q1, the first NMOS tube Q2, first resistor R1, second resistance R2,3rd resistor R3, rectifier diode D1, simulated battery internal resistance
R11, first capacitor C1；Wherein, the first PMOS tube Q1, the first NMOS tube Q2, first resistor R1, second resistance R2,3rd resistor
R3 constitutes first switch circuit 104, and the first PMOS tube Q1 is first switch unit 1041, and the first NMOS tube Q2 is second switch list
Member 1042.Wherein: supply port VBAT-OUT is electrically connected to power supply；The source electrode (S) and supply port of first PMOS tube Q1
Electrical connection, the drain electrode (D) of the first PMOS tube Q1 are electrically connected with the positive incoming end (1) of rectifier diode D1, the first PMOS tube Q1
Grid (G) be electrically connected with the drain electrode (D) of the first NMOS tube Q2；The ground terminal of source electrode (S) and power supply of first NMOS tube Q2
GND electrical connection, the grid (G) of the first NMOS tube Q2 are electrically connected with one end of 3rd resistor R3, and the other end of 3rd resistor R3 connects
It is connected to the first control port CHAR-TEST_EN, under the control of the control signal of the first control port CHAR-TEST_EN output
The first PMOS tube of on or off Q1；First resistor R1 is connected electrically in the grid of supply port VBAT-OUT and the first PMOS tube
(G) between；Second resistance R2 is connected electrically between the grid (G) of the first NMOS tube Q2 and the ground terminal GND of power supply；Rectification two
The reversed incoming end (2) of pole pipe D1 is electrically connected to one end of testing resistance R22；Simulated battery internal resistance R11 and first capacitor C1 are simultaneously
Connection, and be connected electrically between the reversed incoming end (2) of rectifier diode D1 and the ground terminal GND of power supply；It is needing to be measured
Charging chip when being tested, simulated battery circuit 10 just needs work, so, when controlling signal is high level, first
NMOS tube Q2 is connected with the first PMOS tube Q1, and first switch circuit 104 is connected, and simulated battery circuit 10 is working properly.Work as control
When signal is low level, the first NMOS tube Q2 and the first PMOS tube Q1 are turned off, and first switch circuit 104 turns off, simulated battery electricity
Road 10 stops working.When not needing to be tested, simulated battery circuit can be controlled by control signal and stopped working, thus
The loss to circuit can be reduced.
Slowdown monitoring circuit 20 to be checked includes: the second control port CHAR-TEST_EN, testing resistance R22, the second PMOS tube Q3,
Two NMOS tube Q4, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 and second output terminal VBAT-OUT1；Wherein: rectification two
The reversed incoming end (2) of pole pipe D1 is electrically connected to one end of testing resistance R22；The other end of testing resistance R22 and the 2nd PMOS
The drain electrode (D) of pipe Q3 is electrically connected, and the source electrode (S) of the second PMOS tube Q3 is electrically connected with second output terminal VBAT-OUT1, the 2nd PMOS
The grid (G) of pipe Q3 is electrically connected with the drain electrode (D) of the second NMOS tube Q4；The source electrode (S) of second NMOS tube Q4 and power supply
Ground terminal GND electrical connection, the grid (G) of the second NMOS tube Q4 are electrically connected with one end of the 6th resistance R6, and the 6th resistance R6's is another
End is connected to the second control port CHAR-TEST_EN, in the control of the control signal of the second control port CHAR-TEST_EN output
Make lower the second PMOS tube of on or off；4th resistance R4 is connected electrically in the grid (G) and power supply of the second NMOS tube Q4
Between ground terminal GND；5th resistance electricity R5 is connected between the grid (G) of the second PMOS tube Q3 and second output terminal VBAT-OUT1.
Only when needing to test charging chip to be measured, slowdown monitoring circuit 20 to be checked just needs work, so, when the second control terminal
When the control signal of mouth CHAR-TEST_EN output is high level, the second NMOS tube Q4 is connected with the second PMOS tube Q3, and second opens
Powered-down road 204 is connected, and slowdown monitoring circuit 20 to be checked is working properly.When controlling signal is low level, the second NMOS tube Q4 and second
PMOS tube Q3 shutdown, second switch circuit 204 turn off, and slowdown monitoring circuit 20 to be checked stops working.It, can be with when not needing to be tested
It controls slowdown monitoring circuit 20 to be checked by control signal to stop working, so as to reduce the loss to circuit.
Charging chip 30 is connected between second output terminal VBAT-OUT1 and the ground terminal GND of power supply, for simulation electricity
Pond circuit 10 charges, and when charging chip 30 is that simulated battery circuit 10 charges, generates electric current and flows through testing resistance R22.Such as Fig. 1
It is shown, the ground terminal GND forming circuit of charging chip 30 and testing resistance R22, simulated battery internal resistance R11, power supply.It is charging
When chip 30 detects that the voltage value of simulated battery circuit 10 is less than preset value, charge mode is opened, electric current is flowed from VBAT-OUT1
Through R22, R11, ground terminal GND is finally flowed into.At this point, there is electric current to flow through testing resistance R22, charging current measuring circuit 40 passes through inspection
Survey circuit under test R22 electric current obtain output voltage measured value, by detect voltage measuring value whether meet charging chip to
The voltage range that the internal cell charging of product works normally, so that it may test out whether the charging chip is qualified chip.
Charging current measures chip and includes the first detection incoming end RS+, the second detection incoming end RS- and output end OUT, the
One detection incoming end RS+ and the second detection incoming end RS- is connected electrically in the both ends of testing resistance R22, output end OUT output voltage
Measured value, voltage measuring value are obtained according to the electric current for flowing through testing resistance.
Chip-detecting apparatus provided in an embodiment of the present invention as a result, is surveyed by the voltage that charging current measuring circuit exports
Magnitude, can monitor whether charging chip is in normal working condition, to find problematic charging chip in time.
As an alternative embodiment, the test circuit further include: the first gain setting resistor Ra1With the second gain
Adjust resistance Ra2；Wherein, the first gain setting resistor Ra1It is connected electrically in output end OUT and the charging of charging current measurement chip
Between the feedback end FB of current measurement chip, the second gain setting resistor Ra2It is connected electrically in the feedback end of charging current measurement chip
Between FB and the reference end REF of charging current measurement chip, the ground terminal electricity GND connection of reference end REF and power supply.In this reality
It applies in example, optionally, high side current detection amplifier can use MAX9922 chip.Voltage measurement is obtained by following formula
Value:Wherein, VOUTFor voltage measuring value, IsampleFor the electricity for flowing through testing resistance
Stream, R22For testing resistance, Ra1For the first gain setting resistor, Ra2For the second gain setting resistor.Pass through the first gain adjustment electricity
Resistance and the second gain setting resistor determine the amplification factor of output voltageSo that the voltage of output end OUT output is surveyed
Magnitude is convenient for observation.
As an alternative embodiment, the test circuit further include: the second capacitor C2, in which: the second capacitor C2 with
First gain setting resistor Ra1Parallel connection, the output end OUT and charging current for being connected to charging current measurement chip measure chip
Between feedback end FB, isolated DC signal is played, remaining exchange and harmonic wave in the power supply that supply port VBAT-OUT is inputted
Composition circuit enters the effect on ground.
In the present embodiment, when normal work, by control terminal CHAR-TEST_EN export high level so that Q1, Q2, Q3,
Q4 is both turned on, charging chip detect need for simulated battery circuit charging when, for simulated battery circuit charge, circuit under test
Electric current is flowed through on R22, measurement chip, should for technical staff's analysis with this according to the current output voltage measured value flowed through on R22
Whether charging chip works in normal charge voltage range.It is defeated by control terminal CHAR-TEST_EN when not needing work
Low level out, so that Q1, Q2, Q3, Q4 are turned off, the voltage measuring value of measurement chip output is zero.
Any process described otherwise above or method description are construed as in flow chart or herein, and expression includes
It is one or more for realizing specific logical function or process the step of executable instruction code module, segment or portion
Point, and the range of the preferred embodiment of the present invention includes other realization, wherein can not press shown or discussed suitable
Sequence, including according to related function by it is basic simultaneously in the way of or in the opposite order, to execute function, this should be of the invention
Embodiment person of ordinary skill in the field understood.
It should be appreciated that each section of the invention can be realized with hardware, software, firmware or their combination.Above-mentioned
In embodiment, software that multiple steps or method can be executed in memory and by suitable instruction execution system with storage
Or firmware is realized.It, and in another embodiment, can be under well known in the art for example, if realized with hardware
Any one of column technology or their combination are realized: having a logic gates for realizing logic function to data-signal
Discrete logic, with suitable combinational logic gate circuit specific integrated circuit, programmable gate array (PGA), scene
Programmable gate array (FPGA) etc..
Those skilled in the art are understood that realize all or part of step that above-described embodiment method carries
It suddenly is that relevant hardware can be instructed to complete by program, the program can store in a kind of computer-readable storage medium
In matter, which when being executed, includes the steps that one or a combination set of embodiment of the method.
It, can also be in addition, each functional unit in each embodiment of the present invention can integrate in a processing module
It is that each unit physically exists alone, can also be integrated in two or more units in a module.Above-mentioned integrated mould
Block both can take the form of hardware realization, can also be realized in the form of software function module.The integrated module is such as
Fruit is realized and when sold or used as an independent product in the form of software function module, also can store in a computer
In read/write memory medium.
Storage medium mentioned above can be read-only memory, disk or CD etc..
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
Centainly refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any
One or more embodiment or examples in can be combined in any suitable manner.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art are not departing from the principle of the present invention and objective
In the case where can make changes, modifications, alterations, and variations to the above described embodiments within the scope of the invention.The scope of the present invention
By appended claims and its equivalent limit.
Claims (5)
1. a kind of chip-detecting apparatus characterized by comprising simulated battery circuit, slowdown monitoring circuit to be checked, charging chip and charging
Current measurement chip；Wherein,
The simulated battery circuit includes at least: supply port, the first control port, the first PMOS tube, the first NMOS tube, first
Resistance, second resistance, 3rd resistor, rectifier diode, simulated battery internal resistance and first capacitor；Wherein: the supply port with
Power supply electrical connection；The source electrode of first PMOS tube is electrically connected with the supply port, the drain electrode of first PMOS tube
It is electrically connected with the positive incoming end of the rectifier diode, the drain electrode of the grid of first PMOS tube and first NMOS tube
Electrical connection；The source electrode of first NMOS tube is electrically connected with the ground terminal of the power supply, the grid of first NMOS tube with
One end of the 3rd resistor is electrically connected, and the other end of the 3rd resistor is connected to first control port, described the
First PMOS tube described on or off under the control of the control signal of one control port output；The first resistor is connected electrically in
Between the supply port and the grid of first PMOS tube；The second resistance is connected electrically in the grid of first NMOS tube
Between pole and the ground terminal of the power supply；The simulated battery internal resistance is in parallel with the first capacitor, and is connected electrically in described
Between the reversed incoming end of rectifier diode and the ground terminal of the power supply；
The slowdown monitoring circuit to be checked includes at least: the second control port, testing resistance, the second PMOS tube, the second NMOS tube, the 4th electricity
Resistance, the 5th resistance, the 6th resistance and second output terminal；Wherein: one end of the testing resistance is anti-with the rectifier diode
It is electrically connected to incoming end, the other end of the testing resistance is electrically connected with the drain electrode of second PMOS tube, the 2nd PMOS
The source electrode of pipe is electrically connected with the second output terminal, and the grid of second PMOS tube and the drain electrode of second NMOS tube are electrically connected
It connects；The source electrode of second NMOS tube is electrically connected with the ground terminal of the power supply, the grid of second NMOS tube with it is described
One end of 6th resistance is electrically connected, and the other end of the 6th resistance is connected to second control port, in second control
Second PMOS tube described on or off under the control of the control signal of port output processed；4th resistance is connected electrically in described
Between the grid of second NMOS tube and the ground terminal of the power supply；5th resistance is connected electrically in second PMOS tube
Between grid and the second output terminal；
The charging chip is connected between the second output terminal and the ground terminal of the power supply, for the simulated battery
Circuit charging generates electric current and flows through the testing resistance when the charging chip is that the simulated battery circuit charges；
First detection incoming end of the charging current measurement chip and the second detection incoming end are electrically connected to the circuit under test
Both ends；The output end output voltage measured value of the charging current measurement chip, the voltage measuring value are that basis flows through institute
State what the electric current of testing resistance obtained.
2. chip-detecting apparatus according to claim 1, which is characterized in that further include: the first gain setting resistor and
Two gain setting resistors；
First gain setting resistor is connected electrically in the output end of the charging current measurement chip and the charging current is surveyed
Between the feedback end for measuring chip, second gain setting resistor be connected electrically in the feedback end of charging current measurement chip with
Between the reference end of the charging current measurement chip, the reference end is electrically connected with the ground terminal of the power supply.
3. chip-detecting apparatus according to claim 2, which is characterized in that further include: the second capacitor；
Second capacitor is in parallel with first gain setting resistor, is connected to the output end of the charging current measurement chip
Between the feedback end of charging current measurement chip.
4. chip-detecting apparatus according to claim 2 or 3, which is characterized in that
Wherein, VOUTFor the voltage measuring value, IsampleIt is described to be measured to flow through
The electric current of resistance, R22For the testing resistance, Ra1For first gain setting resistor, Ra2For the second gain adjustment electricity
Resistance.
5. chip-detecting apparatus according to any one of claims 1 to 3, which is characterized in that
The charging current measurement chip uses MAX9922 chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810827085.9A CN109031097A (en) | 2018-07-25 | 2018-07-25 | A kind of chip-detecting apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810827085.9A CN109031097A (en) | 2018-07-25 | 2018-07-25 | A kind of chip-detecting apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109031097A true CN109031097A (en) | 2018-12-18 |
Family
ID=64645080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810827085.9A Pending CN109031097A (en) | 2018-07-25 | 2018-07-25 | A kind of chip-detecting apparatus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109031097A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112147484A (en) * | 2020-08-28 | 2020-12-29 | 珠海市一微半导体有限公司 | Test system based on charging chip and charging test system |
| CN115015286A (en) * | 2022-06-13 | 2022-09-06 | 中大智能科技股份有限公司 | Chip detection method and system based on machine vision |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005191383A (en) * | 2003-12-26 | 2005-07-14 | Toshiba Microelectronics Corp | Semiconductor device |
| CN101741124A (en) * | 2010-01-25 | 2010-06-16 | 海洋王照明科技股份有限公司 | Battery charging circuit and power supply device |
| US20150233996A1 (en) * | 2014-02-14 | 2015-08-20 | Samsung Electronics Co., Ltd. | Circuit of measuring leakage current in a semiconductor integrated circuit |
| CN206149239U (en) * | 2016-11-22 | 2017-05-03 | 珠海中慧微电子股份有限公司 | Chip measurability port circuit |
| CN208654282U (en) * | 2018-07-25 | 2019-03-26 | 天地融电子（天津）有限公司 | A kind of chip-detecting apparatus |
-
2018
- 2018-07-25 CN CN201810827085.9A patent/CN109031097A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005191383A (en) * | 2003-12-26 | 2005-07-14 | Toshiba Microelectronics Corp | Semiconductor device |
| CN101741124A (en) * | 2010-01-25 | 2010-06-16 | 海洋王照明科技股份有限公司 | Battery charging circuit and power supply device |
| US20150233996A1 (en) * | 2014-02-14 | 2015-08-20 | Samsung Electronics Co., Ltd. | Circuit of measuring leakage current in a semiconductor integrated circuit |
| CN206149239U (en) * | 2016-11-22 | 2017-05-03 | 珠海中慧微电子股份有限公司 | Chip measurability port circuit |
| CN208654282U (en) * | 2018-07-25 | 2019-03-26 | 天地融电子（天津）有限公司 | A kind of chip-detecting apparatus |
Non-Patent Citations (1)
| Title |
|---|
| 李演明;毛翔宇;全思;文常保;温立民;: "一种用于锂电池充电IC的电池检测电路", 微电子学, no. 03 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112147484A (en) * | 2020-08-28 | 2020-12-29 | 珠海市一微半导体有限公司 | Test system based on charging chip and charging test system |
| CN112147484B (en) * | 2020-08-28 | 2024-06-14 | 珠海一微半导体股份有限公司 | Test system based on charging chip and charging test system |
| CN115015286A (en) * | 2022-06-13 | 2022-09-06 | 中大智能科技股份有限公司 | Chip detection method and system based on machine vision |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN201373895Y (en) | Online monitoring device of zinc oxide arrester (MOA) | |
| CN103576064B (en) | A kind of Insulation monitoring calibration steps with calibration module | |
| CN103091596A (en) | Balancing double-switching circuit and insulation detection device and method based on the same | |
| WO2017071589A1 (en) | Device and method for testing battery equalization circuit | |
| US20160187430A1 (en) | Apparatus for measuring cell internal resistance online and measurement method therefor | |
| US9176178B2 (en) | Battery simulation circuit | |
| CN105717278B (en) | A kind of soil salt cooling-water temperature sensor | |
| JP6329376B2 (en) | Radiation monitor and current measurement method for radiation monitor | |
| CN208818818U (en) | A kind of low-power consumption program control type current mutual inductor field detecting device | |
| CN109031097A (en) | A kind of chip-detecting apparatus | |
| CN106875619A (en) | A kind of Combined electric appliance fire disaster monitoring probe | |
| CN203217024U (en) | Balancing double-switching circuit and insulation detection device based on same | |
| CN102353904B (en) | Battery voltage detection module and circuit thereof, and logic transmission circuit | |
| CN203587780U (en) | Battery power detecting device | |
| CN116068274A (en) | Insulation detection circuit and detection method of photovoltaic inverter | |
| CN204228901U (en) | Local discharge detection device | |
| CN109061236A (en) | A kind of equipment for testing charging chip | |
| CN207677424U (en) | A kind of current foldback circuit | |
| CN104391259A (en) | Magnetic moment real-time test system and test method thereof | |
| CN208654282U (en) | A kind of chip-detecting apparatus | |
| CN207098691U (en) | Electrokinetic cell system and its equalizing circuit and electric automobile | |
| CN203909166U (en) | A voltage transformer temperature rise measurement apparatus | |
| CN108896952A (en) | Power grid exception simulated testing system and its test method | |
| CN202815193U (en) | Battery test device | |
| CN208421060U (en) | A kind of bidirectional current detection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |