CN208570602U - A kind of snakelike layouts increasing VDMOS gully density - Google Patents
A kind of snakelike layouts increasing VDMOS gully density Download PDFInfo
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- CN208570602U CN208570602U CN201821420851.1U CN201821420851U CN208570602U CN 208570602 U CN208570602 U CN 208570602U CN 201821420851 U CN201821420851 U CN 201821420851U CN 208570602 U CN208570602 U CN 208570602U
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- trench gate
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- 230000001413 cellular effect Effects 0.000 claims abstract description 39
- 238000010586 diagram Methods 0.000 description 10
- 210000004027 cell Anatomy 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000003834 intracellular effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Abstract
The utility model embodiment is related to a kind of snakelike layouts for increasing VDMOS gully density, and layouts include multiple cellulars along first direction and second direction repeated arrangement: cellular includes: first groove grid, second groove grid, third trench gate and two contact holes；First groove grid and second groove grid are arranged in parallel in a second direction, and third trench gate is S type, are placed between first groove grid and second groove grid；One contact hole is placed between third trench gate and second groove grid, another contact hole is placed between third trench gate and first groove grid；Wherein, the spacing of contact hole to first groove grid, second groove grid and third trench gate is not less than the first minimum spacing；The spacing of third trench gate to first groove grid, second groove grid is not less than the second minimum spacing；The second groove grid of each cellular and the first groove grid of an adjacent cellular in a first direction are the same trench gate to overlap；First direction is perpendicular with second direction.
Description
Technical field
The utility model relates to power semiconductor technologies field more particularly to it is a kind of increase VDMOS gully density it is snakelike
Layouts.
Background technique
Mesolow trench-gate vertical double diffused metal-oxide semiconductor field effect transistor (VDMOS) conducting at present
Resistance is mainly made of several parts such as channel resistance, epitaxial electric resistance, source and drain resistance, metallic resistance and resistance substrates, wherein channel
What resistance typically constituted from entire conducting resistance 25%~50% differs, and epitaxial electric resistance accounts for the 35%~60% of entire conducting resistance,
What remaining part sub-resistance summation accounted for entire conducting resistance 5%~10% differs.And determine the significant portion factor and ditch of channel resistance
Density is related in the unit area of slot grid.
Trench gate VDMOS generally realizes specified conducting resistance, member in parallel using the Butut mode of multiple cellular parallel connections
Then more low corresponding chip area is also bigger (cost is also higher) for the conducting resistance of the more groove VDMOS of born of the same parents, to realize in phase
How smaller chip area in the case where with specified conducting resistance is obtained with realizing lower cost in unit chip area
Obtaining channel width, that is, higher gully density big as far as possible (reducing than conducting resistance) becomes extremely important.
The channel domain of the trench gate VDMOS of mainstream includes: strip structure as shown in Figure 1 at present, by as shown in Figure 2
Cellular constitute；The sub- shape structure in field as shown in Figure 3 and delta structure as shown in Figure 4, the two is by as shown in Figure 5
Cellular is constituted；The structure of hexagon as shown in FIG. 6 is made of cellular as shown in Figure 7.
The composition of design for different structures, cellular is different, this also determines cellular interior raceway groove under unit area
The difference of density.It is set as a, groove width 0.2a, aperture 0.2a, the phase that hole is 0.2a to groove distance in unit length
With under the conditions of, the gully density of strip structure shown in FIG. 1: cellular channel perimeter/cell density=2a/ (a*a)=2/a, Fig. 3
Shown in field sub- shape structure and delta structure as shown in Figure 4 gully density: cellular channel perimeter/cell density=
2.4a/ (a*a)=2.4/a, the gully density of the structure of hexagon shown in fig. 6: cellular channel perimeter/cell density=
2.078a/ (a*0.866a)=2.4/a.Wherein channel perimeter is marked in figure with heavy line.It can be seen that gully density: rectangular
Structure=hexagonal structure > strip structure, but maximum is also only 2.4/a.
In order to further decrease the conducting resistance of VDMOS, it is also necessary to be further improved on layouts.
Utility model content
The purpose of the utility model is to provide a kind of snakelike layouts for increasing VDMOS gully density, can be identical
The grid width of trench gate is greatly improved in area, that is, increases the density of channel, so that reaching reduces mesh of the VDMOS than conducting resistance
's.
For this purpose, the utility model embodiment provides a kind of snakelike layouts for increasing VDMOS gully density, including edge
Multiple cellulars of first direction and second direction repeated arrangement:
The cellular includes: first groove grid, second groove grid, third trench gate and two contact holes；First ditch
Slot grid are arranged in parallel along the second direction with the second groove grid, and the third trench gate is S type, are placed in described the
Between one trench gate and the second groove grid；One contact hole is placed in the third trench gate and the second groove grid
Between, another described contact hole is placed between the third trench gate and the first groove grid；Wherein, the contact hole is extremely
The spacing of the first groove grid, second groove grid and third trench gate is not less than the first minimum spacing；The third groove
The spacing of grid to the first groove grid, second groove grid is not less than the second minimum spacing；
The first groove grid of the second groove grid of each cellular and an adjacent cellular in a first direction are to overlap
Same trench gate；The first direction and the second direction are perpendicular.
Preferably, the third trench gate includes being parallel to the first of first direction setting in, third and the 5th side, with
And be parallel to the second of second direction setting while and when the 4th；
Described second while both ends respectively with described first while and third side connect, the both ends on the 4th side respectively with institute
State third while and the 5th while connect；
5th side of third trench gate and third trench gate in an adjacent cellular in a second direction in each cellular
First side overlaps.
Preferably, the size of the cellular is 1.8a × 1.267a；The size of the first groove grid and second groove grid
For 1.8a × 0.2a；The size of the third trench gate is 1.8a × 0.733a；The size of the contact hole is 0.2a × 0.2a；
Distance point of the contact hole to adjacent first groove grid, third trench gate or adjacent second groove grid, third trench gate
Not Wei 0.2a, the distance of the third trench gate to the first groove grid and second groove grid is respectively 0.067a.
It is further preferred that the gully density of the cellular
=[1.8aX2+ (0.2a+a) X2+ (0.533a+0.6a+0.533a) X2]/(1.8aX1.267a)=4.09/a.
It is further preferred that the a=1.5um.
A kind of snakelike layouts increasing VDMOS gully density provided by the embodiment of the utility model, in same area
The grid width of trench gate inside greatly improved, that is, increase the density of channel, to achieve the purpose that reduce VDMOS than conducting resistance.
Detailed description of the invention
Fig. 1 is the bar shaped layouts schematic diagram that the prior art provides；
Fig. 2 is the structure cell schematic diagram in bar shaped layouts provided by the embodiment of the utility model；
Fig. 3 is the sub- shape structure layouts schematic diagram in field that the prior art provides；
Fig. 4 is the delta structure layouts schematic diagram that the prior art provides；
Fig. 5 is the structure cell schematic diagram in the sub- shape structure in field and delta structure that the prior art provides；
Fig. 6 is the hexagon layouts schematic diagram that the prior art provides；
Fig. 7 is the structure cell schematic diagram in the hexagon layouts that the prior art provides；
Fig. 8 is the snakelike layouts schematic diagram provided by the embodiment of the utility model for increasing VDMOS gully density；
Fig. 9 is one of structure cell schematic diagram provided by the embodiment of the utility model；
Figure 10 is the two of structure cell schematic diagram provided by the embodiment of the utility model.
Specific embodiment
Below by drawings and examples, the technical solution of the utility model is described in further detail.
The utility model embodiment provides a kind of snakelike layouts for increasing VDMOS gully density, as shown in figure 8,
The layouts include repeating to arrange along first direction (transverse direction as shown in the figure) and second direction (longitudinal direction as shown in the figure)
Multiple cellulars of column:
Each cellular can include: first groove grid 11, second groove grid 12, third trench gate 13 and two as shown in Figure 9
Contact hole 141,142；Wherein in the structure of repeated arrangement, the second groove grid 12 of each cellular with it is adjacent in a first direction
The first groove grid 11 of one cellular are the same trench gate to overlap；Because second groove grid 12 intracellular are included in ditch in member
The channel width that track density calculates, therefore the composition of cellular is provided in the manner described above.Likewise, third trench gate 13 is second
There is also kindred circumstances for repeated arrangement on direction.
First groove grid 11 are arranged in parallel with second groove grid 12, and third trench gate 13 is that S type is placed in first groove grid 11
Between second groove grid 12；Third trench gate 13 specifically includes be parallel to first direction setting first in, third and the
Five sides, and be parallel to the second of second direction setting while and when the 4th；Second while both ends respectively with first while and third side
Connect, the 4th while both ends respectively with third while and the 5th side connect；In each cellular the 5th side of third trench gate with the
The first side of third trench gate overlaps in an adjacent cellular on two directions.
Contact hole 142 is placed between the third trench gate 13 and the second groove grid 12；Contact hole 141 is placed in described
Between third trench gate 13 and the first groove grid 11 wherein, contact hole is to first groove grid 11, second groove grid 12 and
The spacing of three trench gates 13 is not less than the first minimum spacing as defined in design rule；Third trench gate 13 is to first groove grid
11, the spacing of second groove grid 12 is not less than the second minimum spacing as defined in design rule.
In a preferred example shown in Fig. 9, the size of cellular is 1.8a × 1.267a；First groove grid 11 and second
The size of trench gate 12 is 1.8a × 0.2a；The size of third trench gate 13 is 1.8a × 0.733a；Contact hole 141 and 142
Having a size of 0.2a × 0.2a；Contact hole is to adjacent first groove grid 11, third trench gate 13 or adjacent second groove grid
12, the distance of third trench gate 13 is respectively 0.2a, third trench gate 13 to first groove grid 11 and second groove grid 12 away from
From respectively 0.067a.
Such as a is 1.5um in actual product；The size of cellular is 2.7um × 1.9um；First groove grid 11 and the second ditch
The size of slot grid 12 is 2.7um × 0.3um；The size of third trench gate 13 is 2.7um × 1.1um；The ruler of contact hole 141,142
Very little is 0.3um × 0.3um；The distance of contact hole to adjacent first trenches grid 11, second groove grid 12, third trench gate 13 is distinguished
For 0.3um, the distance of third trench gate 13 to first groove grid 11 and second groove grid 12 is respectively 0.1um.
Gully density is calculated according to the channel perimeter in cellular in unit area/unit area, channel perimeter is thick in figure
Channel width shown by lines is added to obtain.
Therefore the gully density of available cellular
=[1.8aX2+ (0.2a+a) X2+ (0.533a+0.6a+0.533a) X2]/(1.8aX1.267a)=4.09/a.
It can be seen that the gully density of the utility model much larger than matrix pattern structure in the prior art, delta structure and
The gully density of hexagonal structure.So the snakelike layouts of the utility model, compare conducting resistance with smaller.
The structure cell that can obtain the snakelike layouts of the utility model is not limited to one kind shown in figure 9 above,
It can be shown in structure shown in Fig. 10.
By the layouts provided by the embodiment of the utility model for increasing VDMOS gully density, have in same area
There is the grid width of bigger trench gate, that is, increase the density of channel, to achieve the purpose that reduce VDMOS than conducting resistance.Also,
When obtaining same conducting resistance, smaller area is occupied using the structure of the utility model, therefore be conducive to further
Reduce chip area.
Above-described specific embodiment, to the purpose of this utility model, technical scheme and beneficial effects carried out into
One step is described in detail, it should be understood that being not used to limit the foregoing is merely specific embodiment of the present utility model
Determine the protection scope of the utility model, within the spirit and principle of the utility model, any modification for being made equally is replaced
It changes, improve, should be included within the scope of protection of this utility model.
Claims (5)
1. a kind of snakelike layouts for increasing VDMOS gully density, which is characterized in that the snakelike layouts include along the
Multiple cellulars in one direction and second direction repeated arrangement:
The cellular includes: first groove grid, second groove grid, third trench gate and two contact holes；The first groove grid
Arranged in parallel along the second direction with the second groove grid, the third trench gate is S type, is placed in first ditch
Between slot grid and the second groove grid；One contact hole be placed in the third trench gate and the second groove grid it
Between, another described contact hole is placed between the third trench gate and the first groove grid；Wherein, the contact hole is to institute
The spacing for stating first groove grid, second groove grid and third trench gate is not less than the first minimum spacing；The third trench gate
Spacing to the first groove grid, second groove grid is not less than the second minimum spacing；
The first groove grid of the second groove grid of each cellular and an adjacent cellular in a first direction be overlap it is same
One trench gate；The first direction and the second direction are perpendicular.
2. the snakelike layouts according to claim 1 for increasing VDMOS gully density, which is characterized in that the third
Trench gate includes being parallel to the first of first direction setting in, third and the 5th side, and be parallel to second direction setting
Second while and when the 4th；
Described second while both ends respectively with described first while and third side connect, the both ends on the 4th side are respectively with described
Three while and the 5th while connect；
5th side of third trench gate and first of third trench gate in an adjacent cellular in a second direction in each cellular
While overlapping.
3. the snakelike layouts according to claim 1 for increasing VDMOS gully density, which is characterized in that the cellular
Size be 1.8a × 1.267a；The size of the first groove grid and second groove grid is 1.8a × 0.2a；The third ditch
The size of slot grid is 1.8a × 0.733a；The size of the contact hole is 0.2a × 0.2a；The contact hole is to adjacent first
The distance of trench gate, third trench gate or adjacent second groove grid, third trench gate is respectively 0.2a, the third groove
The distance of grid to the first groove grid and second groove grid is respectively 0.067a.
4. the snakelike layouts according to claim 3 for increasing VDMOS gully density, which is characterized in that the cellular
Gully density=[1.8aX2+ (0.2a+a) X2+ (0.533a+0.6a+0.533a) X2]/(1.8aX1.267a)=4.09/a.
5. the snakelike layouts according to claim 3 for increasing VDMOS gully density, which is characterized in that the a=
1.5um。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821420851.1U CN208570602U (en) | 2018-08-30 | 2018-08-30 | A kind of snakelike layouts increasing VDMOS gully density |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821420851.1U CN208570602U (en) | 2018-08-30 | 2018-08-30 | A kind of snakelike layouts increasing VDMOS gully density |
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| CN208570602U true CN208570602U (en) | 2019-03-01 |
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| CN201821420851.1U Withdrawn - After Issue CN208570602U (en) | 2018-08-30 | 2018-08-30 | A kind of snakelike layouts increasing VDMOS gully density |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108899318A (en) * | 2018-08-30 | 2018-11-27 | 无锡摩斯法特电子有限公司 | A kind of snakelike layouts and layout method increasing VDMOS gully density |
-
2018
- 2018-08-30 CN CN201821420851.1U patent/CN208570602U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108899318A (en) * | 2018-08-30 | 2018-11-27 | 无锡摩斯法特电子有限公司 | A kind of snakelike layouts and layout method increasing VDMOS gully density |
| CN108899318B (en) * | 2018-08-30 | 2024-01-26 | 无锡摩斯法特电子有限公司 | Serpentine layout structure and layout method for increasing VDMOS channel density |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A serpentine structure for increasing channel density of VDMOS Effective date of registration: 20200911 Granted publication date: 20190301 Pledgee: Bank of China Wuxi Binhu sub branch Pledgor: WUXI MOSIFATE ELECTRONIC Co.,Ltd. Registration number: Y2020320010144 |
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| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20210628 Granted publication date: 20190301 Pledgee: Bank of China Wuxi Binhu sub branch Pledgor: WUXI MOSIFATE ELECTRONIC Co.,Ltd. Registration number: Y2020320010144 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A serpentine layout structure for increasing channel density of VDMOS Effective date of registration: 20210629 Granted publication date: 20190301 Pledgee: Bank of China Wuxi Binhu sub branch Pledgor: WUXI MOSIFATE ELECTRONIC Co.,Ltd. Registration number: Y2021980005498 |
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| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20190301 Effective date of abandoning: 20240126 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20190301 Effective date of abandoning: 20240126 |