CN208570601U - A kind of layouts increasing VDMOS gully density - Google Patents
A kind of layouts increasing VDMOS gully density Download PDFInfo
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- CN208570601U CN208570601U CN201821420833.3U CN201821420833U CN208570601U CN 208570601 U CN208570601 U CN 208570601U CN 201821420833 U CN201821420833 U CN 201821420833U CN 208570601 U CN208570601 U CN 208570601U
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- groove grid
- trench gate
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- groove
- contact hole
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- 230000001413 cellular effect Effects 0.000 claims abstract description 33
- 230000003834 intracellular effect Effects 0.000 claims abstract description 9
- 210000004027 cell Anatomy 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The utility model embodiment is related to a kind of layouts for increasing VDMOS gully density, and the structure includes multiple cellulars along first direction and second direction repeated arrangement: each cellular includes first groove grid, second groove grid, third trench gate and contact hole；The second groove grid of each cellular and the first groove grid of an adjacent cellular in a first direction are the same trench gate to overlap；First groove grid are arranged in parallel with second groove grid, and third trench gate and contact hole are placed between first groove grid and second groove grid；First direction is the direction of vertical first groove grid and second groove grid；Second direction is the direction of parallel first groove grid and second groove grid；Contact hole to first groove grid, the spacing of second groove grid, contact hole to the member spacing of third trench gate and the spacing of adjacent member third trench gate intracellular intracellular is not less than the first minimum spacing；The spacing of third trench gate to first groove grid, second groove grid is not less than the second minimum spacing.
Description
Technical field
The utility model relates to power semiconductor technologies field more particularly to a kind of Bututs for increasing VDMOS gully density
Structure.
Background technique
Mesolow trench-gate vertical double diffused metal-oxide semiconductor field effect transistor (VDMOS) conducting at present
Resistance is mainly made of several parts such as channel resistance, epitaxial electric resistance, source and drain resistance, metallic resistance and resistance substrates, wherein channel
What resistance typically constituted from entire conducting resistance 25%~50% differs, and epitaxial electric resistance accounts for the 35%~60% of entire conducting resistance,
What remaining part sub-resistance summation accounted for entire conducting resistance 5%~10% differs.And determine the significant portion factor and ditch of channel resistance
Density is related in the unit area of slot grid.
Trench gate VDMOS generally realizes specified conducting resistance, member in parallel using the Butut mode of multiple cellular parallel connections
Then more low corresponding chip area is also bigger (cost is also higher) for the conducting resistance of the more groove VDMOS of born of the same parents, to realize in phase
How smaller chip area in the case where with specified conducting resistance is obtained with realizing lower cost in unit chip area
Obtaining channel width, that is, higher gully density big as far as possible (reducing than conducting resistance) becomes extremely important.The groove of mainstream at present
The channel domain of grid VDMOS includes: strip structure as shown in Figure 1, is made of cellular as shown in Figure 2；As shown in Figure 3
The sub- shape structure in field and delta structure as shown in Figure 4, the two are made of cellular as shown in Figure 5；As shown in FIG. 6 six
The structure of side shape is made of cellular as shown in Figure 7.
The composition of design for different structures, cellular is different, this also determines cellular interior raceway groove under unit area
The difference of density.It is set as a, groove width 0.2a, aperture 0.2a, the phase that hole is 0.2a to groove distance in unit length
With under the conditions of, the gully density of strip structure shown in FIG. 1: cellular channel perimeter/cell density=2a/ (a*a)=2/a, Fig. 3
Shown in field sub- shape structure and delta structure as shown in Figure 4 gully density: cellular channel perimeter/cell density=
2.4a/ (a*a)=2.4/a, the gully density of the structure of hexagon shown in fig. 6: cellular channel perimeter/cell density=
2.078a/ (a*0.866a)=2.4/a.Wherein channel perimeter is marked in figure with heavy line.It can be seen that gully density: rectangular
Structure=hexagonal structure > strip structure, but maximum is also only 2.4/a.
In order to further decrease the conducting resistance of VDMOS, it is also necessary to be further improved on layouts.
Utility model content
The purpose of the utility model is to provide a kind of layouts for increasing VDMOS gully density, can be in same area
The grid width of trench gate is inside greatly improved, that is, increases the density of channel, to achieve the purpose that reduce VDMOS than conducting resistance.
For this purpose, the utility model embodiment provides a kind of layouts for increasing VDMOS gully density, including along first
Multiple cellulars in direction and second direction repeated arrangement:
Each cellular includes: first groove grid, second groove grid, third trench gate and contact hole；Wherein each cellular
Second groove grid and the first groove grid of an adjacent cellular in a first direction are the same trench gate to overlap；Described
One trench gate is arranged in parallel with the second groove grid, and the third trench gate and contact hole are placed in the first groove grid and institute
It states between second groove grid；The first direction is the direction of vertical the first groove grid and the second groove grid；It is described
Second direction is the direction of parallel the first groove grid and the second groove grid；Wherein, the contact hole is to described first
Trench gate, the spacing of second groove grid are not less than the first minimum spacing；The third trench gate is to the first groove grid,
The spacing of two trench gates is not less than the second minimum spacing；The contact hole to member third trench gate intracellular spacing with
And the spacing away from adjacent member third trench gate intracellular is not less than first minimum spacing.
Preferably, the cellular width is unit size a；The size of the first groove grid and second groove grid is
1.067a×0.2a；The size of the third trench gate is 0.467a × 0.467a；The size of the contact hole be 0.2a ×
0.2a；The distance of the contact hole to the third trench gate is 0.2a, the contact hole to the first groove grid and second
The distance of trench gate is respectively 0.2a, and the distance of the third trench gate to the first groove grid and second groove grid is respectively
0.067a。
It is further preferred that the gully density of the cellular=(2a+0.467a × 4)/(a × 1.067a)=3.625/a.
Preferably, a=1.5um.
A kind of layouts increasing VDMOS gully density provided by the embodiment of the utility model are big in same area
Width improves the grid width of trench gate, that is, increases the density of channel, to achieve the purpose that reduce VDMOS conducting resistance.
Detailed description of the invention
Fig. 1 is the bar shaped layouts schematic diagram that the prior art provides；
Fig. 2 is the structure cell schematic diagram in bar shaped layouts provided by the embodiment of the utility model；
Fig. 3 is the sub- shape structure layouts schematic diagram in field that the prior art provides；
Fig. 4 is the delta structure layouts schematic diagram that the prior art provides；
Fig. 5 is the structure cell schematic diagram in the sub- shape structure in field and delta structure that the prior art provides；
Fig. 6 is the hexagon layouts schematic diagram that the prior art provides；
Fig. 7 is the structure cell schematic diagram in the hexagon layouts that the prior art provides；
Fig. 8 is the layouts schematic diagram provided by the embodiment of the utility model for increasing VDMOS gully density；
Fig. 9 is one of structure cell schematic diagram provided by the embodiment of the utility model；
Figure 10 is the two of structure cell schematic diagram provided by the embodiment of the utility model.
Specific embodiment
Below by drawings and examples, the technical solution of the utility model is described in further detail.
The utility model embodiment provides a kind of layouts for increasing VDMOS gully density, as shown in figure 8, the cloth
Graph structure includes along first direction (transverse direction as shown in the figure) and second direction (longitudinal direction as shown in the figure) repeated arrangement
Multiple cellulars:
Each cellular can include: first groove grid 11, second groove grid 12, third trench gate 13 and contact as shown in Figure 9
Hole 14；Wherein in the structure of repeated arrangement, the second groove grid 12 of each cellular and an adjacent cellular in a first direction
First groove grid 11 be the same trench gate to overlap；That is, it includes: that substantially repetitive structure, which may be considered,
One trench gate 11, third trench gate 13 and contact hole 14.But because second groove grid 12 intracellular are included in gully density in member
The channel width of calculating, therefore the composition of cellular is provided in the manner described above.
First groove grid 11 are arranged in parallel with second groove grid 12, and third trench gate 13 and contact hole 14 are placed in first groove
Between grid 11 and second groove grid 12；First direction, i.e., transverse direction as shown in the figure are vertical first groove grid and second groove
The direction of grid；Second direction, i.e., longitudinal direction as shown in the figure are the direction of parallel first groove grid and second groove grid；Wherein,
The spacing of contact hole 14 to first groove grid 11, second groove grid 12 is not less than the first minimum spacing as defined in design rule；
The spacing of third trench gate 13 to first groove grid 11, second groove grid 12 is not less than between the second minimum as defined in design rule
Away from；Spacing of the contact hole 14 to the spacing of member third trench gate 13 intracellular and away from adjacent member third trench gate 13 intracellular is equal
Not less than the first minimum spacing.
In a preferred example shown in Fig. 9, cellular width is unit size a；First groove grid 11 and second groove
The size of grid 12 is 1.067a × 0.2a；The size of third trench gate 13 is 0.467a × 0.467a；The size of contact hole 14 is
0.2a×0.2a；The distance of contact hole 14 to third trench gate 13 is 0.2a, and contact hole 14 arrives first groove grid 11 and the second ditch
The distance of slot grid 12 is respectively 0.2a, and the distance of third trench gate 13 to first groove grid 11 and second groove grid 12 is respectively
0.067a。
Such as cellular width is 1.5um in actual product；The size of first groove grid 11 and second groove grid 12 is 1.6um
×0.3um；The size of third trench gate 13 is 0.7um × 0.7um；The size of contact hole 14 is 0.3um × 0.3um；Contact hole
The distance of 14 to third trench gate 13 is 0.3um, the distance difference of contact hole 14 to first groove grid 11 and second groove grid 12
For 0.3um, the distance of third trench gate 13 to first groove grid 11 and second groove grid 12 is respectively 0.1um.
Gully density is calculated according to the channel perimeter in cellular in unit area/unit area, channel perimeter is thick in figure
Channel width shown by lines is added to obtain.
Therefore gully density=(2a+0.467a × 4)/(a × 1.067a)=3.625/a of available cellular.Thus
As it can be seen that the gully density of the utility model is much larger than matrix pattern structure, delta structure and hexagonal structure in the prior art
Gully density.So the layouts of the utility model, compare conducting resistance with smaller in identical chips area.
The structure cell that can obtain the layouts of the utility model is not limited to one kind shown in figure 9 above, may be used also
To include other structure cells that other can splice to obtain structure shown in Fig. 8, such as structure shown in Fig. 10.
By the layouts provided by the embodiment of the utility model for increasing VDMOS gully density, can be improved identical
The grid width of area internal channel grid, that is, increase the density of channel, to achieve the purpose that the ratio conducting resistance for reducing VDMOS.Also,
When obtaining same conducting resistance, smaller area is occupied using the structure of the utility model, therefore be conducive to further
Reduce chip area.
Above-described specific embodiment, to the purpose of this utility model, technical scheme and beneficial effects carried out into
One step is described in detail, it should be understood that being not used to limit the foregoing is merely specific embodiment of the present utility model
Determine the protection scope of the utility model, within the spirit and principle of the utility model, any modification for being made equally is replaced
It changes, improve, should be included within the scope of protection of this utility model.
Claims (4)
1. a kind of layouts for increasing VDMOS gully density, which is characterized in that the layouts include along first direction and
Multiple cellulars of second direction repeated arrangement:
Each cellular includes: first groove grid, second groove grid, third trench gate and contact hole；Wherein the second of each cellular
Trench gate and the first groove grid of an adjacent cellular in a first direction are the same trench gate to overlap；First ditch
Slot grid are arranged in parallel with the second groove grid, and the third trench gate and contact hole are placed in the first groove grid and described the
Between two trench gates；The first direction is the direction of vertical the first groove grid and the second groove grid；Described second
Direction is the direction of parallel the first groove grid and the second groove grid；Wherein, the contact hole is to the first groove
Grid, second groove grid spacing be not less than the first minimum spacing；The third trench gate is to the first groove grid, the second ditch
The spacing of slot grid is not less than the second minimum spacing；The contact hole to member third trench gate intracellular spacing and away from
The spacing of adjacent member third trench gate intracellular is not less than first minimum spacing.
2. the layouts according to claim 1 for increasing VDMOS gully density, which is characterized in that the cellular width
For unit size a；The size of the first groove grid and second groove grid is 1.067a × 0.2a；The ruler of the third trench gate
Very little is 0.467a × 0.467a；The size of the contact hole is 0.2a × 0.2a；The contact hole is to the third trench gate
Distance is 0.2a, and the distance of the contact hole to the first groove grid and second groove grid is respectively 0.2a, the third ditch
The distance of slot grid to the first groove grid and second groove grid is respectively 0.067a.
3. the layouts according to claim 2 for increasing VDMOS gully density, which is characterized in that the ditch of the cellular
Track density=(2a+0.467a × 4)/(a × 1.067a)=3.625/a.
4. the layouts according to claim 2 for increasing VDMOS gully density, which is characterized in that a=1.5um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821420833.3U CN208570601U (en) | 2018-08-30 | 2018-08-30 | A kind of layouts increasing VDMOS gully density |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821420833.3U CN208570601U (en) | 2018-08-30 | 2018-08-30 | A kind of layouts increasing VDMOS gully density |
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| CN208570601U true CN208570601U (en) | 2019-03-01 |
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| CN201821420833.3U Withdrawn - After Issue CN208570601U (en) | 2018-08-30 | 2018-08-30 | A kind of layouts increasing VDMOS gully density |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108899319A (en) * | 2018-08-30 | 2018-11-27 | 赵少峰 | A kind of layouts and layout method increasing VDMOS gully density |
-
2018
- 2018-08-30 CN CN201821420833.3U patent/CN208570601U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108899319A (en) * | 2018-08-30 | 2018-11-27 | 赵少峰 | A kind of layouts and layout method increasing VDMOS gully density |
| CN108899319B (en) * | 2018-08-30 | 2024-01-26 | 赵少峰 | Layout structure and layout method for increasing channel density of VDMOS |
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