CN208445569U - A kind of storage analytical equipment of acquisition in real time - Google Patents

Abstract

The utility model discloses a kind of storage analytical equipments of acquisition in real time, the CPU computer plate that VPX including setting VPX back panel and front panel reinforces cabinet and connect with VPX back panel and mutually communicate respectively, Receiver Module, data acquisition module, data memory module, fiber optic telecommunications module, the data acquisition module includes the first FPGA and a broadband A/D C chipset connecting respectively with the first FPGA, one narrowband ADC chipset, five groups of backplane interfaces of SRIO × 4, one group of interface of PCIE × 4, first FPGA connects four data memory modules by four groups of backplane interfaces of SRIO × 4 in five groups of backplane interfaces of SRIO × 4 simultaneously and carries out data storage, the first FPGA passes through another group of SR in five groups of backplane interfaces of SRIO × 4 simultaneously The backplane interface of IO × 4, the interface of PCIE × 4 connection CPU computer plate carry out data processing.Real-time acquisition, storage, the analysis of high-speed data may be implemented in the utility model, and complete machine configures, is easy to use.

Description

A kind of storage analytical equipment of acquisition in real time

Technical field

The utility model belongs to data acquisition storage analytical equipment field, is a kind of acquisition storage point in real time specifically Desorption device.

Background technique

With development in science and technology, data processing field needs to acquire some data in real time, stores, analyzes.But it passes The user data acquisition system based on the website PC and access log of system had both been unable to satisfy high speed, real-time data processing capacity Demand, and can not be integrated into a complete machine, i.e., performance is bad and occupies larger space.

Utility model content

Aiming at the problems and shortcomings existing in the prior art, the purpose of this utility model is to provide a kind of acquisitions in real time to deposit Analytical equipment is stored up, first is that can be achieved after being sampled using ADC chip, carrying out digitized processing inside FPGA to wider dynamic model It encloses, the monitoring of the signals such as more muting sensitivity signal of communication, data-link signal, radar signal, to reach timely collection data Performance requirement；Second is that complete machine realizes broadband/narrowband monitoring, storage, signal analysis function.

The utility model is achieved through the following technical solutions: a kind of storage analytical equipment of acquisition in real time, including setting VPX are carried on the back The VPX of plate reinforces cabinet and connect respectively with VPX back panel and the CPU computer that mutually communicates, Receiver Module, data are adopted Collect module, data memory module, fiber optic telecommunications module, it is characterised in that: the data acquisition module includes a fpga chip And a broadband A/D C chipset, a narrowband ADC chipset, the five groups of backboards of SRIO × 4 connecting respectively with fpga chip connect Mouth, one group of interface of PCIE × 4, fpga chip pass through four groups of backplane interfaces of SRIO × 4 in five groups of backplane interfaces of SRIO × 4 simultaneously Connect four data memory modules and carry out data storages, at the same fpga chip pass through it is another in five groups of backplane interfaces of SRIO × 4 The group backplane interface of SRIO × 4, the interface of PCIE × 4 connection CPU computer carry out data processing.

Further, in order to preferably realize that the utility model, the broadband A/D C chipset can be configured to 1 channel The ADC of the ADC or 4 channel 5GSa/12bit of the ADC of 20GSa/12bit or 2 channel 10GSa/12bit；The narrowband ADC Chipset can be configured to the ADC of 2 channel 1GSa/14bit, and the ADC chip of narrowband ADC chipset by JESE204 interface with Fpga chip connection.

Further, in order to preferably realize the utility model, the data acquisition module further includes and fpga chip connects The DDR3 memory modules of the staggeredly caching of the two groups of 64bit connect.

Further, in order to preferably realize the utility model, the data acquisition module further includes and fpga chip connects The first clock module, the first power module connect.

Further, in order to preferably realize the utility model, the Receiver Module include second power supply module with And by second power supply module power supply preposition pre-selection machine low noise unit, converter unit, intermediate frequency unit, frequency synthesizer unit, monitoring and Communication unit, the preposition pre-selection machine low noise unit access converter unit and converter unit, frequency synthesizer unit simultaneously with intermediate frequency list Member connection, intermediate frequency unit output end connection monitoring and communication unit connection, i.e., external input signal is through preposition pre-selection machine low noise It is output to converter unit after unit pre-selection filtering, frequency synthesizer unit generates intermediate-freuqncy signal after repeatedly mixing with the signal of converter unit, It is exported after monitoring and communication unit monitoring are adjusted again.

Further, in order to preferably realize the utility model, the preposition pre-selection machine low noise unit include limiter, First ATT chip, SPDT switch, the first LAN low-noise amplifier, the 2nd LAN low-noise amplifier, the 2nd ATT chip, third ATT chip, the first SP3T analog switch, the 2nd SP3T analog switch, the 3rd SP3T analog switch, the 4th SP3T analog switch, First filter, second filter, third filter, the 4th filter.

The limiter, the first ATT chip, the first SPDT switch are sequentially connected.

One branch of first SPDT switch connects first by the first LAN low-noise amplifier, the 2nd ATT chip SP3T analog switch, the first SP3T analoging switch output end are first divided into two with first filter, with second filter Branch accesses the 2nd SP3T analog switch again.

Another branch of the SPDT switch meets the 3rd SP3T by the 2nd LAN low-noise amplifier, the 3rd ATT chip Analog switch, the 3rd SP3T analoging switch output end are first divided into third filter, with two branches of the 4th filter The 4th SP3T analog switch is accessed again.

Further, in order to preferably realize the utility model, the frequency synthesizer unit includes three local oscillation circuits and difference Generate tri- local oscillation signals of LO1, LO2, LO3；The converter unit include the first frequency mixer, the second frequency mixer, third frequency mixer, 5th filter, the 6th filter, the second SPDT switch, the first AMP amplifier.

The first frequency mixer, the 5th filter that the 2nd SP3T analoging switch output end passes through input LO1 local oscillation signal The input terminal of the second SPDT switch is connect, while the 4th SP3T analoging switch output end is directly connected to the input of the second SPDT switch End.

The output end of second SPDT switch passes sequentially through the second frequency mixer of input LO2 local oscillation signal, the 6th filtering Device, the first AMP amplifier, the third frequency mixer connection for inputting LO3 local oscillation signal.

Further, in order to preferably realize the utility model, the intermediate frequency unit includes sequentially connected 7th filtering Device, the 4th ATT chip, the 2nd AMP amplifier；The output of the third frequency mixer terminates the 7th filter；2nd AMP is put The signal output end of big device is connect with monitoring and communication unit.

Further, in order to preferably realize the utility model, the data memory module include FPGA system master control with And connect respectively with FPGA system master control PowerPC master control, at least one comply with standard the SSD hard disk of SATA3 agreement, front Connector for substrate, VPX connector；The FPGA system master control passes through VPX connector and VPX back panel communication connection, while FPGA system System master control is connect by front-panel connector with fiber optic telecommunications module.

Further, in order to preferably realize the utility model, the quantity of the SSD hard disk is not less than 16, and single The memory capacity of SSD hard disk is 2TB.

The utility model compared with prior art, have the following advantages that and the utility model has the advantages that

(1) the utility model provides a kind of storage analytical equipment of acquisition in real time, and adopting in real time for high-speed data may be implemented Collection, storage, analysis, and complete machine configures, is easy to use.

(2) data acquisition module of the utility model supports 1 channel 20GSa/12bit sampling or 2 channel 10GSa/12bit Or 4 channel 5GSa/12bit and 2 channel 1GSa/14bit samplings, the DDR3 of two groups of 64bit is staggeredly cached, and utilizes ADC core Piece highest can realize that 20GSa/s 12bit is sampled.

(3) the data memory module acquisition and recording process of the utility model is participated in without OS, full FPGA data acquisition and directly High speed SSD disk is written, framework is succinct, data flow is short, high reliablity；Agreement is written in high speed SATA3 6Gbs data, mature Framework is concurrently written, single-deck, which stablizes lasting write-in, can achieve 400MBs or more.

Detailed description of the invention

Fig. 1 is the structural block diagram of the utility model.

Fig. 2 is the structural block diagram of data acquisition module.

Fig. 3 is E2V12AS350A chip block diagram.

Fig. 4 is E2V12AS350A chip interior phase diagram.

Fig. 5 is data FFT processing schematic after data sorting device.

Fig. 6 is the structural block diagram of data memory module.

Fig. 7 is the working principle schematic block diagram of Receiver Module.

Specific embodiment

Embodiment 1:

A kind of storage analytical equipment of acquisition in real time, the VPX including setting VPX back panel and front panel reinforce cabinet and difference CPU computer, Receiver Module, data acquisition module, data memory module, the light for connecting with VPX back panel and mutually communicating Fiber communication module, it is characterised in that: the data acquisition module includes a fpga chip and connect respectively with fpga chip A broadband A/D C chipset, a narrowband ADC chipset, five groups of backplane interfaces of SRIO × 4, one group of interface of PCIE × 4, Fpga chip connects four data by four groups of backplane interfaces of SRIO × 4 in five groups of backplane interfaces of SRIO × 4 simultaneously and stores mould Block carries out data storage, at the same fpga chip by another group of backplane interface of SRIO × 4 in five groups of backplane interfaces of SRIO × 4, The interface of PCIE × 4 connects CPU computer and carries out data processing.

In the present embodiment, illustrated as shown in Figure 1, acquiring storage analytical equipment in real time with a kind of 20GSa/s@128TB, Device model is GR510.Data processing core is X86 computer plate in CPU computer in GR510；Receiver Module uses 400MHz ~ 26.5GHz Receiver Module；Data acquisition module uses 20G@12bit data acquisition module；Data memory module Using 4 5GB/s@32TB data memory modules；Fiber optic telecommunications module uses 10,000,000,000 nets/fiber interface module.The VPX is reinforced Cabinet has display screen and keyboard, runs on 2012 platform of Windows Server.

That is 20GSa/s 128TB acquires storage analytical equipment in real time, including VPX reinforces cabinet, VPX back panel, CPU computer And 1 400MHz ~ 26.5GHz Receiver Module, 1 20G@12bit data acquisition module, 4 5GB/s@32TB data Memory module, 10,000,000,000 nets/fiber interface module.The VPX back panel simultaneously with 1 400MHz ~ 26.5GHz Receiver Module, 1 20G@12bit data acquisition module, 4 5GB/s@32TB data memory modules, 10,000,000,000 nets/fiber interface module, X86 is opened to calculate Machine plate, 10,000,000,000 nets/fiber interface module, display, keyboard connection.

Wherein, the data acquisition module includes broadband A/D C chipset, narrowband ADC chipset.The narrowband ADC chip Group is the ADC chip of 2 channel 1GSa/14bit, and the ADC chip of narrowband ADC chipset passes through JESE204 interface and FPGA core Piece connection.

The broadband A/D C chipset is the ADC chip of 1 channel 20GSa/12bit.Alternatively, the broadband A/D C chipset is The ADC chip of 2 channel 10GSa/12bit.Alternatively, the broadband A/D C chipset is the ADC chip of 4 channel 5GSa/12bit.

At this point, the analog signal down coversion of the achievable 400MHz ~ 26.5GHz of GR510,10GSa/s@12bit zero intermediate frequency IQ Acquisition or 20GSa/12bit acquire storage in real time, and complete machine maximum storage capacity is 128TB, using 10,000,000,000 nets/optical fiber to collecting Data unloaded.GR510 is sampled using the ADC chip on data acquisition module, is carried out number inside fpga chip The monitoring to more wide dynamic range, more muting sensitivity signal of communication, data-link signal, radar signal can be achieved after change processing, i.e., Complete machine can realize broadband/narrowband monitoring, storage, signal analysis function.

Embodiment 2:

The present embodiment optimizes on the basis of embodiment 1, as shown in Fig. 2, the data acquisition module uses equipment The data acquisition module of model GR6528, modular structure are 6U VPX ,+12V power supply, power consumption: 70W.Wherein, fpga chip Chip model is XC7V690T-1927.The chip model of the ADC chip is E2V12AS350A.

The connection of the ADC chip of fpga chip and 12bit passes through the ADC chip of JESE204 interface and 14bit@1GSa/s Connection is connect, by the interface of SRIO × 4 interfaces/PCIE × 4 and CPU computer with data memory module by the interface of SRIO × 4 Connection.It is connected between fpga chip and data memory module by the interface of SRIO × 4, rate 3.125Gbps.

The backplane interface of data acquisition module described in the present embodiment has: 4 groups of interfaces of SRIO × 4, rate 5Gbps are used for High-speed transfer；1 group of interface of SRIO × 4, for controlling；1 group of interface of PCIe × 4, for controlling.

At this point, data acquisition module highest described in the present embodiment can realize that 20GSa/s 12bit is sampled.

Further, broadband A/D C chipset is the ADC chip of 1 20GSa/12bit or the ADC of 2 10GSa/12bit The ADC chip of chip or 4 5GSa/12bit.

The first design: it when the ADC chip configuration that broadband A/D C chipset is 1 channel 20GSa/12bit, is handed over using 4 It knits, AC coupled, the connection type of external power splitter, frequency 1GHz is inputted using rate 20Gsa/s, number of significant digit 6bit@at this time.

Second of design: it when the ADC chip configuration that broadband A/D C chipset is 2 channel 10GSa/12bit, is handed over using each 2 It knits, AC coupled, the connection type of external power splitter, frequency is inputted using rate 10Gsa/s, number of significant digit 6.5bit@at this time 1GHz supports IQ synchronized sampling.

The third design: broadband A/D C chipset be 4 channel 5GSa/12bit ADC chip configuration when, using rate 5Gsa, Number of significant digit 7.8bit@inputs frequency 1GHz, supports 4 channel parallel operations.The analog signal of data acquisition module input, first By 4 function point, it is separately input to 4 E2V12AS350A chips；4 ADC chips carry out high speed interleave samples, adopt per a piece of Sample rate is 5GSPS, and 4 are completed the sampling of 20GSPS altogether.

Further, fpga chip is internally provided with FFT module.

As shown in figure 5, when DDC high-speed data is to parallel FFT module, data first pass through data sorting device, by data point For the data matrix of multiple N point × M phases, M phase data is inputted in corresponding M phase FFT later, and the result data after finishing FFT is simultaneously Row output.

That is, GR6528 data acquisition module 1 channel 20GSa/12bit of support sampling (or 2 channel 10GSa/ 12bit or 4 channel 5GSa/12bit) and 2 channel 1GSa/14bit sampling, the DDR3 of two groups of 64bit, which interlocks, to be cached, and back is passed through The interface of multiple groups SRIO × 4 of plate is quickly transferred to data memory module or CPU computer.At this point, in IQ mode, accurate low mistake The compensation that difference and low temperature float can complete binary channels 10GSa/@12bit sampling；In 14bit@1GSa/s sampling configuration, that is, narrowband mould When formula, it can handle in real time and FFT.

In the present embodiment, as shown in figure 3, using E2V12AS350A device as the ADC chip in broadband A/D C chipset, Realize high speed analog-to-digital conversion.Program-controlled intersection analog switch built in the device supports 4 channel 1.35GHz/12bit, 2 channels The operating modes such as 2.7GHz/12bit and 1 channel 5.4GHz/12bit, the signal bandwidth maximum 4.2GHz of each input channel, have Effect digit highest 7.9, no spuious dynamic (SFDR) are -55dBc, and the operating mode in each channel, gain, biasing, phase The poor parameters such as (sampling clock delay) and input impedance can realize adjustment, thus really by SPI serial line interface programming Control Guarantee consistency when protecting four channel interlaced samplings.4 road ADC cores differ 90 ° of when clock by 4 tunnels inside E2V12AS350A Interlaced sampling processed realizes 5.4GHz sampling rate.For the data consistency for guaranteeing interlaced sampling, it is necessary to accurate to control the inclined of four tunnels It sets, gain, frequency response, Amplitude-Phase, delay, the parameters such as noise and shake, is consistent it, needs to pass through full bandwidth thus Accurate calibration and compensation realize consistency.

Further, the data acquisition module also sets up the first clock module and trigger circuit.When using external reference Clock, frequency 100MHz, power+5dBm, sine wave, jitter≤150fs, support External Reference, internal reference, outer triggering signal, LVPECL level.

Further, the data acquisition module uses 6U VPX standard, acts on ANSI/VITA 46.0-2007 correlation rule Model requirement, is powered using backboard+5V and+12V.

The other parts of the present embodiment are same as Example 1, and so it will not be repeated.

Embodiment 3:

The present embodiment optimizes on the basis of embodiment 1 or 2, sets as shown in fig. 6, the data memory module uses The data memory module of standby model GR6126.The data memory module include FPGA system master control and respectively with FPGA system The PowerPC master control of system master control connection, at least one SSD hard disk, front-panel connector, VPX for complying with standard SATA3 agreement connect Connect device；The FPGA system master control is by VPX connector and VPX back panel communication connection, while FPGA system master control passes through front Connector for substrate is connect with fiber optic telecommunications module.

GR6126 data memory module be 6U VPX memory module, be based on 7 Series FPGA of Xilinx, realize RapidIO, The record playback of the interface protocols such as PCI Express, 10G Ethernet, Gigabit Ethernet.Onboard high-performance PowerPC Realize file system management.Storage medium is 16 SSD hard disks, and veneer maximum capacity is 32TB, it can be achieved that 6.5GB/s data connect Continuous record and playback.

The GR6126 data memory module support module cascade, realizes capacity extension；Support module is in parallel, passes through MPO Optical port realizes that intermodule is in parallel, realizes capacity and bandwidth expansion；Optical fiber interface include 1 12 core sending port of MPO, 1 MPO12 core receiving port, 2 road 10G Ethernet, 1 road Gigabit Ethernet；Ethernet uses RJ45 interface Gigabit Ehernet。

The other parts of the present embodiment are identical as embodiment 1 or 2, and so it will not be repeated.

Embodiment 4:

The present embodiment optimizes on the basis of embodiment any one of 1-3, the model of the FPGA system master control XC7VX690T-2FFG1927I, has 80 GTH, and single GTH rate can arrive 28.05Gb/s, while integrated 3 PCIe3.0 control Device processed.

The model T2080NXN8TTB of the PowerPC master control, has 4 core, 8 thread, and monokaryon 1.8GHz provides 16 Serdes high-speed interface supports the interfaces such as PCIe, XFI, SRIO.

The model Samsung 850Pro of the SSD hard disk, single-deck 2TB, writing speed can arrive 520MB/s, and read rate can arrive 540MB/s。

In the present embodiment, FPGA system master control utilizes its concurrent and high data bit width characteristic, realizes high-speed data acquisition, deposits Storage and playback operate 16 SSD hard disks, the superposition of realization theory read or write speed using RAID0 mode；Furthermore FPGA system master control Data exchange is carried out by SATA3.0 interface and SSD hard disk.It is connect between FPGA system master control and PowerPC master control for SATA3.0 Mouthful, high speed document management information exchange channel is provided.The SATA3.0 standard speed is 6Gb/s, and the capacity of 1 SSD hard disk is 2T, the capacity of 16 SSD hard disks are 32T.Data memory module can reach 32B memory capacity and 6Gb/s data in the present embodiment The performance of readwrite bandwidth.

Interface and optical interface on the VPX can all realize data acquisition and playback.

Data record (is memory bandwidth, be also record bandwidth): data input (such as GTH, MPO) from board external interface, FPGA system master control is reached, then by FPGA system master control write-in SSD hard disk.

Data readback (recalls and puts bandwidth): FPGA reads data from SSD hard disk, is exported by external interface.

Each link in data record and playback path can have an impact data bandwidth, data bandwidth mainly by It is limited to three links: the performance (interface bandwidth performance) of external interface, processor performance (processor hardware performance and software Can), SSD hard disk performance.The continuous data recording and playback bandwidth for realizing 6Gb/s, need each link that will work to connecing Nearly theoretical velocity, design difficulty are very big.

In the present embodiment, based on the 6Gb/s memory module of the mono- slot structure of VPX, using FPGA+PowerPC, FPGA is plug-in SSD hard-disc storage group structure realizes data storage function.High-speed data acquisition playback interface and SSD are realized in FPGA system master control Disk read-write, PowerPC master control realize that file system management and 10,000,000,000 network datas import and export interface, FPGA system master control and Data exchange is carried out by PCIe3.0 bus between PowerPC master control.The memory module major function list:

1. supporting the record of fiber data, playback；

2. the circulation covering of disk is supported to write；

3. supporting 16 solid state hard disks, every capacity is 2T；

4. supporting 6Gb/s reading and writing data bandwidth；

5. supporting the export of acquisition data, deleting；

6. supporting power down abnormal restoring.

In order to preferably realize the utility model, further, the FPGA system master control, PowerPC master control are all connected with There is DDR3 cache module.

The other parts of the present embodiment are identical as any one of embodiment 1-3, and so it will not be repeated.

Embodiment 5:

The present embodiment optimizes on the basis of embodiment any one of 1-4, as shown in fig. 7, the Receiver Module Use device model for the Receiver Module of GR6219.The GR6219 Receiver Module, 400MHz ~ 26.5GHz radio frequency Down coversion, instant bandwidth 4GHz have the output of 100MHz reference clock；All radiofrequency signals are rear outlet mode, using VPX Mixed loading connector.The GR6219 Receiver Module, operating mode are to directly amplify filtering+double conversion mode；Input frequency Rate range is 400MHz ~ 26.5GHz；Input power range is -75dBm ~ 0dBm；Analog bandwidth have 400MHz, 1GHz, 2GHz, 4GHz software may be selected；Output mode is the output of IQ zero intermediate frequency；Link gain: 0 ~ 40dB, stepping 1dB.

The other parts of the present embodiment are identical as any one of embodiment 1-4, and so it will not be repeated.

Embodiment 6:

The present embodiment optimizes on the basis of embodiment 5, the Receiver Module use device model for The fiber optic telecommunications module of GR6028.The GR6028 fiber optic telecommunications module realizes optical fiber transceiving, ten thousand mbit ethernet interfaces, optical-fiber network Interface function, optical fiber interface include 1 12 core sending port of MPO, 1 MPO12 core receiving port, 2 road 10G Ethernet, 2 road Gigabit Ethernet.

The other parts of the present embodiment are same as Example 5, and so it will not be repeated.

Embodiment 7:

The present embodiment optimizes on the basis of embodiment any one of 1-6, and the CPU computer is using 2.8GHz's Intel CoreTM i7 processor, chipset are Intel QM87, and inside saving as 8GB DDR3-1600 ECC, VPX interface includes The interface of PCI Express, SRIO × 4, Ethernet interface are 10/100/1000M Base-T interface, onboard solid state hard disk capacity 512GB, operating system are Windows Server 2012.

In addition, CPU computer further includes VGA display interface, 3 USB2.0 interfaces, 2 RS232/422/485 serial ports, 2 A gigabit networking interface, in which: VGA display interface plate in front；In 3 USB2.0 interfaces one backboard, two in front Plate；In 2 RS232/422/485 serial ports one in backboard, another plate in front；It is being carried on the back for one in 2 gigabit networking interfaces Plate, another plate in front.

The other parts of the present embodiment are identical as any one of embodiment 1-6, and so it will not be repeated.

Embodiment 8:

The present embodiment optimizes on the basis of embodiment any one of 1-7, and the fiber optic telecommunications module includes 1 MPO 12 core sending ports, 1 MPO12 core receiving port, 2 road 10G Ethernet, 2 road Gigabit Ethernet realize optical fiber Transmitting-receiving, ten thousand mbit ethernet interfaces, optical network interface function.

The other parts of the present embodiment are identical as any one of embodiment 1-7, and so it will not be repeated.

The above is only the preferred embodiment of the utility model, not does limit in any form to the utility model System, any simple modification made by the above technical examples according to the technical essence of the present invention, equivalent variations, each falls within Within the protection scope of the utility model.

Claims (10)

1. a kind of storage analytical equipment of acquisition in real time, including setting VPX back panel and VPX reinforce cabinet and respectively with VPX back panel CPU computer, Receiver Module, data acquisition module, data memory module, the fiber optic communication mould for connecting and mutually communicating Block, it is characterised in that: the data acquisition module includes a fpga chip and connect respectively with fpga chip one wide Band ADC chipset, a narrowband ADC chipset, five groups of backplane interfaces of SRIO × 4, one group of interface of PCIE × 4, fpga chip are logical It crosses four data memory modules of four groups of backplane interfaces of SRIO × 4 in five groups of backplane interfaces of SRIO × 4 while connection and carries out data Storage, while fpga chip passes through another group of backplane interface of SRIO × 4 in five groups of backplane interfaces of SRIO × 4, the interface of PCIE × 4 It connects CPU computer and carries out data processing.

2. a kind of storage analytical equipment of acquisition in real time according to claim 1, it is characterised in that: the broadband A/D C chip Group is the ADC of the ADC or 4 channel 5GSa/12bit of the ADC or 2 channel 10GSa/12bit of 1 channel 20GSa/12bit；Institute The ADC that narrowband ADC chipset is 2 channel 1GSa/14bit is stated, and the ADC chip of narrowband ADC chipset passes through JESE204 interface It is connect with fpga chip.

3. a kind of storage analytical equipment of acquisition in real time according to claim 2, it is characterised in that: the data acquisition module It further include the DDR3 memory modules of the staggeredly caching for two groups of 64bit being connect with fpga chip.

4. a kind of storage analytical equipment of acquisition in real time according to claim 1, it is characterised in that: the data acquisition module It further include the first clock module being connect with fpga chip, the first power module.

5. a kind of storage analytical equipment of acquisition in real time according to claim 1-4, it is characterised in that: the radio frequency Receiving module includes second power supply module and preposition pre-selection machine low noise unit, frequency conversion list by second power supply module power supply Member, intermediate frequency unit, frequency synthesizer unit, monitoring and communication unit, the preposition pre-selection machine low noise unit access converter unit and change Frequency unit, frequency synthesizer unit are connect with intermediate frequency unit simultaneously, intermediate frequency unit output end connection monitoring and communication unit connection, i.e., external Input signal is output to converter unit, the letter of frequency synthesizer unit and converter unit after the filtering of preposition pre-selection machine low noise unit pre-selection Intermediate-freuqncy signal number repeatedly is generated after mixing, then is exported after monitoring and communication unit monitoring are adjusted.

6. a kind of storage analytical equipment of acquisition in real time according to claim 5, it is characterised in that: the preposition pre-selection machine is low Making an uproar, to put unit include limiter, the first ATT chip, SPDT switch, the first LAN low-noise amplifier, the 2nd LAN low noise amplification Device, the 2nd ATT chip, the 3rd ATT chip, the first SP3T analog switch, the 2nd SP3T analog switch, the 3rd SP3T simulation are opened Pass, the 4th SP3T analog switch, first filter, second filter, third filter, the 4th filter；

The limiter, the first ATT chip, the first SPDT switch are sequentially connected；

One branch of first SPDT switch connects the first SP3T mould by the first LAN low-noise amplifier, the 2nd ATT chip Quasi- switch, the first SP3T analoging switch output end are first divided into two branches with first filter, with second filter again Access the 2nd SP3T analog switch；

Another branch of the SPDT switch connects the 3rd SP3T simulation by the 2nd LAN low-noise amplifier, the 3rd ATT chip Switch, the 3rd SP3T analoging switch output end is first divided into be connect again with third filter, two branches with the 4th filter Enter the 4th SP3T analog switch.

7. a kind of storage analytical equipment of acquisition in real time according to claim 6, it is characterised in that: the frequency synthesizer unit includes Three local oscillation circuits and respectively generation tri- local oscillation signals of LO1, LO2, LO3；The converter unit includes the first frequency mixer, second Frequency mixer, third frequency mixer, the 5th filter, the 6th filter, the second SPDT switch, the first AMP amplifier；

The 2nd SP3T analoging switch output end connects the by inputting the first frequency mixer, the 5th filter of LO1 local oscillation signal The input terminal of two SPDT switches, while the 4th SP3T analoging switch output end is directly connected to the input terminal of the second SPDT switch；

The output end of second SPDT switch passes sequentially through input the second frequency mixer of LO2 local oscillation signal, the 6th filter, the One AMP amplifier, the third frequency mixer connection for inputting LO3 local oscillation signal.

8. a kind of storage analytical equipment of acquisition in real time according to claim 7, it is characterised in that: the intermediate frequency unit includes Sequentially connected 7th filter, the 4th ATT chip, the 2nd AMP amplifier；The 7th filter of output termination of the third frequency mixer Wave device；The signal output end of the 2nd AMP amplifier is connect with monitoring and communication unit.

9. a kind of storage analytical equipment of acquisition in real time according to claim 1-4, it is characterised in that: the data Memory module includes FPGA system master control and the PowerPC master control connecting respectively with FPGA system master control, at least one meets SSD hard disk, front-panel connector, the VPX connector of standard SATA3 agreement；The FPGA system master control by VPX connector with VPX back panel communication connection, while FPGA system master control is connect by front-panel connector with fiber optic telecommunications module.

10. a kind of storage analytical equipment of acquisition in real time according to claim 9, it is characterised in that: the number of the SSD hard disk Amount is not less than 16, and the memory capacity of single SSD hard disk is 2TB.