CN208298052U - A kind of novel slew rate enhancing circuit, low pressure difference linear voltage regulator - Google Patents
A kind of novel slew rate enhancing circuit, low pressure difference linear voltage regulator Download PDFInfo
- Publication number
- CN208298052U CN208298052U CN201820899748.3U CN201820899748U CN208298052U CN 208298052 U CN208298052 U CN 208298052U CN 201820899748 U CN201820899748 U CN 201820899748U CN 208298052 U CN208298052 U CN 208298052U
- Authority
- CN
- China
- Prior art keywords
- oxide
- metal
- semiconductor
- slew rate
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Landscapes
- Electronic Switches (AREA)
Abstract
The utility model is suitable for circuit design, provides novel slew rate enhancing circuit, including several metal-oxide-semiconductors and several capacitors；Several capacitors, for sending control signal to several metal-oxide-semiconductors when detecting that feedback voltage changes；Several metal-oxide-semiconductors, the rising or decline of the output end output voltage for controlling novel slew rate enhancing circuit according to control signal, so that the Slew Rate for the power adjustment pipe being connected with the output end of novel slew rate enhancing circuit, which limits, to be improved.Novel slew rate enhancing circuit provided by the embodiment of the utility model can be limited in the Slew Rate that load jump moment improves power adjustment pipe, improved whole transient response, reduced quiescent current.When load current transient changing or generation switch burr and spike, the variation of output voltage can be quickly detected by feedback voltage, and the grid capacitance to power adjustment pipe and Muller equivalent capacity carry out charge and discharge rapidly, finally substantially improve the transient response of circuit.
Description
Technical field
The utility model belongs to circuit design more particularly to a kind of novel slew rate enhancing circuit, low pressure difference linear voltage regulator.
Background technique
As people's living standard develops, it increasingly be unable to do without all kinds of portable electronic devices in life, such as mobile phone, flat
Plate computer etc., such portable device generally use 5V or 12V power supply, but its chip interior power supply usually in 3V hereinafter, and
Low pressure difference linear voltage regulator LDO (Low Dropout Regulator) is exactly the only selection of such decompression conversion, the phase of LDO
Powered-down road has become highly important one kind circuit in power management chip.LDO is simple with structure, cost is relatively low, chip
The advantages that area is smaller, and quiescent dissipation is lower.
The interlock circuit of traditional LDO such as Fig. 1, since chip mostly uses Digital Analog Hybrid Circuits on the market.When chip is normal
When work, cut-off by the switch meeting frequent progress of Digital Signals, this can cause the load current of LDO to generate frequent spike
Jump, in order to guarantee that LDO output is stablized, therefore it is required that voltage reduction module needs preferable transient response.Transient response directly by
The grid end Slew Rate of bandwidth and power tube MP to LDO is limited, it will usually by the way of capacitor outside piece and raising quiescent current
Improve transient response, this makes the LDO chip area to become larger, power consumption increases.
Utility model content
The technical problem to be solved by the utility model is to provide a kind of novel slew rate enhancing circuit, low pressure difference linearity are steady
Depressor, it is intended to which the prior art improves transient response by the way of the outer capacitor of piece and raising quiescent current, this makes LDO domain
The problem of area becomes larger, power consumption increases.
The utility model is realized in this way a kind of novel slew rate enhancing circuit, including several metal-oxide-semiconductors and several capacitors；
Several capacitors, for detecting the variation of externally input feedback voltage, when detecting feedback voltage hair
When changing, control signal is sent to several metal-oxide-semiconductors；
Several metal-oxide-semiconductors, are connected with the capacitor, for being increased according to the control signal control novel Slew Rate
The rising or decline of the output end output voltage on forceful electric power road, so that being connected with the output end of the novel slew rate enhancing circuit
The Slew Rate of power adjustment pipe limit and improved.
Further, the novel slew rate enhancing circuit includes the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th
Metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, first capacitor and the second capacitor；
The source electrode of first metal-oxide-semiconductor connects input voltage, and the drain electrode of first metal-oxide-semiconductor connects the third metal-oxide-semiconductor
Drain electrode, the grid of first metal-oxide-semiconductor passes through the first capacitor and the second capacitance connection to the 4th metal-oxide-semiconductor according to this
Grid；
The source electrode of second metal-oxide-semiconductor connects the input voltage, the drain electrode connection the described 4th of second metal-oxide-semiconductor
The drain electrode of metal-oxide-semiconductor, the grid of second metal-oxide-semiconductor connect the grid of the 5th metal-oxide-semiconductor, and the grid of second metal-oxide-semiconductor
It is connected with drain electrode；
The grid of the third metal-oxide-semiconductor connects the grid of the 6th metal-oxide-semiconductor, and the source electrode of the third metal-oxide-semiconductor is grounded, and
The drain electrode of the third metal-oxide-semiconductor is connected with grid；
The source electrode of 4th metal-oxide-semiconductor is grounded；The source electrode connection input voltage of 5th metal-oxide-semiconductor, the described 5th
The drain electrode of metal-oxide-semiconductor connects the drain electrode of the 6th metal-oxide-semiconductor；The source electrode of 6th metal-oxide-semiconductor is grounded；The novel Slew Rate enhancing electricity
The output end on road is connected between the drain electrode of the 5th metal-oxide-semiconductor and the drain electrode of the 6th metal-oxide-semiconductor.
Further, first metal-oxide-semiconductor, the second metal-oxide-semiconductor and the 5th metal-oxide-semiconductor are PMOS tube, the third metal-oxide-semiconductor, the
Four metal-oxide-semiconductors and the 6th metal-oxide-semiconductor are NMOS tube.
The utility model embodiment additionally provides a kind of low pressure difference linear voltage regulator, including new described in above-mentioned any one
Type slew rate enhancing circuit and low-dropout linear voltage-regulating circuit；
The grid of the power adjustment pipe of the output end and low-dropout linear voltage-regulating circuit of the novel slew rate enhancing circuit
Pole is connected.
Compared with prior art, beneficial effect is the utility model: novel Slew Rate provided by the embodiment of the utility model
Enhancing circuit includes several metal-oxide-semiconductors and several capacitors, which is detecting when changing of externally input feedback voltage,
Control signal is sent to metal-oxide-semiconductor, metal-oxide-semiconductor controls the output end output voltage of the novel slew rate enhancing circuit according to the control signal
Rising or decline so that the Slew Rate for the power adjustment pipe being connected with the output end of the novel slew rate enhancing circuit limits
To improvement.Novel slew rate enhancing circuit provided by the embodiment of the utility model can improve power adjustment pipe in load jump moment
Slew Rate limitation, not only increase whole transient response, and reduce quiescent current.When load current transient changing or production
When raw switch burr and spike, the variation of output voltage can be quickly detected by feedback voltage, and give power adjustment pipe rapidly
Grid capacitance and Muller equivalent capacity carry out charge and discharge, finally substantially improve the transient response of circuit.
Detailed description of the invention
Fig. 1 is the circuit diagram for the low pressure difference linear voltage regulator that the prior art provides；
Fig. 2 is the structural schematic diagram of novel slew rate enhancing circuit provided by the embodiment of the utility model；
Fig. 3 is the structural schematic diagram of low pressure difference linear voltage regulator provided by the embodiment of the utility model；
Fig. 4 is provided by the embodiment of the utility model in input voltage VDD=5V, and low pressure difference linear voltage regulator loads wink
State emulates schematic diagram；
Fig. 5 is provided by the embodiment of the utility model in input voltage VDD=3.5V, low pressure difference linear voltage regulator load
Transient schematic diagram.
Specific embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain
The utility model is not used to limit the utility model.
LDO considers its transient response by its load current, when load current changes from big to small, power adjustment pipe
Grid can not quick response its voltage change, output voltage VDDL will form punching, restores normal value by the regular hour；
Likewise, when load current changes from small to large, the grid voltage of power adjustment pipe can not quick response its voltage change, bear
Carrying electric current can only largely be provided by load capacitance, this causes output voltage VDDL to will form undershoot, until working as power adjustment
The grid voltage of pipe drops to when can provide large load current, and side restores to work normally.
Based on above-mentioned cause, the utility model embodiment provides a kind of novel slew rate enhancing circuit, is mainly used for solving
In the case where lower power consumption when integrated circuit bandwidth deficiency, Slew Rate restricted problem existing for the grid of power adjustment pipe.Power
Tube grid Slew Rate restricted problem is not only to be caused by grid capacitance, and there are also the Muller equivalent capacitys of compensating electric capacity to Slew Rate
Limitation.Novel slew rate enhancing circuit provided by the embodiment of the utility model can improve power adjustment pipe in load jump moment
Slew Rate limitation, not only increases whole transient response, and reduce quiescent current.When load current transient changing or generation
When switching burr and spike, the variation of output voltage can be quickly detected by feedback voltage, and rapidly to power adjustment pipe
Grid capacitance and Muller equivalent capacity carry out charge and discharge, finally substantially improve the transient response of circuit.
The utility model embodiment provides a kind of novel slew rate enhancing circuit, if the novel slew rate enhancing circuit includes
Dry metal-oxide-semiconductor and several capacitors；Several capacitors, it is described when detecting for detecting the variation of externally input feedback voltage
When feedback voltage changes, control signal is sent to several metal-oxide-semiconductors；Several metal-oxide-semiconductors, are connected with the capacitor
Connect, for according to it is described control signal control the novel slew rate enhancing circuit output end output voltage rising or under
Drop, so that the Slew Rate for the power adjustment pipe being connected with the output end of the novel slew rate enhancing circuit, which limits, to be improved.
Specifically, as shown in Fig. 2, novel slew rate enhancing circuit includes the first metal-oxide-semiconductor M20, the second metal-oxide-semiconductor M22, third
Metal-oxide-semiconductor M21, the 4th metal-oxide-semiconductor M23, the 5th metal-oxide-semiconductor M24, the 6th metal-oxide-semiconductor M25, first capacitor C1 and the second capacitor C2；
The source electrode of first metal-oxide-semiconductor M20 connects input voltage VDD, and the drain electrode of the first metal-oxide-semiconductor M20 connects third metal-oxide-semiconductor M21
Drain electrode, the grid of the first metal-oxide-semiconductor M20 passes through first capacitor C1 according to this and the second capacitor C2 is connected to the grid of the 4th metal-oxide-semiconductor M23
Pole；
The source electrode of second metal-oxide-semiconductor M22 connects input voltage VDD, and the drain electrode of the second metal-oxide-semiconductor M22 connects the 4th metal-oxide-semiconductor M23
Drain electrode, the grid of the second metal-oxide-semiconductor M22 connects the grid of the 5th metal-oxide-semiconductor M24, and the grid of the second metal-oxide-semiconductor M22 and the phase that drains
Connection；
The grid of third metal-oxide-semiconductor M21 connects the grid of the 6th metal-oxide-semiconductor M25, and the source electrode of third metal-oxide-semiconductor M21 is grounded, and the
The drain electrode of three metal-oxide-semiconductor M21 is connected with grid；
The source electrode of 4th metal-oxide-semiconductor M23 is grounded；The source electrode of 5th metal-oxide-semiconductor M24 connects input voltage VDD, the 5th metal-oxide-semiconductor M24
Drain electrode connection the 6th metal-oxide-semiconductor M25 drain electrode；The source electrode of 6th metal-oxide-semiconductor M25 is grounded；The novel slew rate enhancing circuit it is defeated
Outlet is connected between the drain electrode of the 5th metal-oxide-semiconductor M24 and the drain electrode of the 6th metal-oxide-semiconductor M25.
Specifically, M20, M22 and M24 are PMOS tube, and M21, M23 and M25 are NMOS tube.In above-mentioned statement, the source of M20
End is connected with the source of M22 and M24 and is connected with VDD, and drain terminal is connected with the drain terminal of M21 and grid end and the grid end phase with M25
Even, grid end is connected with one end of capacitor C1.The source of M23 is connected with the source of M21 and M25 and is connected with ground wire, drain terminal
It is connected with the grid end of M22 and drain terminal and is connected with the grid end of M24, grid end is connected with one end of capacitor C2.Capacitor C1's is another
End is connected with the other end of capacitor C2 and is connected with externally input feedback voltage Vfb.The drain terminal of M24 is connected with the drain terminal of M25
And it is connected with the grid end of external power adjustment pipe MP.
Fig. 3 shows novel slew rate enhancing circuit provided by the embodiment of the utility model applied to portable device without piece
The enhanced low pressure difference linear voltage regulator of low-power consumption transient state of outer capacitor, the circuit of the low pressure difference linear voltage regulator include error amplification
Device, buffer stage circuit, sampling resistor, power adjustment pipe, novel slew rate enhancing circuit and Muller compensation circuit.Reference voltage Vref
Given, the value 1.2V for external bandgap voltage reference.Metal-oxide-semiconductor M1~M9 form LDO error amplifier, by feedback voltage with
The difference of reference voltage amplifies processing.Metal-oxide-semiconductor M10~M12 and resistance R3 constitute auto bias circuit, are error amplifier
Bias voltage needed for working normally is provided.The buffer stage of metal-oxide-semiconductor M13~M19 built-up circuit, in order to improve circuit Slew Rate limit
System, and output resistance is reduced, improve the driving capability to next stage.R1, R2 are the sampling resistor of circuit, monitor output voltage
VDDL simultaneously feeds back result, this result is amplified by error amplifier, forms the feedback control loop of circuit.MP is power
Adjustment pipe.M20~M25, C1 and C2 constitute novel slew rate enhancing circuit, for improving without the low-power consumption LDO of capacitor outside piece
Transient response.Cm1 and Cm2 is Muller compensation circuit, can improve LDO frequency loop characteristic.
In novel slew rate enhancing circuit, Vfb indicates the feedback voltage of sampling resistor, ISRIndicate connection power adjustment pipe MP
Grid, provide Slew Rate strengthening electric current for power adjustment pipe MP.The detection capacitor of C1, C2 indication circuit.
Specifically, novel Slew Rate provided by the embodiment of the utility model enhances circuit operation principle are as follows:
The breadth length ratio of M21 is doubled on the basis of M20 and M21 matched, so that existing between metal-oxide-semiconductor M20 and M21
Imbalance.Therefore when feedback voltage Vfb does not reduce, the voltage value of A point is low potential, so that metal-oxide-semiconductor M25 is held off shape
State.When load current increase suddenly or generate rush when, feedback voltage Vfb reduces suddenly, according to pressure difference of the load on capacitor
The principle that cannot be mutated, the detection capacitor C1 of circuit can quickly detect the reduction of feedback voltage Vfb, then cause metal-oxide-semiconductor
The grid voltage of M20 reduces, and voltage at A point is caused to increase, to open metal-oxide-semiconductor M25 and decline its drain terminal voltage, finally makes
Its high current for generating moment carries out the electric discharge of short time to the gate capacitance and Muller equivalent capacity of power adjustment pipe MP.
Similarly, the breadth length ratio of M22 is doubled on the basis of M22 and M23 matched so that metal-oxide-semiconductor M22 and M23 it
Between exist imbalance.Therefore when feedback voltage Vfb does not increase, the voltage value of B point is high potential, so that metal-oxide-semiconductor M24 keeps closing
Disconnected state.When load current reduces suddenly or generates undershoot, feedback voltage Vfb is flown up, according to load on capacitor
The principle that pressure difference cannot be mutated, the detection capacitor C2 of circuit can quickly detect the rising of feedback voltage Vfb, then cause
The grid voltage of metal-oxide-semiconductor M23 increases, and voltage at B point is caused to decline, thus open metal-oxide-semiconductor M24 and increase its drain terminal voltage,
It is finally set to generate the charging that the high current of moment carries out the short time to the gate capacitance and Muller equivalent capacity of MP.
When the load current of entire circuit is stablized, metal-oxide-semiconductor M24, M25 are in an off state, and capacitor C1, C2 are set
Lesser capacitance, LDO do not influence its frequency characteristic and stability when working normally.
The utility model embodiment uses novel slew rate enhancing circuit, compared to by adjusting error amplifier in LDO
Tail current improves transient response with the GBW for improving LDO loop, and slew rate enhancing circuit provided by the embodiment of the utility model can make
Its grid end for exporting electric current access power adjustment pipe, therefore LDO entirety loop does not need biggish GBW.The utility model is implemented
Example provide slew rate enhancing circuit can use lesser quiescent current, make LDO circuit maintained under preferable transient response compared with
Low-power consumption, therefore slew rate enhancing circuit provided by the embodiment of the utility model can be obviously improved LDO system's transient response energy
Power.
The emulation of low pressure difference linear voltage regulator LDO provided by the embodiment of the utility model different process angle and at a temperature of into
Row, the temperature environment of emulation are ht=85 DEG C, lt=-40 DEG C；Process corner environment is tt, ff, ss, fs, sf.
Quiescent current simulation result is as shown in table 1, therefore the minimum 9.956uA of quiescent current.
Table 1LDO quiescent current simulation result
Transient result such as Fig. 4 and Fig. 5, setting load current are jumped between 6uA to 6mA, rise and fall
Time is 10ns, and input voltage is respectively 5V and 3.5V.It can be seen that, output voltage VDDL is relatively stable, substantially from emulation
Ringing effect is eliminated, and ensure that shorter upper punching and undershoot recovery time.As VDD=5V, upper punching is 84mV, when recovery
Between be 14.4us；Undershoot is 63mV, recovery time 15.3us.As VDD=3.5V, upper punching is 214mV, and recovery time is
14.9us；Undershoot is 200mV, recovery time 11.6us.
Therefore the utility model has preferable transient response in the case where guaranteeing without capacitor outside piece and lower quiescent current.
Novel slew rate enhancing circuit provided by the embodiment of the utility model can be applied in portable device, such as intelligent hand
Machine, laptop, tablet computer etc..
The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this
Made any modifications, equivalent replacements, and improvements etc., should be included in the utility model within the spirit and principle of utility model
Protection scope within.
Claims (4)
1. a kind of novel slew rate enhancing circuit, which is characterized in that the novel slew rate enhancing circuit includes several metal-oxide-semiconductors and several
Capacitor；
Several capacitors, for detecting the variation of externally input feedback voltage, when detecting that the feedback voltage becomes
When change, control signal is sent to several metal-oxide-semiconductors；
Several metal-oxide-semiconductors, are connected with the capacitor, for enhancing electricity according to the control signal control novel Slew Rate
The rising or decline of the output end output voltage on road, so that the function being connected with the output end of the novel slew rate enhancing circuit
The Slew Rate of rate adjustment pipe, which limits, to be improved.
2. novel slew rate enhancing circuit as described in claim 1, which is characterized in that the novel slew rate enhancing circuit includes the
One metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, first capacitor and the second capacitor；
The source electrode of first metal-oxide-semiconductor connects input voltage, and the drain electrode of first metal-oxide-semiconductor connects the leakage of the third metal-oxide-semiconductor
Pole, the grid of first metal-oxide-semiconductor pass through the grid of the first capacitor and the second capacitance connection to the 4th metal-oxide-semiconductor according to this
Pole；
The source electrode of second metal-oxide-semiconductor connects the input voltage, and the drain electrode of second metal-oxide-semiconductor connects the 4th metal-oxide-semiconductor
Drain electrode, the grid of second metal-oxide-semiconductor connects the grid of the 5th metal-oxide-semiconductor, and the grid of second metal-oxide-semiconductor and drain electrode
It is connected；
The grid of the third metal-oxide-semiconductor connects the grid of the 6th metal-oxide-semiconductor, and the source electrode of the third metal-oxide-semiconductor is grounded, and described
The drain electrode of third metal-oxide-semiconductor is connected with grid；
The source electrode of 4th metal-oxide-semiconductor is grounded；The source electrode of 5th metal-oxide-semiconductor connects the input voltage, the 5th metal-oxide-semiconductor
Drain electrode connect the drain electrode of the 6th metal-oxide-semiconductor；The source electrode of 6th metal-oxide-semiconductor is grounded；The novel slew rate enhancing circuit
Output end is connected between the drain electrode of the 5th metal-oxide-semiconductor and the drain electrode of the 6th metal-oxide-semiconductor.
3. novel slew rate enhancing circuit as claimed in claim 2, which is characterized in that first metal-oxide-semiconductor, the second metal-oxide-semiconductor and
5th metal-oxide-semiconductor is PMOS tube, and the third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor are NMOS tube.
4. a kind of low pressure difference linear voltage regulator, which is characterized in that including novel Slew Rate described in claims 1 to 3 any one
Enhance circuit and low-dropout linear voltage-regulating circuit；
The grid phase of the power adjustment pipe of the output end and low-dropout linear voltage-regulating circuit of the novel slew rate enhancing circuit
Connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820899748.3U CN208298052U (en) | 2018-06-11 | 2018-06-11 | A kind of novel slew rate enhancing circuit, low pressure difference linear voltage regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820899748.3U CN208298052U (en) | 2018-06-11 | 2018-06-11 | A kind of novel slew rate enhancing circuit, low pressure difference linear voltage regulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208298052U true CN208298052U (en) | 2018-12-28 |
Family
ID=64701933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820899748.3U Withdrawn - After Issue CN208298052U (en) | 2018-06-11 | 2018-06-11 | A kind of novel slew rate enhancing circuit, low pressure difference linear voltage regulator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208298052U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108508953A (en) * | 2018-06-11 | 2018-09-07 | 深圳大学 | Novel slew rate enhancing circuit, low pressure difference linear voltage regulator |
-
2018
- 2018-06-11 CN CN201820899748.3U patent/CN208298052U/en not_active Withdrawn - After Issue
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108508953A (en) * | 2018-06-11 | 2018-09-07 | 深圳大学 | Novel slew rate enhancing circuit, low pressure difference linear voltage regulator |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1848019B (en) | Constant voltage power supply circuit and method of testing the same | |
| CN102707757B (en) | Dynamic discharge circuit and LDO integrated with same | |
| CN108508953A (en) | Novel slew rate enhancing circuit, low pressure difference linear voltage regulator | |
| CN105138062B (en) | Improve the system of low pressure difference linear voltage regulator load regulation | |
| CN110632972B (en) | Method and circuit for suppressing output voltage overshoot of LDO (low dropout regulator) | |
| CN103529890B (en) | A kind of soft starting device and method | |
| CN106292824B (en) | Low-dropout regulator circuit | |
| CN101097456B (en) | Voltage regulator | |
| CN105988495A (en) | LDO (Low Drop-out voltage regulator) overshooting protection circuit | |
| CN108241396A (en) | A kind of low pressure difference linear voltage regulator for improving transient response speed | |
| CN106227282A (en) | There is multi-mode and control the high-reliability low-pressure difference linear constant voltage regulator circuit of function | |
| CN101943925A (en) | Discharge circuit for voltage regulators | |
| CN111638744A (en) | Current frequency conversion circuit | |
| CN109213255A (en) | A kind of starting overshoot suppression circuit for LDO | |
| CN103792982A (en) | Low dropout linear regulator without external capacitor | |
| CN110858081A (en) | Simple and effective transient enhancement type LDO circuit | |
| CN103529891A (en) | Soft start device and method | |
| CN208298052U (en) | A kind of novel slew rate enhancing circuit, low pressure difference linear voltage regulator | |
| CN102830743B (en) | Under-voltage locking circuit | |
| CN106774599A (en) | A kind of voltage modulator circuit of high PSRR | |
| CN106249795A (en) | A kind of LDO circuit of output of floating | |
| CN101763134A (en) | Parallel voltage stabilizing circuit | |
| CN114185384B (en) | Transient enhancement circuit for low-power LDO (low dropout regulator) | |
| CN114756078B (en) | High-precision voltage-stabilizing power supply circuit of integrated circuit chip | |
| CN203745940U (en) | Low dropout linear voltage regulator without external capacitor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20181228 Effective date of abandoning: 20200324 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20181228 Effective date of abandoning: 20200324 |