CN208240684U - A kind of semiconductor devices - Google Patents
A kind of semiconductor devices Download PDFInfo
- Publication number
- CN208240684U CN208240684U CN201820797777.9U CN201820797777U CN208240684U CN 208240684 U CN208240684 U CN 208240684U CN 201820797777 U CN201820797777 U CN 201820797777U CN 208240684 U CN208240684 U CN 208240684U
- Authority
- CN
- China
- Prior art keywords
- drift region
- semiconductor devices
- region
- area
- body area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The utility model provides a kind of semiconductor devices, the semiconductor devices is transverse diffusion metal oxide semiconductor device, it specifically includes that base, in the base and with the first doping type drift region, in the base and with the second doping type body area, the drift region and the body area have scheduled positional relationship, so that the drift region hinders the body area to the horizontal proliferation in the drift region direction.Therefore, drift region had not only been used as resistance to pressure area, but also as the diffusion inhibition zone for hindering the horizontal proliferation of body area, can effectively reduce the channel length of the semiconductor devices, realized short channel semiconductor device.
Description
Technical field
The utility model relates to technical field of semiconductors, more particularly, to a kind of semiconductor devices.
Background technique
In existing transverse diffusion metal oxide semiconductor device 100 as shown in Figure 1, it generally comprises P type substrate
PSUB, high-pressure N-shaped well region HVNW, the area PXing Ti Pbody and N-type drift region N-drift in P type substrate PSUB are respectively formed
In high-pressure N-shaped well region HVNW, source area N+ and drain region N+ are respectively formed in the area PXing Ti Pbody and N-type drift region N-
In drift, body contact zone P+ is also formed in body area Pbody and is in contact with source area N+, and in the table of semiconductor devices 100
Face is additionally provided with the gate dielectric layer adjacent with source area (unmarked in figure) and the thickness between gate dielectric layer and drain region
Oxygen layer Oxide, grid conductor poly cover the gate dielectric layer and extend on heavy oxygen layer Oxide.
The existing method for forming semiconductor devices 100 is usually first to serve as a contrast substrate PSUB and well region HVNW structure in semiconductor
At substrate surface once form gate dielectric layer and grid conductor Poly, then recycle grid conductor Ploy do autoregistration, and
Body area Pbody is formed in well region HVNW using horizontal proliferation, then re-forms drift region N-drift.This manufacturing method shape
At semiconductor devices 100 since the horizontal proliferation of body area Pbody is than more serious so that channel hand over length so that low pressure applications
Under, channel resistance is larger, and the optimization of the conducting resistance and resistance to pressure of device is limited.
Summary of the invention
In view of this, the present invention provides a kind of semiconductor devices of lateral diffused metal oxide, described in reducing
The channel of semiconductor devices, while optimizing conducting resistance and pressure-resistant performance.
Semiconductor device, the semiconductor devices are kind of a transverse diffusion metal oxide semiconductor device, comprising:
Base,
In the base and with the first doping type drift region,
In the base and the body area with the second doping type, the drift region have scheduled with the body area
Positional relationship, so that the drift region hinders the body area to the horizontal proliferation in the drift region direction.
Preferably, the semiconductor devices further include:
Gate dielectric layer is formed on the first surface of the base and grid conductor, the part of the gate dielectric layer are covered
The surface in the body area is covered, another part is covered on the surface of the base.
Preferably, the semiconductor devices further include: in the body area and with the first doping type source electrode
Area, the source area are adjacent with the gate dielectric layer.
Preferably, the semiconductor devices, further includes:
In the drift region and with the first doping type drain region,
And it is located at the substrate surface, and the Withstand voltage layer between the gate dielectric layer and the drain region, it is described
Withstand voltage layer is at least partly covered on the drift region.
Preferably, the body area is in contact with the drift region or the body area is at least partially disposed at the drift region
In.
Preferably, the drift region is prolonged this side by the drain region of the transverse diffusion metal oxide semiconductor device
Extend to this side of the source region of the transverse diffusion metal oxide semiconductor device.
Preferably, the body area is located at this side of the source region of the transverse diffusion metal oxide semiconductor device
In drift region.
Preferably, the base includes semiconductor substrate and is located in the semiconductor substrate and has the first doping type
Well region,
The body takes to be respectively positioned in the well region with drift region.
Preferably, the semiconductor devices further includes the field conductor being at least partially disposed on the Withstand voltage layer, the field
Conductor and grid conductor space isolation.
Preferably, second doping type is p-type, and the dopant in the body area is the dopant containing indium.
Therefore the semiconductor devices according to lateral diffused metal oxide provided by the utility model, drift region was both
As resistance to pressure area, and as the diffusion inhibition zone for hindering the horizontal proliferation of body area, the ditch of the semiconductor devices can be further decreased
Road length realizes short channel semiconductor device.
Detailed description of the invention
By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model
, feature and advantage will be apparent from, in the accompanying drawings:
Fig. 1 is the structural schematic diagram of existing transverse diffusion metal oxide semiconductor device；
Fig. 2 a-2h is in the manufacturing process according to transverse diffusion metal oxide semiconductor device provided by the utility model
The structural section schematic diagram that each processing step is formed.
Specific embodiment
Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical component part uses
Similar appended drawing reference indicates.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to not
Certain well known parts are shown.For brevity, the structure obtained after several steps can be described in a width figure.?
Described hereafter is many specific details of the utility model, such as the structure of each component part, material, size, processing
Technique and technology, to be more clearly understood that the utility model.But it just as the skilled person will understand, can
Not realize the utility model according to these specific details.
Fig. 2 a-2h be according to transverse diffusion metal oxide semiconductor device provided by the utility model during it is each
The structural section schematic diagram that processing step is formed.
Step 1: as shown in Figure 2 a, in semiconductor substrate, inject N type dopant in the substrate PSUB that adulterates such as p-type, with
The high voltage bearing well region DNWELL of N-type is formed in the substrate PSUB of p-type doping.
In addition, after forming well region DNWELL, it can also be in the substrate surface shape being made of substrate PSUB and well region DNWELL
At field oxide (in Fig. 2 a unmarked), the field oxide is formed for example, by using LOCOS (local oxidation of silicon) technique.
Step 2: as shown in Figure 2 b, N type dopant is injected in the base being made of substrate PSUB and well region DNWELL, with
Formed N-type drift region N-drift, wherein drift region N-drift by the transverse diffusion metal oxide semiconductor device leakage
One side in polar region domain extends to the side of the source region of the transverse diffusion metal oxide semiconductor device.Drift region N-
Resistance to pressure area of the drift mainly as the transverse diffusion metal oxide semiconductor device.
Drift region N-drift can preferably extend to the source area of the transverse diffusion metal oxide semiconductor device
The side in domain, i.e. a part of drift region N-drift are located at the source area of the transverse diffusion metal oxide semiconductor device
In domain.Wherein, the drain region refers to that the region where drain region, drain region are located in the drain region, the source electrode
Region refers to the region where source area, and source area is located in the source region.Drift region N-drift is located at the base
In well region DNWELL, and the drift region N-drift can cover the whole surface of well region DNWELL, therefore, can be by passing through
After the N type dopant that first mask injects the first concentration forms well region DNWELL, without removing first mask immediately, but
Continue to form drift region N-drift by the N type dopant for injecting the second concentration through first mask, such well region DNWELL and
Drift region N-drift can share the first mask, reduce by one of photoetching process, reduce the preparation cost of semiconductor devices.
Step 3: Withstand voltage layer is formed on the first surface of the base, the Withstand voltage layer is at least partially disposed at drift region
On N-drift, and the Withstand voltage layer is also located at gate dielectric layer and the leakage of the transverse diffusion metal oxide semiconductor device
Between polar region.
As shown in Figure 2 c, the Withstand voltage layer is oxide layer Oxide in this embodiment, and the thickness of oxide layer Oxide is usually high
In the thickness of the gate dielectric layer of the transverse diffusion metal oxide semiconductor device, and its shape can be beak-like.?
In other embodiments, the Withstand voltage layer may be other media layer, can also be shallow groove isolation layer.
Step 4: the area PXing Ti Pbody is formed in the well region DNWELL of the base, body area Pbody is located at the transverse direction
In the source region of diffused metal oxide emiconductor device.Such as p-type body can be formed by dopant of the injection containing indium
Area Pbody, to reduce the horizontal proliferation of the area PXing Ti Pbody.Since the drift region N-drift of formation is by the horizontal proliferation gold
Belong to a side of the drain region of oxide semiconductor element to the source area of the transverse diffusion metal oxide semiconductor device
The side in domain extends, so that horizontal proliferation of the body area Pbody to the drift region direction N-drift can be by drift region N-
Drift hinders or inhibits, and the p type impurity in body area Pbody can floated to the distance of the horizontal proliferation in the drift region direction N-drift
It moves under the inhibition of area N-drift and effectively reduces, that is, be formed by the lateral dimension of body area Pbody substantially and described in formation
The opening size of used mask is identical when body area Pbody.When injecting p-type dopant forms body area Pbody, tune can be passed through
The doping concentration of P-type dopant is saved, to adjust the threshold voltage of the transverse diffusion metal oxide semiconductor device.
As shown in Figure 2 d, in the present embodiment, since drift region N-drift has extended directly into the horizontal proliferation metal
The side of the source region of oxide semiconductor element, therefore directly can partly be led positioned at the lateral diffused metal oxide
Injecting p-type dopant in the drift region N-drift of this side of the source region of body device, so that the injection zone is by N-type transoid
At p-type, to be located in the N-drift of drift region so body area Pbody close to described as the area PXing Ti Pbody, Ji Ti area Pbody
The side of gate dielectric layer is surrounded by drift region N-drift, by the doping concentration appropriate for adjusting drift region N-drift, just
It can hinder the horizontal proliferation of body area Pbody.In other embodiments, body area Pbody can be only partially located within drift region N-
In drift, or only it is in contact with drift region N-drift.Spacing between drift region N-drift and body area Pbody is bigger, just
The doping concentration for needing to control drift region N-drift is bigger, to hinder body area Pbody to the transverse direction in the drift region direction N-drift
Diffusion.
Step 5: after forming body area Pbody, gate dielectric layer is formed on the first surface of the base and in the grid
Grid conductor is formed on dielectric layer, wherein a part of the gate dielectric layer is located at a part top of body area Pbody, another
Part is positioned at a part top of the well region DNWELL and/or drift region N-drift, and the side of the gate dielectric layer is with after
The continuous source area formed is adjacent, and the other side is adjacent with the Withstand voltage layer.The grid that are at least partially disposed at of the grid conductor are situated between
On matter layer, optionally, the grid conductor can also be by extending on the Withstand voltage layer on the gate dielectric layer.
The specific step of the gate dielectric layer and grid conductor is formed as shown in Fig. 2 e-2g, first in the base
First surface forms layer of oxide layer Gox, then deposits one layer of conductor layer, such as Poly layers of polysilicon on oxide layer Gox again.
Then described polysilicon Poly layers are etched, etching can stop at gate oxide Gox and (retain in the base except area of grid
Outer gate oxide Gox) can also stop at the base first surface (remove the base in addition to area of grid
Gate oxide Gox), in the present embodiment, etch stop is in the first surface of the base, as shown in Figure 2 g, remaining after etching
Poly layer be used as the grid conductor, this portion of oxide layer Gox below grid conductor is as gate dielectric layer.
When etching the conductor layer and forming the grid conductor, is also formed and be located at the Withstand voltage layer and enter the court conductor, wherein
The grid conductor is isolated with field conductor space.I.e. when etching the conductor layer, so that a part of the conductor layer after etching
As the grid conductor, another part is as the field conductor.Since the present embodiment is when etching the conductor layer, etching stops
Terminate in the first surface of the base, then it, can also be in the base before being subsequently implanted into and to form source area and drain region
Regrow one layer of thin oxide layer on surface.
In addition, after forming the gate dielectric layer and grid conductor, it can also be further in the surface district of the body area Pbody
N type dopant is injected in domain, to form N-type lightly doped drain NLDD (in figure unmarked), and in the side wall of the grid conductor
It is formed side wall (unmarked in figure), the side wall can be oxide, such as SiO2
Step 6: N type dopant is injected in drift region N-drift and body area Pbody respectively as shown in fig. 2h, with respectively
Formed N-type drain region N+ and source area N+, and in body area Pbody injecting p-type dopant to form p-type body contact zone P
+, body contact zone P+ is adjacent with source area N+.
After forming source-drain electrode area, it is also necessary to form each electricity of the transverse diffusion metal oxide semiconductor device
Pole, the source electrode S being such as electrically connected with source area N+, the drain electrode D being electrically connected with drain region N+, the grid being electrically connected with grid conductor
Pole conductor G, and the underlayer electrode B being electrically connected with body contact zone P+.In Fig. 2 and it is not drawn into the specific structure of each electrode,
Only illustrated by connection terminal.In addition, further including when forming each electrode if being provided with the field conductor on the Withstand voltage layer
Form the field plate electrode that is electrically connected with the field conductor, the field plate electrode and the gate electrode connect different current potentials, and with institute
It states source electrode and connects identical current potential.
Other implementations of manufacturing method according to transverse diffusion metal oxide semiconductor device provided by the utility model
In example, not necessarily comprising all steps in above-mentioned each step, being also not limited to only includes above steps, and each above-mentioned
The sequencing of each step is not limited to above-mentioned sequence in other embodiments and can also convert and the doping class in each area
Type is also not limited to above-mentioned form.In addition, according to transverse diffusion metal oxide semiconductor device provided by the utility model
The doping type that drift region described in the embodiment of manufacturing method, well region, lightly doped drain are is the first doping type, and
Being formed by mixing the dopant of the first doping type, the substrate, body area and body contact zone are the second doping type,
And it is formed by mixing the dopant of the second doping type.Wherein, first doping type be one of p-type and N-type,
Second doping type is the another kind in p-type and N-type.
In addition, the utility model additionally provides the semiconductor device formed according to the manufacturing method provided by the utility model
The structural schematic diagram of part, the semiconductor devices can be as shown in fig. 2h.The transverse diffusion metal oxide semiconductor device,
It specifically includes that base, in the base and the drift region with the first doping type, is located in the base and has the
The body area of two doping types, the drift region and the body area have scheduled positional relationship, so that the drift region hinders institute
Horizontal proliferation of the area Shu Ti to the drift region direction.And the transverse diffusion metal oxide semiconductor device can also be further
It should include: to form gate dielectric layer and grid conductor, the part of the gate dielectric layer on the first surface of the base to cover
The surface in the body area is covered, another part is covered on the surface of the base, is located in the body area and has the first doping
The source area of type, the source area is adjacent with the gate dielectric layer, is located in the drift region and has the first doping type
Drain region, and be located at the substrate surface, and the Withstand voltage layer between the gate dielectric layer and the drain region is described
Withstand voltage layer is at least partly covered on the drift region, and the field conductor being at least partially disposed on the Withstand voltage layer, the field is led
Body and grid conductor space isolation.It further include the body contact zone for being located in the body area and having the second doping type.Its
In, the body area is in contact with the drift region or the body area is at least partially disposed in the drift region.Specifically, described
Drift region extends to the horizontal proliferation gold by this side of the drain region of the transverse diffusion metal oxide semiconductor device
Belong to this side of source region of oxide semiconductor element, the body area is located at the lateral diffusion metal oxide semiconductor device
In the drift region of this side of the source region of part.
In addition, the base include semiconductor substrate and in the semiconductor substrate and have the first doping type
Well region, the body takes to be respectively positioned in the well region with drift region.According to the semiconductor devices provided by the utility model
In one embodiment, first doping type is N-type, and second doping type is p-type, then the dopant in the body area is
Dopant containing indium, in other embodiments, second doping type may be N-type, then the first doping type is p-type.
Therefore according to transverse diffusion metal oxide semiconductor device provided by the utility model, since body area exists
Gate dielectric layer and grid conductor have just been formed before being formed, thus be conducive to reduce the channel length of the semiconductor devices,
Conducting resistance is reduced, and so that drift region had not only been used as resistance to pressure area, but also as the diffusion inhibition zone for hindering the horizontal proliferation of body area, it can be into one
Step reduces the channel length of the semiconductor devices, realizes short channel semiconductor device.
It is as described above according to the embodiments of the present invention, these embodiments details all there is no detailed descriptionthe,
Also not limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This
These embodiments are chosen and specifically described to specification, be in order to preferably explain the principles of the present invention and practical application, from
And skilled artisan is enable to make well using the utility model and modification on the basis of the utility model
With.The utility model is limited only by the claims and their full scope and equivalents.
Claims (10)
1. a kind of semiconductor devices, the semiconductor devices is transverse diffusion metal oxide semiconductor device, which is characterized in that
Include:
Base,
In the base and with the first doping type drift region,
In the base and the body area with the second doping type, the drift region and the body area have scheduled position
Relationship, so that the drift region hinders the body area to the horizontal proliferation in the drift region direction.
2. semiconductor devices according to claim 1, further includes:
Gate dielectric layer is formed on the first surface of the base and grid conductor, the gate dielectric layer are partially covered on institute
The surface in the area Shu Ti, another part are covered on the surface of the base.
3. semiconductor devices according to claim 2, further includes: in the body area and with the first doping type
Source area, the source area are adjacent with the gate dielectric layer.
4. semiconductor devices according to claim 2, further includes:
In the drift region and with the first doping type drain region,
And it is located at the substrate surface, and the Withstand voltage layer between the gate dielectric layer and the drain region, the pressure resistance
Layer is at least partly covered on the drift region.
5. semiconductor devices according to claim 1, which is characterized in that the body area is in contact with the drift region or institute
The area Shu Ti is at least partially disposed in the drift region.
6. semiconductor devices according to claim 5, which is characterized in that the drift region is by the horizontal proliferation metal oxygen
This side of the drain region of compound semiconductor devices extends to the source area of the transverse diffusion metal oxide semiconductor device
This side of domain.
7. semiconductor devices according to claim 6, which is characterized in that
The body area is located in the drift region of this side of the source region of the transverse diffusion metal oxide semiconductor device.
8. semiconductor devices according to claim 1, which is characterized in that the base include semiconductor substrate and be located at institute
The well region of the first doping type is stated in semiconductor substrate and has,
The body area and drift region are respectively positioned in the well region.
9. semiconductor devices according to claim 4, which is characterized in that further include being at least partially disposed on the Withstand voltage layer
Field conductor, the field conductor and the grid conductor space isolation.
10. semiconductor devices according to claim 1, which is characterized in that second doping type is p-type, the body
Dopant in area is the dopant containing indium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820797777.9U CN208240684U (en) | 2018-05-25 | 2018-05-25 | A kind of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820797777.9U CN208240684U (en) | 2018-05-25 | 2018-05-25 | A kind of semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208240684U true CN208240684U (en) | 2018-12-14 |
Family
ID=64575034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820797777.9U Active CN208240684U (en) | 2018-05-25 | 2018-05-25 | A kind of semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208240684U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108682691A (en) * | 2018-05-25 | 2018-10-19 | 矽力杰半导体技术(杭州)有限公司 | The manufacturing method and semiconductor devices of transverse diffusion metal oxide semiconductor device |
-
2018
- 2018-05-25 CN CN201820797777.9U patent/CN208240684U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108682691A (en) * | 2018-05-25 | 2018-10-19 | 矽力杰半导体技术(杭州)有限公司 | The manufacturing method and semiconductor devices of transverse diffusion metal oxide semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9853146B2 (en) | Lateral double diffused MOS transistors | |
| US6825531B1 (en) | Lateral DMOS transistor with a self-aligned drain region | |
| TWI722390B (en) | Lateral diffusion metal oxide semiconductor device and manufacturing method thereof | |
| US10861965B2 (en) | Power MOSFET with an integrated pseudo-Schottky diode in source contact trench | |
| CN111048587B (en) | Groove gate depletion type VDMOS device and manufacturing method thereof | |
| TWI695512B (en) | Lateral diffusion metal oxide semiconductor device and its manufacturing method | |
| CN105070759A (en) | Nldmos device and manufacturing method thereof | |
| CN104377244A (en) | Device structure lowering LDMOS on resistance | |
| CN111725070A (en) | Manufacturing method of semiconductor device and semiconductor device | |
| CN106024905A (en) | Low on-resistance lateral double-diffusion metal oxide semiconductor device | |
| US9178054B2 (en) | Planar vertical DMOS transistor with reduced gate charge | |
| CN108682691A (en) | The manufacturing method and semiconductor devices of transverse diffusion metal oxide semiconductor device | |
| TWI550883B (en) | Ldmos device and resurf structure | |
| CN115547838A (en) | Preparation method of metal oxide semiconductor device and device | |
| CN105655402A (en) | Low-voltage super-junction MOSFET (metal-oxide-semiconductor field effect transistor) terminal structure and method for manufacturing same | |
| CN104659091A (en) | Ldmos device and manufacturing method thereof | |
| CN109273364B (en) | Semiconductor structure and forming method thereof | |
| CN107546274B (en) | LDMOS device with step-shaped groove | |
| CN208240684U (en) | A kind of semiconductor devices | |
| US7768068B1 (en) | Drain extended MOS transistor with increased breakdown voltage | |
| CN112909093B (en) | Semiconductor device with a plurality of transistors | |
| CN102694020A (en) | Semiconductor device | |
| CN105633155A (en) | Structure and fabrication method of metal-oxide-semiconductor field-effect transistor | |
| CN111192915A (en) | Semiconductor power device and method for manufacturing the same | |
| CN104218080A (en) | Radio frequency LDMOS device and fabrication method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP02 | Change in the address of a patent holder | ||
| CP02 | Change in the address of a patent holder |
Address after: 310051 No. 6 Lianhui Street, Xixing Street, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: Hangzhou Silergy Semiconductor Technology Co., Ltd. Address before: 310012 A1501-A1505 and A1509-A1511, building 90, 71 Wensanlu Road, Xihu District, Zhejiang, Hangzhou, China Patentee before: Hangzhou Silergy Semiconductor Technology Co., Ltd. |