CN208063173U - A kind of dynamic circuit of the clock jitter removing based on digital phase-locked loop - Google Patents

Abstract

A kind of dynamic circuit of the clock jitter removing based on digital phase-locked loop, including digital phase-locked loop module, analog/digital conversion module and D A switch module；One end connection dithering clock signal source of the analog/digital conversion module, the other end are electrically connected with the digital phase-locked loop module；One end of the D A switch module is electrically connected with the analog/digital conversion module, and the other end is electrically connected with the digital phase-locked loop module.The advantageous effect of the application is：By the sinus wave patters that jitter clock is converted to number, is simulated, the final clock for obtaining Key dithering is of less demanding to system clock, reduces the design difficulty and cost of system；Digital phase-locked loop module realizes that consistency is good, and debugging difficulty is low, the Key dithering of low-jitter clock easy to implement using FPGA.

Description

A kind of dynamic circuit of the clock jitter removing based on digital phase-locked loop

Technical field

The application belongs to clock jitter removing and moves technical field, is gone specifically, being related to a kind of clock based on digital phase-locked loop Dither circuit.

Background technology

Common digital dock de-jittering method, the periodicity of the Key dithering clock signal recovered cannot still meet High-precision clock request.Reduce the variation of clock jitter, it is necessary to recovered clock frequency is improved, to improve to restoring The sample rate of clock.If the requirement to the variation of clock jitter is down to nanosecond, required recovered clock frequency is up to 1GHz is even higher.Under current technical conditions, this is difficult to realize, and it is also very high both to have made realization expense.And it is high The sample rate of frequency is very high to the design requirement of phase discriminator and loop filtering, and the design for virtually increasing support device again is difficult Degree and design cost, finally improve use cost.

Invention content

In view of this, there is provided a kind of clock jitter removings based on digital phase-locked loop for technical problems to be solved in this application Dynamic circuit, the frequency control word that the jitter clock difference information of phase discriminator unit acquisition, loop filtering unit can be utilized to obtain The Key dithering clock information that information and NCO are generated, recovers the clock after Key dithering.

In order to solve the above-mentioned technical problem, this application discloses a kind of clock jitter removings based on digital phase-locked loop to move circuit, And it is realized using following technical scheme.

A kind of clock jitter removing based on digital phase-locked loop moves circuit, including digital phase-locked loop module, analog/digital conversion module and D A switch module；One end connection dithering clock signal source of the analog/digital conversion module, the other end and the digital servo-control Ring moulds block is electrically connected；One end of the D A switch module is electrically connected with the analog/digital conversion module, the other end and the number Word phase-locked loop module is electrically connected.

Further, the digital servo-control ring element includes phase discriminator, loop filtering module and NCO modules, the phase demodulation Device, the loop filtering module and the NCO modules are sequentially connected electrically；And the input terminal of the phase discriminator turns with the analog/digital Block electrical connection is changed the mold, the output end of the NCO modules is electrically connected with the D A switch module.

Further, the D/A switch circuit uses AD9233 chips.

Further, the analog/digital conversion module uses DA9957 chips.

Compared with prior art, the application can be obtained including following technique effect：By the way that jitter clock is converted to number Word, simulation sinus wave patters, the final clock for obtaining Key dithering is of less demanding to system clock, reduces the design of system Difficulty and cost；Digital phase-locked loop module realizes that consistency is good, and debugging difficulty is low, low-jitter clock easy to implement using FPGA Key dithering.

Certainly, implement any product of the application it is not absolutely required to and meanwhile reach all the above technique effect.

Description of the drawings

Attached drawing described herein is used for providing further understanding of the present application, constitutes part of this application, this Shen Illustrative embodiments and their description please do not constitute the improper restriction to the application for explaining the application.In the accompanying drawings：

Fig. 1 is that the clock jitter removing based on digital phase-locked loop of the application one embodiment moves schematic block circuit diagram.

Fig. 2 is the phase discriminator functional block diagram of the application one embodiment.

Specific implementation mode

Presently filed embodiment is described in detail below in conjunction with accompanying drawings and embodiments, thereby how the application is applied Technological means solves technical problem and reaches the realization process of technical effect to fully understand and implement.

A kind of dynamic circuit of the clock jitter removing based on digital phase-locked loop, as shown in Figure 1, including digital phase-locked loop module, analog/digital Conversion module 1 and D A switch module 5.One end of analog/digital conversion module 1 connects original dithering clock signal source, the other end It is electrically connected with digital phase-locked loop module；One end of D A switch module 5 is electrically connected with analog/digital conversion module 1, the other end and number Word phase-locked loop module is electrically connected.

Digital phase-locked loop module includes phase discriminator 2, loop filtering module 3 and NCO modules 4 (i.e. numerically-controlled oscillator), Phase discriminator 2, loop filtering module 3 and NCO modules 4 are sequentially connected electrically.The specially input terminal of phase discriminator 2 and analog/digital conversion mould The output end of block 1 is electrically connected, and the output end of phase discriminator 2 is electrically connected with the input terminal of loop filtering module 3, loop filtering module 3 Output end be electrically connected with the input terminal of NCO modules 4, the output end and the input terminal of D A switch module 5 of NCO modules 4 are electrically connected It connects.

Phase discriminator 2, loop filtering module 3 and NCO modules 4 are generally realized by FPGA.D A switch module 5 generally by D/A switch circuit is converted to realize, such as using AD9233 chips.Analog/digital conversion module 1 is generally by analog/digital conversion Circuit is converted to realize, such as using DA9957 chips.

Pair A/D converter 1 carries out analog-to-digital conversion after collecting dithering clock signal to the clock signal of shake, i.e., The sine wave of original analog dithering clock signal is sampled, and converts thereof into Digital dither clock signal, and send phase demodulation to Device 2.Phase discriminator 2 receives analog/digital conversion module 1 and transmits the dithering clock signal of coming, and obtains between jitter clock and threshold value Difference, then send difference signal to loop filtering module 3.The difference signal that loop filtering module 3 obtains phase discriminator 2 into Row loop filtering simultaneously obtains frequency control word information, then sends the frequency control word information of acquisition to NCO modules 4.NCO modules 4 according to frequency control word information, and the corresponding digital sine wave signal generated using NCO oneself, generates clock information and passes Give D A switch module 5.The clock information that NCO modules 4 generate is converted into analog sine letter by D A switch module 5 Number, then it is transported to analog/digital conversion module 1, the analog sine clock signal after Key dithering is converted by analog/digital conversion module 1 At digitized sine wave clock signal with to be used.

The functional block diagram of phase discriminator 2 is as shown in Fig. 2, phase discriminator is indicated by UP and DN, and the output of adjustment NCO modules 4 is frequently Rate；When UP is effective, NCO frequencies should be increased, because NCO has already fallen behind in input signal；When DN is effective, NCO should be reduced Frequency, because NCO has been ahead of input signal.FPGA may be selected to realize in phase discriminator, also can be used other achievable Chip.Jitter clock enters phase discriminator unit, is compared with given threshold value to the waveform after sampling, output sampled value with Difference between threshold value；Threshold value is artificially to be arranged as needed, can be changed, which determines that recovered clock rises Along at the time of appearance.

Better Key dithering effect in order to obtain, the Key dithering process of the application can with circulating repetition, especially shake compared with Greatly, Key dithering can not be well in the case of recovering signal.

The advantageous effect of the application is：It is final to obtain by the sinus wave patters that jitter clock is converted to number, is simulated The clock of Key dithering, it is of less demanding to system clock, reduce the design difficulty and cost of system；Digital phase-locked loop module uses FPGA realizes that consistency is good, and debugging difficulty is low, the Key dithering of low-jitter clock easy to implement.

A kind of clock jitter removing based on digital phase-locked loop provided above the embodiment of the present application moves circuit, has carried out in detail It is thin to introduce.The description of the example is only used to help understand the method for the present application and its core ideas；Meanwhile for ability The those skilled in the art in domain, according to the thought of the application, there will be changes in the specific implementation manner and application range, comprehensive Upper described, the contents of this specification should not be construed as limiting the present application.

Some vocabulary has such as been used to censure specific components in specification and claims.Those skilled in the art , it is to be appreciated that hardware manufacturer may call the same component with different nouns.Present specification and claims are not In such a way that the difference of title is used as and distinguishes component, but it is used as the criterion of differentiation with the difference of component functionally.Such as Be an open language in "comprising" of the specification and claims in the whole text mentioned in, thus should be construed to " include but not It is defined in "." substantially " refer in receivable error range, those skilled in the art can solve within a certain error range The technical problem basically reaches the technique effect.Specification subsequent descriptions are to implement the better embodiment of the application, so The description is being not limited to scope of the present application for the purpose of the rule for illustrating the application.The protection of the application Range is when subject to the appended claims institute defender.

It should also be noted that, the terms "include", "comprise" or its any other variant are intended to nonexcludability Including so that commodity or system including a series of elements include not only those elements, but also include not clear The other element listed, or further include for this commodity or the intrinsic element of system.In the feelings not limited more Under condition, the element that is limited by sentence "including a ...", it is not excluded that including the element commodity or system in also There are other identical elements.

Several preferred embodiments of the application have shown and described in above description, but as previously described, it should be understood that the application Be not limited to form disclosed herein, be not to be taken as excluding other embodiments, and can be used for various other combinations, Modification and environment, and the above teachings or related fields of technology or knowledge can be passed through in application contemplated scope described herein It is modified.And changes and modifications made by those skilled in the art do not depart from spirit and scope, then it all should be in this Shen It please be in the protection domain of the appended claims.

Claims (4)

1. a kind of clock jitter removing based on digital phase-locked loop moves circuit, it is characterised in that：Including digital phase-locked loop module, analog/digital Conversion module (1) and D A switch module (5)；One end connection dithering clock signal source of the analog/digital conversion module (1), separately One end is electrically connected with the digital phase-locked loop module；One end of the D A switch module (5) and the analog/digital conversion module (1) it is electrically connected, the other end is electrically connected with the digital phase-locked loop module.

2. the clock jitter removing based on digital phase-locked loop moves circuit according to claim 1, it is characterised in that：The digital servo-control Ring element includes phase discriminator (2), loop filtering module (3) and NCO modules (4), the phase discriminator (2), the loop filtering mould Block (3) and the NCO modules (4) are sequentially connected electrically；And the input terminal of the phase discriminator (2) and the analog/digital conversion module (1) Electrical connection, the output end of the NCO modules (4) are electrically connected with the D A switch module (5).

3. the clock jitter removing based on digital phase-locked loop moves circuit according to claim 2, it is characterised in that：The D/A turns It changes circuit (5) and uses AD9233 chips.

4. the clock jitter removing based on digital phase-locked loop moves circuit according to claim 2, it is characterised in that：The analog/digital turns It changes the mold block (1) and uses DA9957 chips.