CN207868201U - The encapsulating structure of image sensing chip - Google Patents
The encapsulating structure of image sensing chip Download PDFInfo
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- CN207868201U CN207868201U CN201721909278.6U CN201721909278U CN207868201U CN 207868201 U CN207868201 U CN 207868201U CN 201721909278 U CN201721909278 U CN 201721909278U CN 207868201 U CN207868201 U CN 207868201U
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- image sensing
- sensing chip
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Abstract
The utility model discloses a kind of encapsulating structure of image sensing chip, including silicon base, and the silicon base has the first face and second face opposite with the first face；Interconnection layer is set to the first face of the silicon base, the weld pad that the interconnection layer is equipped with induction zone and is electrically coupled with the induction zone；Optical coating, is at least completely covered the induction zone, and the refractive index of the optical coating is less than or equal to 1.4；Transparent substrates, it is at least Nian Jie with the optical coating by adhesive.The encapsulating structure of the image sensing chip of the utility model can improve chip utilization rate.
Description
Technical field
The utility model is related to technical field of semiconductors, especially a kind of encapsulating structure of image sensing chip.
Background technology
With the trend of electronic product multifunction and miniaturization, high density microelectronic mounting technology is produced in electronics of new generation
Mainstream is increasingly becoming on product.In order to coordinate the development of electronic product of new generation, the size of chip to density higher, speed faster,
Smaller, the more low direction of cost is developed.With chip manufacturing process and it is imaged being constantly progressive for special process, promotes and adopts
With the exploitation of the image sensor of front illumination (FSI) technology.As human eye, light is fallen in chip FSI image sensors
Front is finally accumulated into light-sensing region then by reading circuit and interconnection.FSI technologies are current image sensor institute
The mainstream technology of use has the mass production ability, high reliability and the high yield that have obtained confirmation and has much attraction
The advantages such as cost performance have pushed its answering in various fields such as mobile phone, laptop, DV and digital cameras significantly
With.
Currently, the prior art needs to do CV walls, because CV walls have width requirement, induction region is limited to encapsulation chip
Edge will have a certain distance, limit the area of induction region, while can also introduce dust, video sensing area to induction region
The performance in domain.
For this purpose, still needing to be improved the prior art.
Utility model content
The purpose of this utility model is to provide a kind of encapsulating structure of image sensing chip, the encapsulating structure systems of the wafer
It is easy to make, and chip utilization rate is high.
To realize that above-mentioned purpose of utility model, the utility model disclose a kind of encapsulating structure of image sensing chip, wrap
It includes：
Silicon base, the silicon base have the first face and second face opposite with the first face；
Interconnection layer, is set to the first face of the silicon base, the interconnection layer be equipped with induction zone and with the induction
The weld pad that area is electrically coupled；
Optical coating, is at least completely covered the induction zone, and the refractive index of the optical coating is less than or equal to 1.4；
Transparent substrates, it is at least Nian Jie with the optical coating by adhesive.
As being further improved for one embodiment of the utility model, the induction is only completely covered in the optical coating
Area, and the shape of the optical coating is matched with the induction zone, and described adhesive is bonded in the optical coating and light transmission
Between the interconnection layer and transparent substrates that are covered between substrate and not by the optical coating.
As being further improved for one embodiment of the utility model, the optical coating be completely covered the induction zone with
And the interconnection layer, described adhesive are bonded between optical coating and transparent substrates.
As being further improved for one embodiment of the utility model, the second face of the silicon base is provided through described
The via of silicon base, for the via for exposing the weld pad, the via is configured to inverted trapezoidal, the edge of the induction zone away from
It is less than or equal to 100 microns with a distance from the weld pad.
As being further improved for one embodiment of the utility model, the second face of the silicon base is provided through described
The via of silicon base, for the via for exposing the weld pad, the via is configured to straight hole, the edge of the induction zone and institute
State the edge adjoining of weld pad.
As being further improved for one embodiment of the utility model, the refractive index of the optical coating is less than or equal to
1.2。
As being further improved for one embodiment of the utility model, the thickness of the optical coating between 1-2 microns,
The thickness of described adhesive is between 20-60 microns, and the thickness of the transparent substrates is between 100-300 microns.
As being further improved for one embodiment of the utility model, the transparent substrates are configured to glass substrate, described
The light transmittance of adhesive is more than or equal to 60%.
As being further improved for one embodiment of the utility model, the light transmittance of described adhesive is more than or equal to
75%.
As being further improved for one embodiment of the utility model, the encapsulating structure further includes again wiring layer and is electrically connected
Connecting terminal, the wiring layer again are set to the top in the second face of the silicon base, the electric connection terminal setting it is described again
Wiring layer, the electric connection terminal are electrically connected with the wiring layer again, and for being electrically connected with external circuit.
Compared with prior art, the beneficial effects of the utility model are：The utility model is coated with completely on interconnection layer
The optical coating of induction zone is covered, transparent substrates are at least Nian Jie with optical coating by adhesive, relieve and do CV walls to induction
Chip utilization rate is improved, and process stabilizing and reliability are high to the distance limitation of encapsulation chip edge in area.
Description of the drawings
Fig. 1 is showing for the encapsulating structure of the image sensing chip after being cut in the preferred first embodiment of the utility model
It is intended to；
Fig. 2 is showing for the encapsulating structure of the image sensing chip after being cut in the preferred second embodiment of the utility model
It is intended to；
Fig. 3 to Figure 10 is the process sequence diagram of the packaging method of the encapsulating structure of image sensing chip in Fig. 1, wherein：
Fig. 3 is the structural schematic diagram of the image sensing chip coated optical coating in Fig. 1；
Fig. 4 is the structural schematic diagram of the packaging body after the image sensing chip in Fig. 3 is Nian Jie with transparent substrates；
Fig. 5 is to form the structural schematic diagram after opening in Fig. 4 on image sensing chip packing-body；
Fig. 6 is to form the structural schematic diagram after insulating layer in Fig. 5 on image sensing chip packing-body；
Fig. 7 is to form the structural schematic diagram after wiring layer again in Fig. 6 on image sensing chip packing-body；
Fig. 8 is the structural schematic diagram that image sensing chip packing-body carries out after first time cutting in Fig. 7；
Fig. 9 is the structural schematic diagram that image sensing chip packing-body forms after solder mask in Fig. 8；
Figure 10 is that image sensing chip packing-body carries out the structural schematic diagram after cutting second in Fig. 9；
Figure 11 is the structural schematic diagram of the image sensing chip coated optical coating in Fig. 2；
Figure 12 is the structural schematic diagram of the packaging body after the image sensing chip in Figure 11 is Nian Jie with transparent substrates.
Specific implementation mode
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work
The every other embodiment obtained, shall fall within the protection scope of the present invention.
It should be noted that the purpose for providing these attached drawings is to help to understand the embodiments of the present invention, and
It should not be construed as the improper restriction to the utility model.For the sake of becoming apparent from, size as shown in the figure is not necessarily to scale, can
Can make amplify, reduce or other change.In addition, the three dimensions ruler of length, width and depth should be included in actual fabrication
It is very little.Be formed as in addition, structure of the fisrt feature described below in the "upper" of second feature may include the first and second features
The embodiment being in direct contact, can also be formed in the embodiment between the first and second features including other feature, and such
One and second feature may not be to be in direct contact.
To keep the above objects, features, and advantages of the utility model more obvious and easy to understand, below in conjunction with the accompanying drawings and have
Body embodiment is described in further detail the utility model.
It is the image sensing chip in the preferred first embodiment of the utility model with reference to shown in figure 1 and Fig. 3 to Fig. 5
Encapsulating structure, the encapsulating structure include silicon base 10, and silicon base 10 includes the first face and second face opposite with the first face, silicon substrate
Second face at bottom 10, as the second face of image sensing chip.First face of silicon base 10, which makes, interconnection layer 20, interconnection layer 20
On be provided with multiple video sensing areas 201 and multiple with 201 electric coupling of video sensing area weld pad 203.
The optical coating 30 that induction zone 201 is completely covered is coated on interconnection layer 20, the surface of optical coating 30 can be done
Flat, i.e., induction zone 201 and interconnection layer 20 is completely covered in optical coating 30, and transparent substrates 70 pass through adhesive 40 and optical coating
30 bondings, form image sensing chip packing-body, image sensing chip packing-body includes multiple image sensings to link together
Device.Transparent substrates 70 are preferably glass substrate.The refractive index of optical coating 30 is less than or equal to 1.4, it is preferred that optical coating
30 refractive index is less than or equal to 1.2, i.e., better closer to 1 effect.The light transmittance of adhesive 40 is more than or equal to 60%,
The light transmittance of preferred adhesive 40 is more than or equal to 75%, i.e. adhesive 40 has high transparency.Preferably, optical coating
30 thickness is between 1-2 microns, and the thickness of adhesive 40 is between 20-60 microns, and the thickness of transparent substrates 70 is in 100-300
Between micron.
First face of silicon base 10 is provided with wiring layer 50 again, is at least used to be electrically connected weld pad 203.It is set on wiring layer 50 again
It is equipped with electric connection terminal, preferred in the present embodiment, electric connection terminal is configured to solder-bump 55 (BGA), naturally it is also possible to be
The plane weld pad (LGA) being formed in again on wiring layer 50, i.e., the contact terminal being made of a part for wiring layer 50 again.It welds convex
It plays 55 to be electrically connected with weld pad 203 with by wiring layer 50 again, and for being electrically connected with external circuit.The metal line materials connected up again
It is copper, then connecting up has enhancing to connect up copper again and weld pad 203 is attached to each other the metal or alloy film of power between copper and weld pad 203,
The metal or alloy material can be nickel, titanium, nickel chromium triangle, titanium tungsten etc..The forming method of wiring layer 50 includes that metal film, light again
The sequence technique that quarter, copper facing, striping, copper/titanium etch.
With reference to shown in Fig. 6, the first face of silicon base 10 is provided through the via 15 of silicon base 10, and via 15 is for exposing
Weld pad 203, in order to realize being electrically connected for solder-bump 55 and weld pad 203.Wherein, via 15 can be bilayer step via,
Inverted trapezoidal hole or straight hole.Specifically, straight hole can be cylindrical or prismatic via.At this point, via refers to by the first face
To on the direction in the second face, the aperture of via is gradually constant.Certainly, the cross section of straight hole can also be rectangle, ellipse or
Other shapes.Via 15 is corresponded with weld pad 203, and via 15 is for exposing corresponding weld pad 203.The method for forming via 15
There are laser boring, photoetching etc..
With reference to shown in Fig. 7, solder-bump 55 is electrically connected by the wiring layer again 50 being arranged in via 15 with weld pad 203.
Also there is between wiring layer 50 and silicon base 10 insulating layer 60 again.Insulating layer 60 covers the side wall of via 15, and exposes via 15
Bottom, in order to which wiring layer 50 again and weld pad 203 are electrically connected.Wiring layer 50 covers bottom and the insulating layer 60 of via again.
Insulating layer 60 is preferably configured to insulation/dielectric film, and insulation/dielectric film is insulation/dielectric film of photaesthesia, such as SU-
8.Photaesthesia dielectric film can by rotary coating or press mold, photoetching a sequence process deposits the first of silicon base 10
Face.
With reference to shown in Fig. 9, specifically, being additionally provided with solder mask 80 on 50 surface of wiring layer again, 80 surface of solder mask has
It is provided with the opening of solder-bump 55, in order to which solder-bump 55 is arranged so that the wiring layer again of solder-bump 55 and opening
50 electrical connections.The method for forming solder mask 80 includes a sequence technique of deposition, photoetching, chemical plating nickel aluminum.The image of formation passes
The encapsulating structure of sense chip can be cut to such as the encapsulating structure in Fig. 1.
By foregoing description it is found that in the utility model embodiment encapsulating structure, it is coated on interconnection layer and sense is completely covered
The optical coating in area is answered, transparent substrates are at least Nian Jie with optical coating by adhesive, relieve and do CV walls to induction zone to envelope
The distance at cartridge chip edge limits, i.e. the distance of induction zone to encapsulation chip edge can be most short, improves chip utilization rate, and
Process stabilizing and reliability are high.
It is the image sensing chip in the preferred second embodiment of the utility model with reference to shown in figure 2 and Figure 11 to Figure 12
Encapsulating structure, which includes silicon base 10, and silicon base 10 includes the first face and second face opposite with the first face, silicon
Second face of substrate 10, as the second face of image sensing chip.First face of silicon base 10, which makes, interconnection layer 20, interconnection layer
Multiple video sensing areas 201 and multiple and 201 electric coupling of video sensing area weld pad 203 are provided on 20.
The optical coating 30 for the induction zone 201 being only completely covered on interconnection layer 20, optical coating are coated on interconnection layer 20
30 coating shape and the shape of induction zone 201 matches, transparent substrates 70 by adhesive 40 and optical coating 30 and not by
The interconnection layer 20 that optical coating 30 covers is bonded, and forms image sensing chip packing-body, and image sensing chip packing-body includes more
A image sensor to link together.The other structures of the encapsulating structure of image sensing chip in the present embodiment are real with first
It is identical to apply example, which is not described herein again.
Based on above-mentioned encapsulating structure embodiment, the utility model additionally provides a kind of packaging method, which is used for
The encapsulating structure of above-described embodiment is formed, which includes：
Image sensing chip is formed, as shown in Fig. 2, specifically comprising：A piece of silicon base 10 is provided, silicon base 10 is wrapped
Include the first face and second face opposite with the first face, the second face of silicon base 10, as the second face of image sensing chip.In silicon
First face of substrate 10 makes interconnection layer 20, and multiple video sensing areas 201 on interconnection layer 20 and multiple and image
The weld pad 203 that induction zone 201 coordinates.
Form the optical coating 30 that the induction zone 201 on interconnection layer 20 is at least completely covered, the refraction of the optical coating 30
Rate is less than or equal to 1.4, is more preferably less than or equal to 1.2, better closer to 1.
Image sensor substrate is formed, specifically comprising：A piece of transparent substrates 70 are provided, transparent substrates 70 at least with
Optical coating 30 is bonded by adhesive 40, forms image sensing chip packing-body, image sensing chip packing-body includes multiple
The image sensor to link together.As shown in Figure 4 and Figure 5, in the first embodiment, sense is completely covered in coated optical coating 30
Area 201 and interconnection layer 20, adhesive 40 is answered to be bonded between optical coating 30 and transparent substrates 70.Such as Figure 11 and Figure 12 institutes
Show, in a second embodiment, induction zone 201 is only completely covered in coated optical coating 30, and adhesive 40 is bonded in optical coating
Between 30 and transparent substrates 70 and between interconnection layer 20 and transparent substrates 70.The light transmittance of adhesive is more than or equal to
60%, more preferably it is more than or equal to 75%.
After the completion of bonding, the second face of silicon base 10 is ground thinned.As shown in Figure 6, Figure 7, and after being thinned,
Second face of silicon base 10 forms multiple vias 15 and multiple Cutting Roads opening 16 using photoetching and plasma etch techniques.
Wherein, via 15 can expose weld pad 203, and Cutting Road opening 16 can expose interconnection layer 20.Preferably, in the utility model one
Further include a slot opening 13 in embodiment, via 15 is set in slot opening 13, that is to say, that via 15 is terraced
Shape step via, in this manner, the distance of the Edge Distance weld pad of induction zone can be accomplished to be less than or equal to 100 micro-
Rice, expands the area of induction zone with this.Certainly, if via is set as straight hole, the Edge Distance weld pad of induction zone can approach
In 0, that is to say, that the edge of induction zone can be abutted with weld pad.Skilled person will appreciate that Cutting Road opening is disposed on
Between two adjacent image sensors, it is mainly used for the image sensor that segmentation links together.Usually, it is set to
Between the adjacent welding-pad of two adjacent image sensors.Details are not described herein.
Insulating layer 60 is formed by gas phase deposition technology on the surface of silicon base 10 after photoetching and plasma etching,
The surface of covering is all faces for exposing silicon base 10.Specifically, as shown in fig. 7, insulating layer 60 is covered in silicon base 10
Second face and via 15, Cutting Road are open on the side wall of 16, slot opening 13.On insulating layer 60 and 203 surface of weld pad of exposure
Wiring layer 50 again are formed by photoetching, plating, then wiring layer 50 is also formed into exposed 20 surface of interconnection layer.
After completing above-mentioned technique, the image sensing chip packing-body of formation can be cut.
As shown in figure 8, carrying out first time cutting to image sensing chip packing-body by the first cutter, adjacent shadow is detached
As the interconnection layer of sensor；Specifically, the first cutter is cut along Cutting Road opening 16 to 20 direction of interconnection layer.It is preferred that
Ground, first time depth of cut, which is can be controlled in, is switched to some adhesive 40.Being cut to the representative of some adhesive 40 will not glue
Mixture 40 detaches.Because the material of interconnection layer 20 is more crisp, ductility, toughness are poor, and it is hard to carry out the first cutter of first time cutting
Larger knife is spent, in this way, the injury to interconnection layer 20 can be reduced, interconnection layer 20 is avoided to crack.Preferably, the first cutter is gold
Belong to knife.Cutting for the first time or scribing line cutting, laser are carried out along Cutting Road opening two side to the interconnection layer direction
Cutting.
As shown in figure 9, the outermost layer in the first face side of silicon base 10 forms solder mask 80, and it is electrically connected cloth again
Multiple solder-bumps 55 of line layer 50；It is, on exposed 60 surface of partial insulative layer, again 50 surface of wiring layer and first
The opening inner wall of cutter cutting is respectively formed on solder mask 80.
Cutting openings along cutting for the first time are to 70 direction of light-transparent substrate, by the second cutter to image sensing chip package
Body carries out second and cuts, to obtain multiple independent image sensors.It is soft compared with the first cutter that material may be selected in second cutter
Knife.Preferably, it can be selected and the resin knife of the material of cutting transparent substrates 70 be suitble to be the second cutter, be more than second to avoid hardness
First cutter of cutter damages transparent substrates 70, also avoids that transparent substrates edge is caused to burst apart.
In this way, the wafer-level packaging method of the image sensor by the utility model, reduces cutting and is interconnected to wafer
The injury that layer and transparent base are done avoids interconnection layer, transparent substrates cracking, also reduces extraneous steam or dust erosion image sensing
The problem of device, effectively improves the performance and reliability of image sensor.
Although this specification is described in terms of embodiments, but not each embodiment only includes an independent skill
Art scheme, this description of the specification is merely for the sake of clarity, and those skilled in the art should be using specification as one
A entirety, the technical solution in each embodiment may also be suitably combined to form it will be appreciated by those skilled in the art that its
His embodiment.
Tool of the series of detailed descriptions listed above only for the feasible embodiment of the utility model
Body illustrates that they are all without departing from made by the utility model skill spirit not to limit the scope of protection of the utility model
Equivalent implementations or change should be included within the scope of protection of this utility model.
Claims (10)
1. a kind of encapsulating structure of image sensing chip, which is characterized in that including：
Silicon base, the silicon base have the first face and second face opposite with the first face；
Interconnection layer, is set to the first face of the silicon base, and the interconnection layer is electric equipped with induction zone and with the induction zone
The weld pad of coupling；
Optical coating, is at least completely covered the induction zone, and the refractive index of the optical coating is less than or equal to 1.4；
Transparent substrates, it is at least Nian Jie with the optical coating by adhesive.
2. the encapsulating structure of image sensing chip according to claim 1, which is characterized in that the optical coating is only complete
The induction zone is covered, and the shape of the optical coating is matched with the induction zone, described adhesive is bonded in the light
It learns between coating and transparent substrates and between the interconnection layer and transparent substrates that are not covered by the optical coating.
3. the encapsulating structure of image sensing chip according to claim 1, which is characterized in that the optical coating covers completely
It covers the induction zone and the interconnection layer, described adhesive is bonded between optical coating and transparent substrates.
4. the encapsulating structure of image sensing chip according to claim 1, which is characterized in that the second face of the silicon base
It is provided through the via of the silicon base, for the via for exposing the weld pad, the via is configured to inverted trapezoidal, described
The distance of weld pad described in the Edge Distance of induction zone is less than or equal to 100 microns.
5. the encapsulating structure of image sensing chip according to claim 1, which is characterized in that the second face of the silicon base
It is provided through the via of the silicon base, for the via for exposing the weld pad, the via is configured to straight hole, the sense
The edge at the edge for answering area and the weld pad abuts.
6. the encapsulating structure of image sensing chip according to claim 1, which is characterized in that the refraction of the optical coating
Rate is less than or equal to 1.2.
7. the encapsulating structure of image sensing chip according to claim 1, which is characterized in that the thickness of the optical coating
Between 1-2 microns, the thickness of described adhesive is between 20-60 microns, and the thickness of the transparent substrates is at 100-300 microns
Between.
8. the encapsulating structure of image sensing chip according to claim 1, which is characterized in that the transparent substrates are configured to
The light transmittance of glass substrate, described adhesive is more than or equal to 60%.
9. the encapsulating structure of image sensing chip according to claim 8, which is characterized in that the light transmittance of described adhesive
More than or equal to 75%.
10. the encapsulating structure of image sensing chip according to claim 1, which is characterized in that the encapsulating structure also wraps
Wiring layer again and electric connection terminal are included, the wiring layer again is set to the top in the second face of the silicon base, the electrical connection
Terminal is arranged in the wiring layer again, and the electric connection terminal is electrically connected with the wiring layer again, and for electric with external circuit
Connection.
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| CN201721909278.6U CN207868201U (en) | 2017-12-29 | 2017-12-29 | The encapsulating structure of image sensing chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994045A (en) * | 2017-12-29 | 2018-05-04 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure of image sensing chip and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994045A (en) * | 2017-12-29 | 2018-05-04 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure of image sensing chip and preparation method thereof |
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