CN207489450U

CN207489450U - Shift register cell, gate driving circuit, display device

Info

Publication number: CN207489450U
Application number: CN201721709702.2U
Authority: CN
Inventors: 刘鹏; 王珍; 张寒; 张锴; 乔赟; 孙建; 刘白灵; 黄飞; 王争奎; 张建军
Original assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Current assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Priority date: 2017-12-08
Filing date: 2017-12-08
Publication date: 2018-06-12
Anticipated expiration: 2027-12-08

Abstract

The utility model provides a kind of shift register cell, gate driving circuit, display device, is related to display technology field, can solve the problems, such as that the shift register cell in gate driving circuit can not reset caused gate driving circuit output abnormality.Shift register cell, including：Pull-up node and pull-down node, further include：First input module, the first signal end of connection, first voltage end and first node, for by the voltage output of the first signal end to first node；Pull up control module, connection first node, second voltage end and second node, for by the voltage output at second voltage end to second node；Pull-down control module, connection first node, tertiary voltage end, the first clock signal terminal, signal output end and pull-down node, for by the voltage output at tertiary voltage end to pull-down node；Or for by the voltage output at tertiary voltage end to pull-down node；Or for by the voltage output of the first clock signal terminal to pull-down node.

Description

Shift register cell, gate driving circuit, display device

Technical field

The utility model is related to display technology field more particularly to a kind of shift register cell, gate driving circuit, show Showing device.

Background technology

With the continuous improvement of display technology, requirement of the people for display device is also being continuously improved, wherein, big ruler The display technologies such as very little, high-resolution, narrow frame increasingly attract attention.The very important technology of one of which is exactly GOA (Gate Driver on Array, integrated gate drive circuitry) technology mass production realization.Using GOA technologies by gate driving circuit collection Into in the array substrate of display panel, so as to save grid-driving integrated circuit part, with from material cost and making Two aspect of technique reduces product cost.This gate switch circuit using GOA Integration ofTechnologies in array substrate is also referred to as GOA Each shift register in circuit or shift-register circuit, wherein the gate switch circuit is also referred to as GOA unit.

Existing gate driving circuit, reset signal end and the next stage shift register list of this grade of shift register cell The signal output end of member is connected, this causes the drop-down stage of this grade of shift register cell to rely on next stage shift register list The signal that member provides could be completed, and when next stage shift register cell output abnormality, this grade of shift register can be caused Unit can not complete the drop-down stage, lead to gate driving circuit output abnormality.

Utility model content

The embodiment of the utility model provides a kind of shift register cell, gate driving circuit, display device, can solve Shift register cell in gate driving circuit can not reset the problem of caused gate driving circuit output abnormality.

In order to achieve the above objectives, the embodiment of the utility model adopts the following technical scheme that：

In a first aspect, a kind of shift register cell is provided, including：Pull-up node and pull-down node, the pull-up node For the signal output end of the shift register cell to be controlled to export gated sweep signal, the pull-down node is used to stop institute Signal output end output gated sweep signal is stated, the shift register cell further includes：First input module, pull-up control mould Block and pull-down control module；First input module, the first signal end of connection, first voltage end and first node, for Under the control at the first voltage end, by the voltage output of first signal end to the first node；The pull-up control Module connects the first node, second voltage end and second node, described under the control of the first node, inciting somebody to action The voltage output at second voltage end is to the second node；The pull-down control module connects the first node, tertiary voltage End, the first clock signal terminal, the signal output end and the pull-down node, under the control of the first node, inciting somebody to action The voltage output at the tertiary voltage end is to the pull-down node；Or under the control of the signal output end, by institute The voltage output at tertiary voltage end is stated to the pull-down node；Or under the control of first clock signal terminal, inciting somebody to action The voltage output of first clock signal terminal is to the pull-down node；Wherein, the second node connects with the pull-up node It connects.

Optionally, the shift register cell further includes：Filter module；The filter module, connection second section Point, the pull-up node, the second voltage end, it is under the control at the second voltage end, the second node is defeated Enter to the clutter in the signal of the filter module and exported after filtering out to the pull-up node.

Optionally, the shift register cell further includes：Second input module；Second input module, connection the Binary signal end, the 4th voltage end and the first node, under the control of the 4th voltage end, by the second signal The voltage output at end is to the first node.

Optionally, the shift register cell further includes：Pull-down module and output module；The pull-down module, connection The pull-down node, the second node, the signal output end and the tertiary voltage end, in the pull-down node Under control, by the voltage output at the tertiary voltage end to the second node and the signal output end；The output module, The pull-up node, second clock signal end, the signal output end are connected, under the control of the pull-up node, inciting somebody to action The voltage output of the second clock signal end is to the signal output end.

Optionally, the shift register cell further includes：Initialization module；The initialization module, connection third letter Number end, the second voltage end and the pull-down node, under the control of the third signal end, by the second voltage The voltage output at end is to the pull-down node.

Optionally, the shift register cell further includes：Residual lotus cancellation module；The residual lotus cancellation module, connection the Four signal ends, the tertiary voltage end, the second node, the pull-down node and the signal output end, for described Under the control at fourth signal end, the voltage output at the tertiary voltage end to the second node and the pull-down node is gone back For by the voltage output at the fourth signal end to the signal output end.

Optionally, first input module includes the first transistor；The grid connection described the of the first transistor One signal end, the first pole connect the first voltage end, and the second pole connects the first node.

Optionally, the pull-up control module includes second transistor；The grid connection described the of the second transistor One node, the first pole connect the second voltage end, and the second pole connects the second node.

Optionally, the pull-down control module includes third transistor, the 4th transistor, the 5th transistor；The third The grid of transistor connects first clock signal terminal, and the first pole connects first clock signal terminal, the second pole connection institute State pull-down node；The grid of 4th transistor connects the first node, and the first pole connects the pull-down node, the second pole Connect the tertiary voltage end；The grid of 5th transistor connects the signal output end, and the first pole connects the drop-down Node, the second pole connect the tertiary voltage end.

Optionally, the pull-down control module further includes the 6th transistor；Described in the grid connection of 6th transistor Second voltage end, the first pole connect first clock signal terminal, and the second pole connects the grid of the third transistor.

Optionally, the pull-down control module further includes the first capacitance；First capacitance the first pole connection it is described under Node is drawn, the second pole connects the tertiary voltage end.

Optionally, when the shift register cell further includes filter module, the filter module includes the 7th transistor； The grid of 7th transistor connects the second voltage end, and the first pole connects the second node, described in the connection of the second pole Pull-up node.

Optionally, when the shift register cell further includes the second input module, second input module includes the Eight transistors；The grid of 8th transistor connects the second signal end, and the first pole connects the first node, the second pole Connect the 4th voltage end.

Optionally, the pull-down module includes the 9th transistor and the tenth transistor, and the output module includes the 11st Transistor and the second capacitance；The grid of 9th transistor connects the pull-down node, and the first pole connects the second node, Second pole connects the tertiary voltage end；The grid of tenth transistor connects the pull-down node, described in the connection of the first pole Signal output end, the second pole connect the tertiary voltage end；The first pole connection pull-up node of second capacitance, second Pole connects the signal output end；The grid of 11st transistor connects the pull-up node, the first pole connection described the Two clock signal terminals, the second pole connect the signal output end.

Optionally, when the shift register cell further includes initialization module, the initialization module includes the 12nd Transistor；The grid of tenth two-transistor connects the third signal end, and the first pole connects the pull-down node, the second pole Connect the second voltage end.

Optionally, when the shift register cell further includes residual lotus cancellation module, the residual lotus cancellation module includes the 13 transistors, the 14th transistor and the 15th transistor；The grid of 13rd transistor connects the fourth signal End, the first pole connect the pull-down node, and the second pole connects the tertiary voltage end；The grid connection of 14th transistor The fourth signal end, the first pole connect the signal output end, and the second pole connects the fourth signal end；Described 15th is brilliant The grid of body pipe connects the fourth signal end, and the first pole connects the second node, and the second pole connects the tertiary voltage end.

Second aspect provides a kind of gate driving circuit, the displacement as described in relation to the first aspect including at least two-stage cascade Register cell；First signal end of first order shift register cell is connected with initial signal end；In addition to the first order Other than shift register cell, the first signal end and its upper level shift register cell per level-one shift register cell Signal output end is connected.

Optionally, the shift register cell further includes second signal input module；In addition to afterbody shift LD Other than device unit, second signal end and the signal of its next stage shift register cell per level-one shift register cell export End is connected；The second signal end of the afterbody shift register cell connects the initial signal end or resets letter Number end.

The third aspect also provides a kind of display device, including the gate driving circuit described in second aspect.

Fourth aspect provides a kind of driving method for being used to drive the shift register cell described in first aspect, one In picture frame, the method includes：Input phase：Under the control at first voltage end, the first input module is by the first signal end The cut-in voltage of input is exported to first node, and the first node control pull-up control module is opened, by second voltage end Voltage is exported through second node to pull-up node；The drop-down stage：Under the control of the first clock signal terminal, pull-down control module will The clock signal of first clock signal terminal is exported to pull-down node.

Optionally, the shift register cell includes the second input module, filter module, pull-down module and output mould Block；The method further includes：Input phase：Under the control at the first voltage end, first input module is by described The cut-in voltage of one signal end input is exported to the first node, and the first node control pull-up control module is opened It opens, by the voltage output at the second voltage end to the second node, the filter module inputs the second node Clutter in signal is exported after filtering out to the pull-up node；Alternatively, under the control of the 4th voltage end, the second input mould Block exports the cut-in voltage that second signal end inputs to the first node, the first node control pull-up control mould Block is opened, and by the voltage output at the second voltage end to the second node, the filter module is defeated by the second node Clutter in the signal entered is exported after filtering out to the pull-up node；The output stage：It is described under the control of the pull-up node Output module exports the clock signal of second clock signal end to signal output end, and the signal output end exports gated sweep Signal；The drop-down stage further includes：Under the control of the pull-down node, drop-down that pull-down module inputs tertiary voltage end The clutter that signal is exported in the signal for inputting the second node to the second node, the filter module exports after filtering out To the pull-up node, the output circuit is controlled to close；The drop-down that the pull-down module also inputs the tertiary voltage end Signal is exported to the signal output end.

Optionally, the shift register cell includes initialization module and residual lotus cancellation module；The method further includes： Initial phase：Under the control of third signal end, the initialization module is by the voltage output at the second voltage end to institute State pull-down node；Under the control of the pull-down node, the pulldown signal that pull-down module inputs the tertiary voltage end exports To the second node, output is on described after the clutter in the signal that the filter module inputs the second node filters out Draw node；The pull-down module also exports the pulldown signal that the tertiary voltage end inputs to the signal output end；Residual lotus The elimination stage：Under the control at fourth signal end, pull-up signal that the residual lotus cancellation module inputs the tertiary voltage end Export the clutter in the signal for the second node being inputted to the pull-down node and the second node, the filter module It is exported after filtering out to the pull-up node；The residual lotus cancellation module is also by the voltage output at the fourth signal end to the letter Number output terminal.

The utility model embodiment provides a kind of shift register cell, gate driving circuit, display device, is driving Cheng Zhong, drop-down stage are to believe the clock of the first clock signal terminal by the pull-down control module of this grade of shift register cell Number output to pull-down node, so as to drag down the current potential of pull-up node, and low level signal is exported to signal output end, to complete The drop-down stage of shift register cell.Therefore, the reseting stage of the shift register cell in the utility model and other grades The signal of shift register cell output is unrelated, so as to a degree of stability for improving gate driving circuit.

Description of the drawings

It in order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor Under, it can also be obtained according to these attached drawings other attached drawings.

Fig. 1 is the structure diagram of a kind of shift register cell that the utility model embodiment provides；

Fig. 2 is the structure diagram of another shift register cell that the utility model embodiment provides；

Fig. 3 is the structure diagram of another shift register cell that the utility model embodiment provides；

Fig. 4 is the structure diagram of another shift register cell that the utility model embodiment provides；

Fig. 5 is the structure diagram of another shift register cell that the utility model embodiment provides；

Fig. 6 is the control signal timing diagram of a kind of shift register cell that the utility model embodiment provides；

Sequence diagram when Fig. 7 is a kind of shift register cell signal disorder that the prior art provides；

Fig. 8 is the structure diagram of a kind of gate driving circuit that the utility model embodiment provides.

Reference numeral

The first input modules of 10-；20- pulls up control module；30- pull-down control modules；40- filter modules；50- second is defeated Enter module；60- pull-down modules；70- output modules；80- initialization modules；The residual lotus cancellation modules of 90-；PU- pull-up nodes；PD- Lower drawknot node；A- first nodes；B- second nodes；The first signal ends of S1-；S2- second signals end；S3- third signal ends；S4- Fourth signal end；V1- first voltages end；V2- second voltages end；V3- tertiary voltages end；The 4th voltage ends of V4-；OUTPUT- believes Number output terminal；The first clock signal terminals of CKB-；CK- second clock signal ends.

Specific embodiment

The following is a combination of the drawings in the embodiments of the present utility model, and the technical scheme in the embodiment of the utility model is carried out It clearly and completely describes, it is clear that the described embodiments are only a part of the embodiments of the utility model rather than whole Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are without making creative work All other embodiments obtained shall fall within the protection scope of the present invention.

The utility model embodiment provides a kind of shift register cell, as shown in Figure 1, including：Pull-up node PU is under The signal output end OUTPUT that node PD, pull-up node PU are used to control shift register cell is drawn to export gated sweep signal, Pull-down node PD exports gated sweep signal for stop signal output terminal OUTPUT.

Wherein, pull-up node PU exports gated sweep signal, i.e. pull-up node PU for control signal output OUTPUT High level signal is exported for control signal output OUTPUT；Pull-down node PD exports for stop signal output terminal OUTPUT Gated sweep signal, i.e. pull-down node PD export low level signal for control signal output OUTPUT.

Certainly, those skilled in the art should also be understood that for the pull-up node PU in shift register cell and For lower drawknot node, the two is typically in opposite state, for example, pull-up node PU in running order (for example, high level State) when, pull-down node PD is in off working state (for example, low level state)；Pull-up node PU is in inoperative shape During state (for example, low level state), pull-down node PD is in running order (for example, high level state).

As shown in Figure 1, the shift register cell further includes：First input module 10, pull-up control module 20 and drop-down Control module 30.

First input module 10, the first signal end S1 of connection, first voltage end V1 and first node A, in the first electricity Under the control of pressure side V1, by the voltage output of the first signal end S1 to first node A.

Pull up control module 20, connection first node A, second voltage end V2 and second node B, in first node A Control under, by the voltage output of second voltage end V2 to second node B.

Pull-down control module 30, connection first node A, tertiary voltage end V3, the first clock signal terminal CKB, signal output OUTPUT and pull-down node PD is held, under the control of first node A, by the voltage output of tertiary voltage end V3 to pulling down section Point PD；Or under the control of signal output end OUTPUT, by the voltage output of tertiary voltage end V3 to pull-down node PD； Or under the control of the first clock signal terminal CKB, by the voltage output of the first clock signal terminal CKB to pull-down node PD。

Wherein, second node B is connect with pull-up node PU.

Those skilled in the art is it is to be understood that can refer to Fig. 1, in shift register cell, pull-up node PU with Output module 70 connects, and opens output module 70 by pull-up node PU to export gated sweep by signal output end OUTPUT Signal (high level signal)；Pull-down node PD is connect with pull-down module 60, opens pull-down module 60 by pull-down node PD to lead to Cross signal output end OUTPUT output terminations signal (for example, can be low level signal).

Herein it should be noted that first, second node B is connect with pull-up node PU, can be with as shown in Figure 1, the second section Point B is directly connected to (two nodes are overlapped as a node) with pull-up node PU；Can also include other modules, the mould Block is all connected with second node B and pull-up node PU, and when the module is connected, second node B is connect with pull-up node PU.

The shift register cell that the utility model embodiment provides, during driving, the drop-down stage is by this The pull-down control module 30 of grade shift register cell exports the clock signal of the first clock signal terminal CKB to pull-down node PD so as to drag down the current potential of pull-up node PU, and low level signal is exported to signal output end OUTPUT, is posted to complete displacement The drop-down stage of storage unit.Therefore, the reseting stage of the shift register cell in the utility model is posted with other grade of displacement The signal of storage unit output is unrelated, so as to a degree of stability for improving gate driving circuit.

On this basis, in order to improve the quality for the signal for being input to pull-up node PU, as shown in Fig. 2, the displacement is posted Storage unit further includes filter module 40.

Filter module 40, connection second node B, pull-up node PU, second voltage end V2, for second voltage end V2's Under control, output is to pull-up node PU after the clutter that second node B is input in the signal of filter module 40 filters out.

Further, it forward scan and is reversely swept in order to which shift register cell provided by the utility model is enable to realize It retouches, as shown in Fig. 2, the shift register cell further includes the second input module 50.

Second input module 50, connection second signal end S2, the 4th voltage end V4 and first node A, in the 4th electricity Under the control of pressure side V4, by the voltage output of second signal end S2 to first node A.

Further, as depicted in figs. 1 and 2, the shift register cell further includes：Pull-down module 60 and output module 70。

Pull-down module 60, connection pull-down node PD, second node B, signal output end OUTPUT and tertiary voltage end V3, is used Under the control in pull-down node PD, by the voltage output of tertiary voltage end V3 to second node B and signal output end OUTPUT.

Output module 70, connection pull-up node PU, second clock signal end CK, signal output end OUTPUT, for Under the control for drawing node PU, by the voltage output of second clock signal end CK to signal output end OUTPUT.

Further, in order to be initialized when needed to shift register cell provided by the utility model, As shown in Fig. 2, shift register cell provided by the utility model further includes initialization module 80.

Initialization module 80, connection third signal end S3, second voltage end V2 and pull-down node PD, in third signal Under the control for holding S3, by the voltage output of second voltage end V2 to pull-down node PD.

When shift register cell breaks down, in order to not influence the use of the shift register cell after restarting, As shown in Fig. 2, shift register cell provided by the utility model further includes residual lotus cancellation module 90.

Residual lotus cancellation module 90, connection fourth signal end S4, tertiary voltage end V3, second node B, pull-down node PD and letter Number output terminal OUTPUT, under the control of fourth signal end S4, by the voltage output of tertiary voltage end V3 to second node B With pull-down node PD, it is additionally operable to the voltage output of fourth signal end S4 to signal output end OUTPUT.

Hereinafter, the concrete structure of the modules in above-mentioned shift register cell is described in detail.

Optionally, as shown in Fig. 3, Fig. 4, Fig. 5, the first input module 10 includes the first transistor T1.

The grid of the first transistor T1 connects the first signal end S1, the first pole connection first voltage end V1, the connection of the second pole First node A.

As shown in Fig. 3, Fig. 4, Fig. 5, pull-up control module 20 includes second transistor T2.

The grid connection first node A of second transistor T2, the first pole connection second voltage end V2, the second pole connection second Node B.

As shown in Fig. 3, Fig. 4, Fig. 5, pull-down control module 30 includes third transistor T3, the 4th transistor T4, the 5th crystalline substance Body pipe T5.

The grid of third transistor T3 connects the first clock signal terminal CKB, and the first pole connects the first clock signal terminal CKB, Second pole connection pull-down node PD.

The grid connection first node A of 4th transistor T4, the first pole connection pull-down node PD, the second pole connection third electricity Pressure side V3.

The grid connection signal output terminal OUTPUT of 5th transistor T5, the first pole connection pull-down node PD, the second pole connects Meet tertiary voltage end V3.

As shown in Figure 4 and Figure 5, pull-down control module 30 further includes the 6th transistor T6.

The grid connection second voltage end V2 of 6th transistor T6, the first pole connects the first clock signal terminal CKB, the second pole Connect the grid of third transistor T3.

Further, as shown in Figure 4 and Figure 5, pull-down control module 30 further includes the first capacitance C1.

The first pole connection pull-down node PD of first capacitance C1, the second pole connection tertiary voltage end V3.

As shown in Figure 4 and Figure 5, filter module 40 includes the 7th transistor T7.

The grid connection second voltage end V2 of 7th transistor T7, the first pole connection second node B, the second pole connection pull-up Node PU.

As shown in Fig. 3, Fig. 4, Fig. 5, the second input module 50 includes the 8th transistor T8.

The grid connection second signal end S2 of 8th transistor T8, the first pole connection first node A, the second pole connection the 4th Voltage end V4.

As shown in Fig. 3, Fig. 4, Fig. 5, pull-down module 60 includes the 9th transistor T9 and the tenth transistor T10.

The grid connection pull-down node PD of 9th transistor T9, the first pole connection second node B, the second pole connection third electricity Pressure side V3.

The grid connection pull-down node PD of tenth transistor T10, the first pole connection signal output terminal OUTPUT, the second pole connects Meet tertiary voltage end V3.

As shown in Fig. 3, Fig. 4, Fig. 5, output module 70 includes the 11st transistor T11 and the second capacitance C2.

The first pole connection the pull-up node PU, the second pole connection signal output terminal OUTPUT of second capacitance C2.

The grid connection pull-up node PU of 11st transistor T11, the first pole connection second clock signal end CK, the second pole Connection signal output terminal OUTPUT.

As shown in figure 5, initialization module 80 includes the tenth two-transistor T12.

The grid connection third signal end S3 of tenth two-transistor T12, the first pole connection pull-down node PD, the connection of the second pole Second voltage end V2.

As shown in figure 5, residual lotus cancellation module 90 includes the 13rd transistor T13, the 14th transistor T14 and the 15th crystalline substance Body pipe T15.

The grid connection fourth signal end S4 of 13rd transistor T13, the first pole connection pull-down node PD, the connection of the second pole Tertiary voltage end V3.

Grid connection fourth signal the end S4, the first pole connection signal output terminal OUTPUT, second of 14th transistor T14 Pole connection fourth signal end S4.

The grid connection fourth signal end S4 of 15th transistor T15, the first pole connection second node B, the connection of the second pole Tertiary voltage end V3.

It should be noted that above-mentioned transistor can be N-type transistor, or P-type transistor；Can be enhanced Transistor, or depletion mode transistor；The first of above-mentioned transistor extremely can be source electrode, second extremely can be drain electrode or The first of the above-mentioned transistor of person extremely can be drain electrode, and second extremely source electrode, the utility model is not construed as limiting this.

Hereinafter, by taking above-mentioned transistor is N-type transistor as an example, with reference to signal timing diagram shown in fig. 6 to shown in fig. 5 Break-make situation of the shift register cell in the different stages of a picture frame (such as U frames, U >=1, U are positive integer) carries out Detailed illustration.Wherein, the first clock signal terminal CKB and second clock signal end CK be complementary signal, first voltage end V1 and the 4th voltage end V4 is the low and high level for controlling positive counter-scanning, is with second voltage end V2 perseverances in the utility model embodiment Surely the explanation carried out for high level is exported.In addition, following explanation is by taking forward scan as an example, i.e., with the first signal input module Work, second signal input module illustrate (i.e. first voltage end V1 input high level signals, the 4th voltage for not working Hold V4 input low levels signal).When reverse scan, second signal input module work, the first signal input module does not work.

In input phase P1, S1=1, CK=0, CKB=1, S3=0, S4=0；Wherein, " 0 " represents low level, " 1 " table Show high level.

At this point, since first voltage end V1 exports high level signal, the first transistor T1 conductings, so as to which first be believed The high level signal of number end S1 is exported to first node A, and control second transistor T2 is opened, and the voltage of second voltage end V2 is through the Two-transistor T2 is transmitted to second node B.Since second voltage end V2 exports high level signal, the 7th transistor T7 is normal Open transistor, the output after the 7th transistor T7 filtering of the high level signal on second node B to pull-up node PU, and passes through the Two capacitance C2 store the high level signal.Under the control of pull-up node PU high potentials, the 11st transistor T11 is led It is logical, by the low level output of second clock signal end CK to signal output end OUTPUT.In the control of pull-up node PU high potentials Under, the 11st transistor T11 conductings by the low level output of second clock signal end CK to signal output end OUTPUT, and are controlled Make the 5th transistor T5 cut-offs.

At the same time, the high level signal of the first signal end S1 is exported to first node A, and the high level of first node A is believed Number control the 4th transistor T4 open, the low level signal of tertiary voltage end V3 is transmitted to pull-down node PD, at this point, even if Under the control of the high level signal of second voltage end V2 outputs, the 6th transistor T6 conductings, by the height of the first clock signal terminal CKB Level is exported to the grid of third transistor T3, and control third transistor T3 is opened, by the high level of the first clock signal terminal CKB Output is to pull-down node PD, but third transistor T3, the 4th transistor T4 and the 6th transistor T6 are in the partial pressure of pull-down node PD So that the 9th transistor T9 and the tenth transistor T10 ensures the charged state of pull-up node PU still in cut-off state.

Third signal end S3 input low levels signal controls the tenth two-transistor T12 cut-offs, and S4 inputs in fourth signal end are low Level signal, the 13rd transistor T13 of control, the 14th transistor T14, the 15th transistor T15 cut-offs.

In conclusion the first transistor T1 is opened, second transistor T2 is opened, third transistor T3 ends, the 4th crystal Pipe T4 is opened, the 5th transistor T5 cut-offs, the 6th transistor T6 is opened, the 7th transistor T7 is opened, the 8th transistor T8 ends, 9th transistor T9 cut-offs, the tenth transistor T10 cut-offs, the 11st transistor T11 are opened, the tenth two-transistor T12 cut-offs, the 13 transistor T13 cut-offs, the 14th transistor T14 cut-offs, the 15th transistor T15 cut-offs, signal output end OUTPUT exist Above-mentioned input phase P1 exports low level.

Output stage P2, S1=0, CK=1, CKB=0, S3=0, S4=0.

At this point, since first voltage end V1 exports high level signal, the first transistor T1 conductings, so as to which first be believed The low level signal of number end S1 is exported to first node A, controls second transistor T2 and the 4th transistor T4 cut-offs.Second capacitance C2 charges to pull-up node PU with the high level that input phase P1 is stored, so that the 11st transistor T11 holdings are opened Open state.In the case, the high level of second clock signal end CK is exported by the 11st transistor T11 to signal output end OUTPUT, and the 5th transistor T5 is controlled to open, the low level signal of tertiary voltage end V3 is transmitted to by the 5th transistor T5 The low level signal of pull-down node PD, pull-down node PD control the 9th transistor T9 and the tenth transistor T10 cut-offs.

In addition, under bootstrapping (Bootstrapping) effect of the second capacitance C2, the current potential of pull-up node PU further rises It is high that (the second capacitance C2 is 1 by 0 saltus step with the current potential of signal output end OUTPUT one end connecting, in the second capacitance C2 to pull-up When node PU is charged, the current potential of pull-up node PU is on the basis of 1 again to high potential saltus step 1), to maintain the 11st crystal The state that pipe T11 is on, so that the high level of second clock signal end CK can be used as gated sweep signal to export To the grid line being connected with signal output end OUTPUT.

At the same time, under the control of the high level signal of second voltage end V2 outputs, the 6th transistor T6 conductings, first Clock signal exports low level signal, the T3 cut-offs of control third transistor.

In conclusion the first transistor T1 is opened, second transistor T2 ends, third transistor T3 ends, the 4th crystal Pipe T4 cut-offs, the 5th transistor T5 are opened, the 6th transistor T6 is opened, the 7th transistor T7 is opened, the 8th transistor T8 ends, 9th transistor T9 cut-offs, the tenth transistor T10 cut-offs, the 11st transistor T11 are opened, the tenth two-transistor T12 cut-offs, the 13 transistor T13 cut-offs, the 14th transistor T14 cut-offs, the 15th transistor T15 cut-offs, signal output end OUTPUT exist Above-mentioned output stage P2 exports high level, to export gated sweep signal to the grid line being connected with signal output end OUTPUT.

Drop-down stage P3, S1=0, CK=0, CKB=1, S3=0, S4=0.

At this point, since first voltage end V1 exports high level signal, the first transistor T1 conductings, so as to which first be believed The low level signal of number end S1 is exported to first node A, controls second transistor T2 and the 4th transistor T4 cut-offs.In the second electricity Under the control of the high level signal of pressure side V2 outputs, the 7th transistor T7 and the 6th transistor T6 conductings, the first clock signal are defeated The high level signal control third transistor T3 gone out is opened, and the high level signal that the first clock signal is exported is transmitted to drop-down Node PD, pull-down node PD control the 9th transistor T9 and the tenth transistor T10 are opened, by the 9th transistor T9 by second The current potential of node B is pulled down to the low level of tertiary voltage end V3, and the low level signal of second node B is filtered out through the 7th transistor T7 Pull-up node PU is transmitted to after clutter, i.e., the current potential of pull-up node PU is pulled down to the low level of tertiary voltage end V3, and is controlled 11st transistor T11 ends；The current potential of signal output end OUTPUT is pulled down to by tertiary voltage end by the tenth transistor T10 The low level of V3, and control the 5th transistor T5 cut-offs.First capacitance C1 stores the high level of pull-down node PD, makes Draw the holding high level of node PU long-time stables.

In addition, third signal end S3 input low levels signal controls the tenth two-transistor T12 cut-offs, fourth signal end S4 is defeated Enter low level signal, the 13rd transistor T13 of control, the 14th transistor T14, the 15th transistor T15 cut-offs.

In conclusion the first transistor T1 is opened, second transistor T2 ends, third transistor T3 is opened, the 4th crystal Pipe T4 cut-offs, the 5th transistor T5 end, the 6th transistor T6 is opened, the 7th transistor T7 is opened, the 8th transistor T8 ends, 9th transistor T9 is opened, the tenth transistor T10 is opened, the 11st transistor T11 cut-offs, the tenth two-transistor T12 cut-offs, the 13 transistor T13 cut-offs, the 14th transistor T14 cut-offs, the 15th transistor T15 cut-offs, signal output end OUTPUT exist Above-mentioned drop-down stage P3 exports low level.

Wherein, in above-mentioned drop-down stage P3, as shown in figure 3, without the 6th transistor T6, then the first clock signal terminal CKB High level signal control third transistor T3 open, and the high level signal of the first clock signal terminal CKB is transmitted to drop-down Node PD.As described in Fig. 4 and Fig. 5, including the 6th transistor T6, then the high level signal of the first clock signal terminal CKB is through opening The 6th transistor T6 be transmitted to the grid of third transistor T3, control third transistor T3 is opened, the first clock signal terminal CKB High level signal be transmitted to pull-down node PD through third transistor T3.

Shift register cell (not including the 6th transistor T6) as shown in Figure 3, in the voltage such as Fig. 6 of pull-down node PD Shown in dotted line, shift register cell (including the 6th transistor T6) as shown in Figure 4 and Figure 5, the voltage of pull-down node PD is such as It is shown in solid in Fig. 6.As can be seen from Figure 6, shift register cell pull-down node PD voltages as shown in Figure 3 can not completely keep The high level (there is loss) of one clock signal, due to N-type transistor, when exporting high level, there are inevitable threshold values Loss, causes third transistor T3 to be unable to reach complete high point open width value when charging to pull-down node PD, there are certain Loss.Such as figure more complete holding high level that marks of shift register cell pull-down node PD voltages as shown in Figure 4 and Figure 5, After increasing by the 6th transistor T6, the 6th transistor T6 and third transistor T3 cooperations so that third transistor T3 grids occur certainly It lifts so that the high level signal of the first clock signal terminal CKB is charged by third transistor T3 can completelys to pull-down node PD, Threshold value is avoided to lose, realizes that the high level signal of the first clock signal terminal CKB is lossless and is input to pull-down node PD, play to drop-down Node PD signals promoted the effect of driving force and waveform shaping, so that it is guaranteed that pull-down node PD signals is continual and steady, The performance and stability of display apparatus grid driving are improved, therefore the preferred pull-down control module 30 of the utility model embodiment is also Including the 6th transistor T6.

Herein, existing shift register cell, this grade of shift register cell export low electricity in above-mentioned drop-down stage P3 It is flat to be realized by this grade of shift register cell, but rely on the high level signal of next stage shift register cell output Come what is completed.So, as shown in fig. 7, in the case of next stage extremely output, this grade of shift register list can not be realized The reset of member leads to follow-up chain output abnormality.And shift register cell provided by the utility model, increase second transistor T2, and change the signal output end OUTPUT of upper level shift register cell with behind the connecting pin of this grade of shift register cell (the signal output end OUTPUT of upper level shift register cell not grid with this grade of shift register cell the first transistor T1 Extremely it is connected), the reset unit and holding reset unit of shift register cell are all third transistor T3, since this grade the 4th is brilliant It is low level (dotted line in Fig. 6 that body pipe T4 remains off i.e. first node A after input signal after input low level signal Represent the potential change of first node A in the prior art, solid line represents the potential change of first node A in the utility model), make Pull-down node PD can be transmitted to by third transistor T3 by obtaining the high level signal of the first clock signal terminal CKB, to draw high drop-down Node PD, which drags down pull-up node PU and realizes, to be resetted, and next stage output extremely is avoided to make this grade that can not reset, avoids the occurrence of and subsequently connects The abnormal output of lock promotes the performance and stability of display apparatus grid driving.

Initial phase P4, S1=0, CK=0, CKB=0, S3=1, S4=0.

At this point, third signal end S3 exports high level signal, the tenth two-transistor T12 of control is opened, by second voltage end The high level signal of V2 is exported to pull-down node PD, pull-down node PD control the 9th transistor T9 and the tenth transistor T10 and is opened, 9th transistor T9 exports the low level signal of tertiary voltage end V3 to pull-up node PU, and the tenth transistor T10 is electric by third The low level signal of pressure side V3 is exported to signal output end OUTPUT, by pull-up node PU and the voltage of signal output end OUTPUT It drags down, completes the initialization to shift register cell.

In conclusion in initial phase P4, the first transistor T1 is opened, second transistor T2 ends, third crystal Pipe T3 cut-offs, the 4th transistor T4 end, the 5th transistor T5 cut-offs, the 6th transistor T6 is opened, the 7th transistor T7 is opened, 8th transistor T8 cut-offs, the 9th transistor T9 unlatchings, the tenth transistor T10 unlatchings, the 11st transistor T11 cut-offs, the tenth Two-transistor T12 is opened, the 13rd transistor T13 cut-offs, the 14th transistor T14 ends, the 15th transistor T15 ends, Signal output end OUTPUT exports low level in above-mentioned initial phase P4.

Residual lotus eliminates stage P5, S1=0, S3=0, S4=1.

At this point, fourth signal end S4 exports high level, the 13rd transistor T13 of control, the 14th transistor T14, the tenth Five transistor T15 are opened, and the 14th transistor T14 exports the high level signal of third signal end S3 to signal output end OUTPUT makes signal output end OUTPUT export gated sweep signal, so that entire circuit completes electric discharge, eliminates because of abnormal show And remain in the charge in circuit.

In order to ensure the eradicating efficacy of residual lotus, the high level signal that the 15th transistor T15 exports third signal end S3 Output is to pull-up node PU, to avoid the output of other effect of signals signal output ends OUTPUT.

At the same time, in order to further ensure the eradicating efficacy of residual lotus, the 13rd transistor T13 is defeated by third signal end S3 The high level signal gone out is exported to pull-down node PD, pull-down node PD control the 9th transistor T9 and the tenth transistor T10 and is opened, The V3 high level signals exported in tertiary voltage end are exported respectively to pull-up node PU and signal output end OUTPUT.

Herein it should be noted that when entering residual lotus elimination stage P5, the signal of third signal end S3 outputs can be by low Level signal becomes high level signal.It, can be mono- by the 14th transistor T14 if shift register cell does not have above-mentioned function It solely completes residual lotus and eliminates task.

Residual lotus cancellation module 90 provided by the utility model, including the 13rd transistor T13, the 14th transistor T14 and 15th transistor T15, three transistors match, and realize signal output end OUTPUT outputs as high level and pull-up is kept to save Point PU more ensures that pull-up node PU is high level while being high level, improves the performance and stabilization of display apparatus grid driving Property.

In conclusion eliminating stage P5 in the residual lotus, the first transistor T1 is opened, second transistor T2 ends, third is brilliant Body pipe T3 cut-offs, the 4th transistor T4 cut-offs, the 5th transistor T5 cut-offs, the 6th transistor T6 is opened, the 7th transistor T7 is opened Open, the 8th transistor T8 cut-offs, the 9th transistor T9 is opened, the tenth transistor T10 is opened, the 11st transistor T11 cut-offs, the Ten two-transistor T12 cut-offs, the 13rd transistor T13 are opened, the 14th transistor T14 is opened, the 15th transistor T15 is opened It opens, signal output end OUTPUT eliminates stage P5 output high level in above-mentioned residual lotus.

It should be noted that the switching process of transistor is to be as N-type transistor using all transistors in above-described embodiment What example illustrated, when all transistors are p-type, need to overturn control signal each in Fig. 5, and shift LD The make and break process of the transistor of modules is same as above in device unit, and details are not described herein again.

In addition, the course of work of above-mentioned shift register cell, is formed with above-mentioned multiple shift register cell cascades Gate driving circuit by the way of the forward scan for the explanation that carries out.When using reverse scan, in Fig. 3, Fig. 4 and figure In shift register cell shown in 5, end the first transistor T1, the 8th transistor T8 is opened.

The utility model embodiment provides a kind of gate driving circuit, as shown in figure 8, including the above-mentioned of at least two-stage cascade Shift register cell (RS1, RS2 ... RSn).

The first signal end S1 of first order shift register cell RS1 is connected with initial signal end STV；In addition to the first order Other than shift register cell RS1, the first signal end S1 per level-one shift register cell RS (n) is posted with the displacement of its upper level The signal output end OUTPUT of storage unit R S (n-1) is connected.Wherein, initial signal end STV, should for exporting initial signal The first order shift register cell RS1 of gate driving circuit start after above-mentioned initial signal is received to grid line (G1, G2 ... Gn) it is progressively scanned.

When shift register cell further includes the second input module 50, in addition to afterbody shift register cell with Outside, the letter of the second signal end S2 and its next stage shift register cell RS (n+1) per level-one shift register cell RS (n) Number output terminal OUTPUT is connected；The second signal end S2 connection initial signals end STV of afterbody shift register cell or Person's reset signal end (is carried out in Fig. 8 with the second signal end S2 connection initial signals end STV of afterbody shift register cell Signal).So, initial signal end STV is for exporting initial signal, during the gate driving circuit reverse scan, last Grade shift register cell starts to progressively scan grid line (G1, G2 ... Gn) after above-mentioned initial signal is received.

The advantageous effect of gate driving circuit and having for above-mentioned shift register cell that the utility model embodiment provides Beneficial effect is identical, and details are not described herein again.

The utility model embodiment provides a kind of display device, including any one gate driving circuit as described above, With the structure and advantageous effect identical with the gate driving circuit that previous embodiment provides.Since previous embodiment is to grid The structure and advantageous effect of pole driving circuit are described in detail, and details are not described herein again.

It should be noted that in the utility model embodiment, display device specifically can at least include LCD display Plate or organic LED display panel, such as the display panel can be applied to liquid crystal display, LCD TV, digital phase In any product or component with display function such as frame, mobile phone or tablet computer.

The utility model embodiment provides a kind of method for driving any one above-mentioned shift register cell, specifically In a picture frame, the method includes：

Input phase P1：

Under the control of first voltage end V1, the cut-in voltage that the first input module 10 inputs the first signal end S1 exports To first node A, first node A control pull-up control modules 20 are opened, and the voltage of second voltage end V2 is defeated through second node B Go out to pull-up node PU.At the same time, first node A controls pull-down control module 30 to open, by the low electricity of tertiary voltage end V3 Ordinary mail number output to pull-down node PD, control pull-down module 60 is closed.At this point, initialization module 80 and residual lotus cancellation module 90 are equal It closes.

When in above-mentioned shift register cell modules structure as shown in figure 5, and transistor in modules it is equal During for N-type transistor, in input phase P1, the first signal end S1 input high level signals, the first clock signal terminal CKB is defeated Enter high level, second clock signal end CK input low levels, third signal end S3 input low levels, fourth signal end S4 inputs low Level, first voltage end V1 input high levels, second voltage end V2 input high levels, tertiary voltage end V3 input low levels, the Four voltage end V4 input low levels, pull-up node PU are high level, and pull-down node PD is low level, and signal output end OUTPUT is defeated Go out low level.

When shift register cell further includes filter module 40, input phase P1：

Under the control of first voltage end V1, the cut-in voltage that the first input module 10 inputs the first signal end S1 exports To first node A, first node A control pull-up control modules 20 are opened, by the voltage output of second voltage end V2 to the second section Point B, output is to pull-up node PU after the clutter in the signal that filter module 40 inputs second node B filters out.

At the same time, the high level signal of first node A controls the 4th transistor T4 to open, by the low of tertiary voltage end V3 Level signal is transmitted to pull-down node PD, at this point, even if second voltage end V2 output high level signal control under, the 6th Transistor T6 is connected, and by the grid of the high level output of the first clock signal terminal CKB to third transistor T3, controls third crystal Pipe T3 is opened, by the high level output of the first clock signal terminal CKB to pull-down node PD, but third transistor T3, the 4th crystal Pipe T4 and the 6th transistor T6 cause the 9th transistor T9 and the tenth transistor T10 still in cut-off in the partial pressure of pull-down node PD State ensures the charged state of pull-up node PU.

Output stage P2：

Under the control of pull-up node PU, output module 70 by the clock signal of second clock signal end CK, (believe by high potential Number) export to signal output end OUTPUT, signal output end OUTPUT output gated sweep signals.At the same time, signal exports The high level signal control pull-down control module 30 of end OUTPUT outputs is opened, and the low level signal of tertiary voltage end V3 is exported To pull-down node PD, control pull-down module 60 is closed.At this point, initialization module 80 and residual lotus cancellation module 90 are turned off.

When in above-mentioned shift register cell modules structure as shown in figure 5, and transistor in modules it is equal During for N-type transistor, in output stage P2, the first signal end S1 input low levels, second clock signal end CK input height Level, the first clock signal terminal CKB input low levels, third signal end S3 input low levels, fourth signal end S4 input low electricity It is flat, first voltage end V1 input high levels, second voltage end V2 input high levels, tertiary voltage end V3 input low levels, the 4th Voltage end V4 input low levels, pull-up node PU are high level, and pull-down node PD is low level, and signal output end OUTPUT is exported Low level.

In addition, under the boot strap of the second capacitance C2, the current potential of pull-up node PU further increases, to maintain the 11st The state that transistor T11 is on, so that the high level of second clock signal end CK can be used as gated sweep signal In output to the grid line being connected with signal output end OUTPUT.

Drop-down stage P3：

Under the control of the first clock signal terminal CKB, pull-down control module 30 believes the clock of the first clock signal terminal CKB Number (high potential signal) output is to pull-down node PD.

Under the control of pull-down node PD, pull-down module 60 exports the V3 pulldown signals inputted in tertiary voltage end to second Node B, output is to pull-up node PU, control output after the clutter in the signal that filter module 40 inputs second node B filters out Circuit is closed；Pull-down module 60 also exports the V3 pulldown signals inputted in tertiary voltage end to signal output end OUTPUT.

At the same time, the low level signal control pull-up control module 20 of the first signal end S1 inputs is closed.At this point, output Module 70, initialization module 80 and residual lotus cancellation module 90 are turned off.

When in above-mentioned shift register cell modules structure as shown in figure 5, and transistor in modules it is equal During for N-type transistor, in drop-down stage P3, the first signal end S1 input low levels, second clock signal end CK inputs low Level, the first clock signal terminal CKB input high levels, third signal end S3 input low levels, fourth signal end S4 input low electricity It is flat, first voltage end V1 input high levels, second voltage end V2 input high levels, tertiary voltage end V3 input low levels, the 4th Voltage end V4 input low levels, pull-up node PU are low level, and pull-down node PD is high level, and signal output end OUTPUT is exported Low level.

Initial phase P4：

Under the control of third signal end S3, initialization module 80 is by the voltage output of second voltage end V2 to pull-down node PD；Under the control of pull-down node PD, pull-down module 60 exports the V3 pulldown signals inputted in tertiary voltage end to second node B, output is to pull-up node PU after the clutter in the signal that filter module 40 inputs second node B filters out；Pull-down module 60 is also The V3 pulldown signals inputted in tertiary voltage end are exported to signal output end OUTPUT.

At this stage, initialization module 80, pull-down module 60, filter module 40 are opened.

When in above-mentioned shift register cell modules structure as shown in figure 5, and transistor in modules it is equal During for N-type transistor, in initial phase P4, the first signal end S1 input low levels, second clock signal end CK inputs Low level, the first clock signal terminal CKB input low levels, third signal end S3 input high levels, fourth signal end S4 inputs are low Level, first voltage end V1 input high levels, second voltage end V2 input high levels, tertiary voltage end V3 input low levels, the Four voltage end V4 input low levels, pull-up node PU are low level, and pull-down node PD is high level, and signal output end OUTPUT is defeated Go out low level.

Residual lotus eliminates stage P5：

Under the control of fourth signal end S4, the pull-up signal that residual lotus cancellation module 90 inputs tertiary voltage end V3 exports To pull-down node PD and second node B, the clutter in the signal that filter module 40 inputs second node B exports supreme after filtering out Draw node PU；Residual lotus cancellation module 90 is also by the voltage output of fourth signal end S4 to signal output end OUTPUT.

At this stage, residual lotus cancellation module 90, pull-down module 60, filter module 40 are opened.

When in above-mentioned shift register cell modules structure as shown in figure 5, and transistor in modules it is equal During for N-type transistor, in the residual lotus eliminates stage P5, the first signal end S1 input low levels, second clock signal end CK is defeated Enter low level, the first clock signal terminal CKB input high levels, third signal end S3 input low levels, fourth signal end S4 inputs High level, first voltage end V1 input high levels, second voltage end V2 input high levels, tertiary voltage end V3 input high levels, 4th voltage end V4 input low levels, pull-up node PU be high level, pull-down node PD be high level, signal output end OUTPUT Export high level.

At this point, fourth signal end S4 exports high level, the 13rd transistor T13 of control, the 14th transistor T14, the tenth Five transistor T15 are opened, and the 14th transistor T14 exports the high level signal of third signal end S3 to signal output end OUTPUT, the 15th transistor T15 export the third signal end S3 high level signals exported to pull-up node PU, and the 13rd is brilliant Body pipe T13 exports the third signal end S3 high level signals exported to pull-down node PD, the 9th crystal of pull-down node PD control Pipe T9 and the tenth transistor T10 are opened, the V3 high level signals exported in tertiary voltage end are exported respectively to pull-up node PU and Signal output end OUTPUT.

It is to be opened with the first input module 10 above, the closing of the second input module 50 is illustrated, when reverse scan, the One module is closed, and the second module is opened, i.e. the 4th voltage end V4 input high level signals, and first voltage end V1 inputs low electricity Ordinary mail number, other signals are constant.

The driving method for the shift register unit that the utility model embodiment provides, advantage are posted with above-mentioned displacement Storage unit is identical, and details are not described herein again.

The above, only specific embodiment of the present utility model, but the scope of protection of the utility model is not limited to In this, in the technical scope that any one skilled in the art discloses in the utility model, variation can be readily occurred in Or replace, it should be covered within the scope of the utility model.Therefore, the scope of protection of the utility model should be with the power Subject to the protection domain of profit requirement.

Claims

1. a kind of shift register cell, including：Pull-up node and pull-down node, the pull-up node are used to control the displacement The signal output end output gated sweep signal of register cell, the pull-down node export for stopping the signal output end Gated sweep signal, which is characterized in that the shift register cell further includes：First input module, pull-up control module and Pull-down control module；

First input module, the first signal end of connection, first voltage end and first node, at the first voltage end Control under, by the voltage output of first signal end to the first node；

The pull-up control module connects the first node, second voltage end and second node, in the first node Control under, by the voltage output at the second voltage end to the second node；

The pull-down control module connects the first node, tertiary voltage end, the first clock signal terminal, signal output End and the pull-down node, under the control of the first node, by the voltage output at the tertiary voltage end to described Pull-down node；Or under the control of the signal output end, by the voltage output at the tertiary voltage end under described Draw node；Or under the control of first clock signal terminal, by the voltage output of first clock signal terminal extremely The pull-down node；

Wherein, the second node is connect with the pull-up node.

2. shift register cell according to claim 1, which is characterized in that the shift register cell further includes： Filter module and/or the second input module；

The filter module connects the second node, the pull-up node, the second voltage end, for described second Under the control of voltage end, output is to described after the clutter that the second node is input in the signal of the filter module filters out Pull-up node；

Second input module, connection second signal end, the 4th voltage end and the first node, in the described 4th electricity Under the control of pressure side, by the voltage output at the second signal end to the first node.

3. shift register cell according to claim 1 or 2, which is characterized in that the shift register cell also wraps It includes：Pull-down module and output module；

The pull-down module connects the pull-down node, the second node, the signal output end and the tertiary voltage End, under the control of the pull-down node, by the voltage output at the tertiary voltage end to the second node and described Signal output end；

The output module connects the pull-up node, second clock signal end, the signal output end, for described Under the control for drawing node, by the voltage output of the second clock signal end to the signal output end.

4. shift register cell according to claim 1 or 2, which is characterized in that the shift register cell also wraps It includes：Initialization module and/or residual lotus cancellation module；

The initialization module, connection third signal end, the second voltage end and the pull-down node, in the third Under the control of signal end, by the voltage output at the second voltage end to the pull-down node；

The residual lotus cancellation module, connection fourth signal end, the tertiary voltage end, the second node, the pull-down node With the signal output end, under the control at the fourth signal end, by the voltage output at the tertiary voltage end to institute Second node and the pull-down node are stated, is additionally operable to the voltage output at the fourth signal end to the signal output end.

5. shift register cell according to claim 1, which is characterized in that it is brilliant that first input module includes first Body pipe；

The grid of the first transistor connects first signal end, and the first pole connects the first voltage end, and the second pole connects Connect the first node.

6. shift register cell according to claim 1, which is characterized in that it is brilliant that the pull-up control module includes second Body pipe；

The grid of the second transistor connects the first node, and the first pole connects the second voltage end, the connection of the second pole The second node.

7. shift register cell according to claim 1, which is characterized in that it is brilliant that the pull-down control module includes third Body pipe, the 4th transistor, the 5th transistor；

The grid of the third transistor connects first clock signal terminal, and the first pole connects first clock signal terminal, Second pole connects the pull-down node；

The grid of 4th transistor connects the first node, and the first pole connects the pull-down node, the second pole connection institute State tertiary voltage end；

The grid of 5th transistor connects the signal output end, and the first pole connects the pull-down node, the connection of the second pole The tertiary voltage end.

8. shift register cell according to claim 7, which is characterized in that the pull-down control module further includes the 6th Transistor；

The grid connection second voltage end of 6th transistor, the first pole connection first clock signal terminal, second Pole connects the grid of the third transistor.

9. shift register cell according to claim 7 or 8, which is characterized in that the pull-down control module further includes First capacitance；

First pole of first capacitance connects the pull-down node, and the second pole connects the tertiary voltage end.

10. shift register cell according to claim 2, which is characterized in that the shift register cell further includes During filter module, the filter module includes the 7th transistor；

The grid of 7th transistor connects the second voltage end, and the first pole connects the second node, the connection of the second pole The pull-up node.

11. shift register cell according to claim 2, which is characterized in that the shift register cell further includes During the second input module, second input module includes the 8th transistor；

The grid of 8th transistor connects the second signal end, and the first pole connects the first node, the connection of the second pole 4th voltage end.

12. shift register cell according to claim 3, which is characterized in that the pull-down module includes the 9th crystal Pipe and the tenth transistor, the output module include the 11st transistor and the second capacitance；

The grid of 9th transistor connects the pull-down node, and the first pole connects the second node, the second pole connection institute State tertiary voltage end；

The grid of tenth transistor connects the pull-down node, and the first pole connects the signal output end, the connection of the second pole The tertiary voltage end；

First pole of second capacitance connects the pull-up node, and the second pole connects the signal output end；

The grid connection pull-up node of 11st transistor, the first pole connection second clock signal end, second Pole connects the signal output end.

13. shift register cell according to claim 4, which is characterized in that the shift register cell further includes During initialization module, the initialization module includes the tenth two-transistor；

The grid of tenth two-transistor connects the third signal end, and the first pole connects the pull-down node, and the second pole connects Connect the second voltage end.

14. shift register cell according to claim 4, which is characterized in that the shift register cell further includes During residual lotus cancellation module, the residual lotus cancellation module includes the 13rd transistor, the 14th transistor and the 15th transistor；

The grid of 13rd transistor connects the fourth signal end, and the first pole connects the pull-down node, and the second pole connects Connect the tertiary voltage end；

The grid of 14th transistor connects the fourth signal end, and the first pole connects the signal output end, the second pole Connect the fourth signal end；

The grid of 15th transistor connects the fourth signal end, and the first pole connects the second node, and the second pole connects Connect the tertiary voltage end.

15. a kind of gate driving circuit, which is characterized in that including at least two-stage cascade as described in claim any one of 1-14 Shift register cell；

First signal end of first order shift register cell is connected with initial signal end；

Other than the first order shift register cell, the first signal end and thereon one per level-one shift register cell The signal output end of grade shift register cell is connected.

16. gate driving circuit according to claim 15, which is characterized in that the shift register cell further includes Binary signal input module；

Other than afterbody shift register cell, second signal end and its next stage per level-one shift register cell The signal output end of shift register cell is connected；

The second signal end of the afterbody shift register cell connects the initial signal end or reset signal end.

17. a kind of display device, which is characterized in that including the gate driving circuit described in claim 15 or 16.