CN109559706A - Display driver circuit and display device - Google Patents
Display driver circuit and display device Download PDFInfo
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- CN109559706A CN109559706A CN201910088286.6A CN201910088286A CN109559706A CN 109559706 A CN109559706 A CN 109559706A CN 201910088286 A CN201910088286 A CN 201910088286A CN 109559706 A CN109559706 A CN 109559706A
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- 238000004134 energy conservation Methods 0.000 abstract description 6
- 230000001737 promoting effect Effects 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 description 53
- 239000004973 liquid crystal related substance Substances 0.000 description 16
- 239000010408 film Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
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- 238000005516 engineering process Methods 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 3
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- 239000013078 crystal Substances 0.000 description 1
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- 238000002834 transmittance Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention provides a kind of display driver circuit and display devices.The display driver circuit includes gate driving circuit and the spaced scan line of more parallel rows with gate driving circuit electric connection, the gate driving circuit includes multistage drive element of the grid, wherein each odd level drive element of the grid is cascaded, and even level drive element of the grid is cascaded；By the way that every level-one GOA unit two horizontal scanning lines of corresponding scanning are arranged, the GOA unit of odd level and the GOA unit of even level alternately scan, and the working time of every level-one GOA unit is enabled to halve, to reduce product power consumption, extend life of product, the green energy conservation for promoting product is horizontal.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of display driver circuit and display devices.
Background technique
Liquid crystal display (Liquid Crystal Display, LCD) has thin fuselage, power saving, radiationless etc. numerous excellent
Point, is widely used.Such as: LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen
Curtain or laptop screen etc., occupy an leading position in flat display field.
Liquid crystal display on existing market is largely backlight liquid crystal display comprising liquid crystal display panel and back
Optical mode group (backlight module).The working principle of liquid crystal display panel is in thin-film transistor array base-plate (Thin
Film Transistor Array Substrate, TFT Array Substrate) and colored filter substrate (Color
Filter, CF) between pour into liquid crystal molecule, and apply driving voltage on two plate bases to control the rotation side of liquid crystal molecule
To, by the light refraction of backlight module come out generate picture.
Active matrix liquid crystal display device (Active Matrix Liquid Crystal Display, AMLCD) is mesh
Preceding most common liquid crystal display device, the active matrix liquid crystal display device include multiple pixels, and each pixel has one
Thin film transistor (TFT) (Thin Film Transistor, TFT), the grid of the TFT is connected to horizontally extending scan line,
Drain electrode is connected to the data line extended in the vertical direction, and the source electrode of the TFT is connected to corresponding pixel electrode.If in level
Apply enough positive voltages in certain scan line in direction, then all TFT being connected in this scan line can be made to open, it will
In the voltage data signal writing pixel electrode loaded on data line, controls the light transmittance of different liquid crystal and then reach control color
Color effect.
The driving (i.e. gate driving) of current active liquid crystal display panel horizontal scanning line is mainly by external integrated electricity
Road (Integrated Circuit, IC) is completed, and external IC can control the charging step by step of horizontal scanning lines at different levels and put
Electricity.And GOA technology (Gate Driver on Array) i.e. array substrate row actuation techniques, it can be with liquid crystal display panel
The driving circuit of horizontal scanning line is produced on the substrate around viewing area by original processing procedure, makes it to substitute external IC to complete
The driving of horizontal scanning line.GOA technology can be reduced welding (bonding) process of external IC, has an opportunity to promote production capacity and reduce
Product cost, and liquid crystal display panel can be made to be more suitable for making the display product of narrow frame or Rimless.
Existing gate driving circuit generally includes cascade multistage drive element of the grid, and scanning mode is the drive of level-one grid
Moving cell scans a horizontal scanning line, and in each vertical interval, all drive element of the grid are required to participate in scanning, this
The power consumption of the gate driving circuit of scanning mode is larger, the longevity of service of every level-one drive element of the grid, and loss is big, Wu Faman
The product standard of sufficient green energy conservation.
Summary of the invention
The purpose of the present invention is to provide a kind of display driver circuits, can reduce product power consumption, extend life of product, mention
The green energy conservation for rising product is horizontal.
The present invention also provides a kind of display devices, can reduce product power consumption, extend life of product, promote the green of product
Energy-saving horizontal.
To achieve the above object, the present invention provides a kind of display driver circuit, including gate driving circuit and with it is described
The spaced scan line of more parallel rows that gate driving circuit is electrically connected, the gate driving circuit include that multistage grid drives
Moving cell, wherein each odd level drive element of the grid is cascaded, even level drive element of the grid is cascaded；
It is a drive element of the grid group per adjacent two-stage drive element of the grid, each drive element of the grid group is corresponding
The adjacent scan line of two rows, two-stage drive element of the grid in the same drive element of the grid group with the drive element of the grid group
Corresponding two horizontal scanning line is electrically connected；
When driving, the drive element of the grid of odd level and the drive element of the grid of even level are handed over according to preset switching cycle
Temporary substitute is made；When the drive element of the grid work of odd level, the drive element of the grid of odd level receives first group of high frequency clock signal,
And scanning signal is generated using first group of high frequency clock signal, each horizontal scanning line is scanned；The gate driving list of even level
When member work, the drive element of the grid of even level receives second group of high frequency clock signal, and utilizes second group of high frequency clock signal
Scanning signal is generated, each horizontal scanning line is scanned.
First group of high frequency clock signal includes the first high frequency clock signal, third high frequency clock signal and the 5th high frequency
Clock signal；
Second group of high frequency clock signal includes the second high frequency clock signal, the 4th high frequency clock signal and the 6th high frequency
Clock signal；
When the rising edge of first high frequency clock signal, third high frequency clock signal and the 5th high frequency clock signal generates
Between be successively spaced a preset delay time；Second high frequency clock signal, the 4th high frequency clock signal and the 6th high frequency
The waveform of clock signal it is corresponding respectively with the first high frequency clock signal, third high frequency clock signal and the 5th high frequency clock signal
Waveform is identical；
If n is positive integer, 6n-5 grades of drive element of the grid, 6n-4 grades of drive element of the grid, 6n-3 grades of grids are driven
Moving cell, 6n-2 grades of drive element of the grid, 6n-1 grades of drive element of the grid and 6n grades of drive element of the grid receive respectively
First high frequency clock signal, the second high frequency clock signal, third high frequency clock signal, the 4th high frequency clock signal, the 5th high frequency
Clock signal and the 6th high frequency clock signal.
First group of high frequency clock signal includes the first high frequency clock signal, third high frequency clock signal, the 5th high frequency
Clock signal and the 7th high frequency clock signal；
Second group of high frequency clock signal includes the second high frequency clock signal, the 4th high frequency clock signal, the 6th high frequency
Clock signal and the 8th clock signal；
First high frequency clock signal, third high frequency clock signal, the 5th high frequency clock signal and the 7th high frequency clock
The rising edge generation time of signal is successively spaced a preset delay time；Second high frequency clock signal, the 4th high frequency
The waveform of clock signal, the 6th high frequency clock signal and the 8th high frequency clock signal it is corresponding respectively with the first high frequency clock signal,
The waveform of third high frequency clock signal, the 5th high frequency clock signal and the 7th high frequency clock signal is identical；
If n is positive integer, 8n-7 grades of drive element of the grid, 8n-6 grades of drive element of the grid, 8n-5 grades of grids are driven
Moving cell, 8n-4 grades of drive element of the grid, 8n-3 grades of drive element of the grid, 8n-2 grades of drive element of the grid, 8n-1
Grade drive element of the grid and 8n grades of drive element of the grid receive respectively the first high frequency clock signal, the second high frequency clock signal,
Third high frequency clock signal, the 4th high frequency clock signal, the 5th high frequency clock signal, the 6th high frequency clock signal, the 7th high frequency
Clock signal and the 8th high frequency clock signal.
When the drive element of the grid work of odd level, the drive element of the grid of the first order also receives the first enabling signal, uses
In driving odd level drive element of the grid starting scanning；
When the drive element of the grid work of even level, the drive element of the grid of the second level also receives the second enabling signal, uses
In driving even level drive element of the grid starting scanning.
Every level-one drive element of the grid also receives the first low-frequency clock signal and the second low-frequency clock signal, at this
The closed state of this grade of drive element of the grid is maintained during the grade non-output of drive element of the grid.
When the work of the drive element of the grid of the drive element of the grid and even level of odd level is at interval of 80 to 120 frame scan
Between switch it is primary.
The work of the drive element of the grid of the drive element of the grid and even level of odd level is cut at interval of 100 vertical intervals
It changes primary.
The display driver circuit further includes multiple pixel units of array arrangement, each horizontal scanning line correspondence and a line
Pixel unit is electrically connected.
The gate driving circuit is GOA circuit.
The present invention also provides a kind of display devices, including above-mentioned display driver circuit.
Beneficial effects of the present invention: the present invention provides a kind of display driver circuit, including gate driving circuit and with institute
The spaced scan line of more parallel rows of gate driving circuit electric connection is stated, the gate driving circuit includes multistage grid
Driving unit, wherein each odd level drive element of the grid is cascaded, even level drive element of the grid is cascaded；By setting
Every level-one GOA unit two horizontal scanning lines of corresponding scanning are set, the GOA unit of odd level and the GOA unit of even level are alternately swept
It retouches, the working time of every level-one GOA unit is enabled to halve, to reduce product power consumption, extend life of product, promote product
Green energy conservation it is horizontal.The present invention also provides a kind of display devices, can reduce product power consumption, extend life of product, are promoted and are produced
The green energy conservation of product is horizontal.
Detailed description of the invention
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with of the invention detailed
Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
In attached drawing,
Fig. 1 is the schematic diagram of the first embodiment of display driver circuit of the invention；
Fig. 2 is the waveform diagram of the first embodiment of display driver circuit of the invention；
Fig. 3 is the circuit diagram of the drive element of the grid of display driver circuit of the invention；
Fig. 4 is the schematic diagram of the second embodiment of display driver circuit of the invention.
Specific embodiment
Further to illustrate technological means and its effect adopted by the present invention, below in conjunction with preferred implementation of the invention
Example and its attached drawing are described in detail.
Referring to Fig. 1, the present invention provides a kind of display driver circuit, including gate driving circuit 1 and driven with the grid
The spaced scan line 2 of more parallel rows that dynamic circuit 1 is electrically connected, the gate driving circuit 2 include multistage gate driving
Unit 21, wherein each odd level drive element of the grid 21 is cascaded, even level drive element of the grid 21 is cascaded；
It is a drive element of the grid group 210, each drive element of the grid per adjacent two-stage drive element of the grid 21
The adjacent scan line 2 of corresponding two rows of group 210, two-stage drive element of the grid 21 in the same drive element of the grid group 210 with
Corresponding two horizontal scanning line 2 of drive element of the grid group 210 is electrically connected.
It should be noted that display driver circuit of the invention is in driving, the drive element of the grid 21 of odd level and even
The drive element of the grid 21 of several levels is worked alternatively according to preset switching cycle；When the drive element of the grid 21 of odd level works,
The drive element of the grid 21 of odd level receives first group of high frequency clock signal, and generates scanning using first group of high frequency clock signal
Signal is scanned each horizontal scanning line 2；When the drive element of the grid 21 of even level works, the drive element of the grid of even level
21 receive second group of high frequency clock signal, and generate scanning signal using second group of high frequency clock signal, to each horizontal scanning line 2 into
Row scanning.
Further, when the drive element of the grid 21 of odd level works, the drive element of the grid 21 of the first order also receives the
One enabling signal STV1, for driving the starting scanning of odd level drive element of the grid 21；
When the drive element of the grid 21 of even level works, the drive element of the grid 21 of the second level also receives the second enabling signal
STV2, for driving the starting scanning of even level drive element of the grid 21.
Further, when every level-one drive element of the grid 21 also receives the first low-frequency clock signal LC1 and the second low frequency
Clock signal LC2, for maintaining the closed state of this grade of drive element of the grid 21 during this grade of non-output of drive element of the grid 21.
Preferably, the work of the drive element of the grid 21 of the drive element of the grid 21 and even level of odd level at interval of 80 to
The switching of 120 vertical intervals is primary.It is highly preferred that the drive element of the grid 21 of odd level and the drive element of the grid 21 of even level
Work switch at interval of 100 vertical intervals it is primary.
Further, the display driver circuit further includes multiple pixel units 3 of array arrangement, each horizontal scanning line 2
It is corresponding to be electrically connected with one-row pixels unit 3.
Preferably, the gate driving circuit 1 is GOA circuit.
For example, as shown in Figure 1, in the first embodiment of the present invention, first group of high frequency clock signal includes
First high frequency clock signal CK1, third high frequency clock signal CK3 and the 5th high frequency clock signal CK5；When second group of high frequency
Clock signal includes the second high frequency clock signal CK2, the 4th high frequency clock signal CK4 and the 6th high frequency clock signal CK6；Described
The rising edge generation time of one high frequency clock signal CK1, third high frequency clock signal CK3 and the 5th high frequency clock signal CK5 according to
One preset delay time of minor tick；The second high frequency clock signal CK2, the 4th high frequency clock signal CK4 and the 6th are high
The waveform correspondence of frequency clock signal CK6 is high with the first high frequency clock signal CK1, third high frequency clock signal CK3 and the 5th respectively
The waveform of frequency clock signal CK5 is identical；
If n is positive integer, 6n-5 grades of drive element of the grid, 6n-4 grades of drive element of the grid, 6n-3 grades of grids are driven
Moving cell, 6n-2 grades of drive element of the grid, 6n-1 grades of drive element of the grid and 6n grades of drive element of the grid receive respectively
First high frequency clock signal CK1, the second high frequency clock signal CK2, third high frequency clock signal CK3, the 4th high frequency clock signal
CK4, the 5th high frequency clock signal CK5 and the 6th high frequency clock signal CK6.
Further, as shown in Fig. 2 and Fig. 1, the course of work of above-mentioned first embodiment are as follows: firstly, the first enabling signal
STV1 provides high level pulse, and the GOA unit 21 that the second enabling signal STV2 does not provide high level pulse odd level is started to work,
The GOA unit 21 of even level does not work, and when the GOA unit 21 of odd level works, first order GOA unit 21 first receives the first high frequency
Clock signal CK1 generates first scanning signal, and first scanning signal is output to first scan line L1 and Article 2
First scan line L1 and Article 2 scan line L2 are scanned in scan line L2, third level GOA unit 21 then receives
Three high frequency clock signal CK3, generate second scanning signal, and by second scanning signal be output to Article 3 scan line L3 and
Article 3 scan line L3 and Article 4 scan line L4 are scanned in Article 4 scan line L4, level V GOA unit 21 connects again
The 5th high frequency clock signal CK5 is received, generates third scanning signal, and third scanning signal is output to Article 5 scan line
Article 5 scan line L5 and Article 6 scan line L6 are scanned in L5 and Article 6 scan line L6, and so on until last
The GOA unit 21 of one odd level completes a frame scan, after the GOA unit 21 of odd level completes 100 frame scans, from the 101st
Frame starts, and the second enabling signal STV2 provides high level pulse, and the first enabling signal STV1 does not provide high level pulse, even level
GOA unit 21 start to work, the GOA unit 21 of odd level do not work, when the GOA unit 21 of even level works, second level GOA
Unit 21 first receives the second high frequency clock signal CK2, generates first scanning signal, and first scanning signal is output to
First scan line L1 and Article 2 scan line L2 are scanned in one scan line L1 and Article 2 scan line L2, the fourth stage
GOA unit 21 then receives the 4th high frequency clock signal CK4, generates second scanning signal, and second scanning signal is defeated
Article 3 scan line L3 and Article 4 scan line L4 are scanned into Article 3 scan line L3 and Article 4 scan line L4 out,
6th grade of GOA unit 21 receives the 6th high frequency clock signal CK6 again, generates third scanning signal, and third is scanned and is believed
It number is output in Article 5 scan line L5 and Article 6 scan line L6 to Article 5 scan line L5 and Article 6 scan line L6 progress
Scanning, and so on until the GOA unit 21 of the last one odd level, completes a frame scan, the GOA unit 21 of even level is again complete
After 100 frame scans, since the 301st frame, the GOA unit 21 of odd level is started to work again, and even level GOA unit 21 stops
Work, subsequent continuous cycle alternation work, thus, the present invention corresponds to two horizontal scanning lines of scanning by the way that every level-one GOA unit is arranged,
The GOA unit of odd level and the GOA unit of even level alternately scan, and enable to the working time of every level-one GOA unit
Halve, to reduce product power consumption, extend life of product, the green energy conservation for promoting product is horizontal
In addition, as shown in figure 4, first group of high frequency clock signal includes first in the second embodiment of the present invention
High frequency clock signal CK1, third high frequency clock signal CK3, the 5th high frequency clock signal CK5 and the 7th high frequency clock signal CK7；
When second group of high frequency clock signal includes the second high frequency clock signal CK2, the 4th high frequency clock signal CK4, six high frequencies
Clock signal CK6 and the 8th clock signal CK8；
The first high frequency clock signal CK1, third high frequency clock signal CK3, the 5th high frequency clock signal CK5 and the 7th
The rising edge generation time of high frequency clock signal CK7 is successively spaced a preset delay time；The second high frequency clock letter
Number CK2, the 4th high frequency clock signal CK4, the waveform of the 6th high frequency clock signal CK6 and the 8th high frequency clock signal CK8 are corresponding
When respectively with the first high frequency clock signal CK1, third high frequency clock signal CK3, the 5th high frequency clock signal CK5 and seven high frequencies
The waveform of clock signal CK7 is identical；
If n is positive integer, 8n-7 grades of drive element of the grid, 8n-6 grades of drive element of the grid, 8n-5 grades of grids are driven
Moving cell, 8n-4 grades of drive element of the grid, 8n-3 grades of drive element of the grid, 8n-2 grades of drive element of the grid, 8n-1
Grade drive element of the grid and 8n grades of drive element of the grid receive the first high frequency clock signal CK1, the second high frequency clock letter respectively
When number CK2, third high frequency clock signal CK3, the 4th high frequency clock signal CK4, the 5th high frequency clock signal CK5, six high frequencies
Clock signal CK6, the 7th high frequency clock signal CK7 and the 8th high frequency clock signal CK8.
Specifically, the course of work of the second embodiment is identical with the first embodiment, only the number of high frequency clock signal
Amount changes, and details are not described herein again.
Further, in other embodiments of the invention, first group of high frequency clock signal and second group of high frequency clock letter
The quantity of number high frequency clock signal for including can also be other quantity, such as be 2 or be 6, it is only necessary to guarantee the
The quantity for the high frequency clock signal for including in one group of high frequency clock signal and second group of high frequency clock signal is equal, and waveform is one by one
Correspondence is identical.
Specifically, in some embodiments of the invention, if M is positive integer, M grades of drive element of the grid include: first
Thin film transistor (TFT) T1, the second thin film transistor (TFT) T2, third thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4, the 5th film crystal
Pipe T5, the 6th thin film transistor (TFT) T6, the 7th thin film transistor (TFT) T7, the 8th thin film transistor (TFT) T8, the 9th thin film transistor (TFT) T9, the tenth
Thin film transistor (TFT) T10, the 11st thin film transistor (TFT) T11, the 12nd thin film transistor (TFT) T12, the 13rd thin film transistor (TFT) T13,
14 thin film transistor (TFT) T14, the 15th thin film transistor (TFT) T15, the 16th thin film transistor (TFT) T16 and capacitor C1；
The grid and source electrode of the first film transistor T1 receive the scanning signal G of M-2 grades of drive element of the grid
(M-2), drain electrode is electrically connected first node Q (M)；
The grid of the second thin film transistor (TFT) T2 is electrically connected first node Q (M), and source electrode receives high frequency clock signal
CK, drain electrode output scanning signal G (M)；
The grid of the third thin film transistor (TFT) T3 receives the scanning signal G (M+2) of M+2 grades of drive element of the grid, source
Pole is electrically connected first node Q (M), and drain electrode receives low potential VSS；
The grid of the 4th thin film transistor (TFT) T4 receives the scanning signal G (M+2) of M+2 grades of drive element of the grid, source
Pole is electrically connected the drain electrode of the second thin film transistor (TFT) T2, and drain electrode receives low potential VSS；
The grid of the 5th thin film transistor (TFT) T5 is electrically connected the drain electrode of the tenth thin film transistor (TFT) T10, and source electrode electrically connects
It connects first node Q (M), drain electrode receives low potential VSS；
The grid of the 6th thin film transistor (TFT) T6 is electrically connected the drain electrode of the tenth thin film transistor (TFT) T10, and source electrode electrically connects
The drain electrode of the second thin film transistor (TFT) T2 is connect, drain electrode receives low potential VSS；
The grid and source electrode of the 7th thin film transistor (TFT) T7 receives the first low-frequency clock signal LC1, and drain electrode electrically connects
Connect the grid of the tenth thin film transistor (TFT) T10；
The grid of the 8th thin film transistor (TFT) T8 is electrically connected first node Q (M), and it is brilliant that source electrode is electrically connected the tenth film
The grid of body pipe T10, drain electrode receive low potential VSS；
The grid of the 9th thin film transistor (TFT) T9 is electrically connected first node Q (M), and it is brilliant that source electrode is electrically connected the tenth film
The drain electrode of body pipe T10, drain electrode receive low potential VSS；
The source electrode of the tenth thin film transistor (TFT) T10 receives the first low-frequency clock signal LC1；
The grid of the 11st thin film transistor (TFT) T11 is electrically connected the drain electrode of the 16th thin film transistor (TFT) T16, source electrode electricity
Property connection first node Q (M), drain electrode receive low potential VSS；
The grid of the 12nd thin film transistor (TFT) T12 is electrically connected the drain electrode of the 16th thin film transistor (TFT) T16, source electrode electricity
Property connection the second thin film transistor (TFT) T2 drain electrode, drain electrode receive low potential VSS；
The grid and source electrode of the 13rd thin film transistor (TFT) T13 receives the second low-frequency clock signal LC2, and drain electrode is electrically
Connect the grid of the 16th thin film transistor (TFT) T16；
The grid of the 14th thin film transistor (TFT) T14 is electrically connected first node Q (M), and source electrode is electrically connected the 16th
The grid of thin film transistor (TFT) T16, drain electrode receive low potential VSS；
The grid of the 15th thin film transistor (TFT) T15 is electrically connected first node Q (M), and source electrode is electrically connected the 16th
The drain electrode of thin film transistor (TFT) T16, drain electrode receive low potential VSS；
The source electrode of 16th thin film transistor (TFT) 16 receives the second low-frequency clock signal LC2；
The first end of the capacitor C1 is electrically connected first node Q (M), and second end is electrically connected the second thin film transistor (TFT) T2
Drain electrode.
Specifically, it corresponds in the first embodiment of the present invention, as shown in figure 3, when M is odd number, the gate driving list
High frequency clock signal CK in member 21 is the first high frequency clock signal CK1, third high frequency clock signal CK3 and the 5th high frequency clock
One in signal CK, when M is even number, when the high frequency clock signal CK in the drive element of the grid 21 is second high frequency
One in clock signal CK2, the 4th high frequency clock signal CK4 and the 6th high frequency clock signal CK6.
Specifically, it corresponds in the second embodiment of the present invention, as shown in figure 3, when M is odd number, the gate driving list
High frequency clock signal CK in member 21 is the first high frequency clock signal CK1, third high frequency clock signal CK3, the 5th high frequency clock
One in signal CK5 and the 7th high frequency clock signal CK7, the high frequency clock when M is even number, in the drive element of the grid 21
Signal CK is the second high frequency clock signal CK2, the 4th high frequency clock signal CK4, the 6th high frequency clock signal CK6 and the 8th
One in high frequency clock signal CK8.
Specifically, it corresponds in embodiment shown in Fig. 3, in order to guarantee the normal work of gate driving circuit, the first order
The source electrode and drain electrode of first film transistor T1 in drive element of the grid 21 receives the first enabling signal STV1, second level grid
The source electrode and drain electrode of first film transistor T1 in driving unit 21 receives the second enabling signal STV2, the last one even level
The grid of the third thin film transistor (TFT) T3 and the 4th thin film transistor (TFT) T4 of GOA unit 21 receive the second enabling signal STV2, finally
The grid of the third thin film transistor (TFT) T3 and the 4th thin film transistor (TFT) T4 of one odd level GOA unit 21 receive the first enabling signal
STV1, so that the drive element of the grid 21 smoothly can start and close.
Further, the course of work of drive element of the grid 21 as shown in Figure 3 are as follows: firstly, M-2 grades of gate driving lists
The scanning signal G (M-2) of member is high potential, and first film transistor T1 is opened, and is charged for first node Q (M), so that second is thin
Film transistor T2 is opened, and high frequency clock signal CK exports scanning signal G (M) via the drain electrode of the second thin film transistor (TFT) T2, then,
M+2 grades of drive element of the grid scanning signal G (M+2) are high potential, and third and fourth thin film transistor (TFT) T3, T4 is opened, drop-down
First node Q (M) and scanning signal G (M) to low potential VSS, finally, the first low-frequency clock signal LC1 and the second high frequency clock
Signal LC2 is worked alternatively, so that first node Q (M) and scanning signal G (M) maintain low potential VSS.
In addition, the present invention also provides a kind of display device, including above-mentioned display driver circuit.
In conclusion the present invention provides a kind of display driver circuit, including gate driving circuit and driven with the grid
The spaced scan line of more parallel rows that dynamic circuit is electrically connected, the gate driving circuit include multistage gate driving list
Member, wherein each odd level drive element of the grid is cascaded, even level drive element of the grid is cascaded；It is each by being arranged
Grade GOA unit two horizontal scanning lines of corresponding scanning, the GOA unit of odd level and the GOA unit of even level alternately scan, can
So that the working time of every level-one GOA unit halves, to reduce product power consumption, extends life of product, promote the green of product
Energy-saving horizontal.The present invention also provides a kind of display devices, can reduce product power consumption, extend life of product, promote the green of product
Color energy-saving horizontal.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology
Other various corresponding changes and modifications are made in design, and all these change and modification all should belong to the claims in the present invention
Protection scope.
Claims (10)
1. a kind of display driver circuit, which is characterized in that including gate driving circuit (1) and with the gate driving circuit (1)
The spaced scan line of the more parallel rows of electric connection (2), the gate driving circuit (1) include multistage drive element of the grid
(21), wherein each odd level drive element of the grid (21) successively cascades, each even level drive element of the grid (21) successively grade
Connection；
It is a drive element of the grid group (210), each drive element of the grid per adjacent two-stage drive element of the grid (21)
Group (210) corresponds to the adjacent scan line (2) of two rows, the two-stage drive element of the grid in the same drive element of the grid group (210)
(21) two horizontal scanning line (2) corresponding with drive element of the grid group (210) is electrically connected；
When driving, the drive element of the grid (21) of odd level and the drive element of the grid (21) of even level are according to preset switching week
Phase works alternatively；When drive element of the grid (21) work of odd level, the drive element of the grid (21) of odd level receives first group
High frequency clock signal, and scanning signal is generated using first group of high frequency clock signal, each horizontal scanning line (2) is scanned；It is even
When drive element of the grid (21) work of several levels, the drive element of the grid (21) of even level receives second group of high frequency clock signal,
And scanning signal is generated using second group of high frequency clock signal, each horizontal scanning line (2) is scanned.
2. display driver circuit as described in claim 1, which is characterized in that first group of high frequency clock signal includes first
High frequency clock signal (CK1), third high frequency clock signal (CK3) and the 5th high frequency clock signal (CK5)；
Second group of high frequency clock signal includes the second high frequency clock signal (CK2), the 4th high frequency clock signal (CK4) and the
Six high frequency clock signals (CK6)；
First high frequency clock signal (CK1), third high frequency clock signal (CK3) and the 5th high frequency clock signal (CK5)
Rising edge generation time is successively spaced a preset delay time；When second high frequency clock signal (CK2), four high frequencies
The waveform of clock signal (CK4) and the 6th high frequency clock signal (CK6) it is corresponding respectively with the first high frequency clock signal (CK1), third
The waveform of high frequency clock signal (CK3) and the 5th high frequency clock signal (CK5) is identical；
If n is positive integer, 6n-5 grades of drive element of the grid, 6n-4 grades of drive element of the grid, 6n-3 grades of gate driving lists
Member, 6n-2 grades of drive element of the grid, 6n-1 grades of drive element of the grid and 6n grades of drive element of the grid receive first respectively
High frequency clock signal (CK1), the second high frequency clock signal (CK2), third high frequency clock signal (CK3), the 4th high frequency clock letter
Number (CK4), the 5th high frequency clock signal (CK5) and the 6th high frequency clock signal (CK6).
3. display driver circuit as described in claim 1, which is characterized in that first group of high frequency clock signal includes first
High frequency clock signal (CK1), third high frequency clock signal (CK3), the 5th high frequency clock signal (CK5) and the 7th high frequency clock letter
Number (CK7)；
Second group of high frequency clock signal includes the second high frequency clock signal (CK2), the 4th high frequency clock signal (CK4), the
Six high frequency clock signals (CK6) and the 8th clock signal (CK8)；
First high frequency clock signal (CK1), third high frequency clock signal (CK3), the 5th high frequency clock signal (CK5) and
The rising edge generation time of seven high frequency clock signals (CK7) is successively spaced a preset delay time；When second high frequency
Clock signal (CK2), the 4th high frequency clock signal (CK4), the 6th high frequency clock signal (CK6) and the 8th high frequency clock signal
(CK8) waveform it is corresponding respectively with the first high frequency clock signal (CK1), third high frequency clock signal (CK3), the 5th high frequency clock
The waveform of signal (CK5) and the 7th high frequency clock signal (CK7) is identical；
If n is positive integer, 8n-7 grades of drive element of the grid, 8n-6 grades of drive element of the grid, 8n-5 grades of gate driving lists
Member, 8n-4 grades of drive element of the grid, 8n-3 grades of drive element of the grid, 8n-2 grades of drive element of the grid, 8n-1 grades of grid
Pole driving unit and 8n grades of drive element of the grid receive the first high frequency clock signal (CK1), the second high frequency clock signal respectively
(CK2), third high frequency clock signal (CK3), the 4th high frequency clock signal (CK4), the 5th high frequency clock signal (CK5), the 6th
High frequency clock signal (CK6), the 7th high frequency clock signal (CK7) and the 8th high frequency clock signal (CK8).
4. display driver circuit as described in claim 1, which is characterized in that the drive element of the grid (21) of odd level works
When, the drive element of the grid (21) of the first order also receives the first enabling signal (STV1), for driving odd level gate driving list
First (21) starting scanning；
When drive element of the grid (21) work of even level, the drive element of the grid (21) of the second level also receives the second enabling signal
(STV2), for driving even level drive element of the grid (21) starting scanning.
5. display driver circuit as described in claim 1, which is characterized in that every level-one drive element of the grid (21) also receives
First low-frequency clock signal (LC1) and the second low-frequency clock signal (LC2), in this grade of drive element of the grid (21) non-output
Period maintains the closed state of this grade of drive element of the grid (21).
6. display driver circuit as described in claim 1, which is characterized in that the drive element of the grid (21) and even number of odd level
The work of the drive element of the grid (21) of grade switches primary at interval of 80 to 120 vertical intervals.
7. display driver circuit as claimed in claim 6, which is characterized in that the drive element of the grid (21) and even number of odd level
The work of the drive element of the grid (21) of grade switches primary at interval of 100 vertical intervals.
8. display driver circuit as described in claim 1, which is characterized in that further include multiple pixel units of array arrangement
(3), each horizontal scanning line (2) is corresponding is electrically connected with one-row pixels unit (3).
9. display driver circuit as described in claim 1, which is characterized in that the gate driving circuit (1) is GOA circuit.
10. a kind of display device, which is characterized in that including display driver circuit as described in any one of claim 1 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910088286.6A CN109559706B (en) | 2019-01-29 | 2019-01-29 | Display driving circuit and display device |
| PCT/CN2019/085769 WO2020155453A1 (en) | 2019-01-29 | 2019-05-07 | Display driving circuit and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910088286.6A CN109559706B (en) | 2019-01-29 | 2019-01-29 | Display driving circuit and display device |
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| CN109559706B CN109559706B (en) | 2020-08-11 |
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| CN201910088286.6A Active CN109559706B (en) | 2019-01-29 | 2019-01-29 | Display driving circuit and display device |
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| WO (1) | WO2020155453A1 (en) |
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| CN111445828A (en) * | 2020-04-20 | 2020-07-24 | 深圳市华星光电半导体显示技术有限公司 | Display driving circuit and display device |
| WO2020155453A1 (en) * | 2019-01-29 | 2020-08-06 | 深圳市华星光电技术有限公司 | Display driving circuit and display device |
| CN111883075A (en) * | 2020-07-28 | 2020-11-03 | 北海惠科光电技术有限公司 | Panel driving circuit, method and display device |
| CN112071272A (en) * | 2020-09-14 | 2020-12-11 | 武汉华星光电半导体显示技术有限公司 | Light-emitting control circuit and display panel |
| CN112365857A (en) * | 2020-12-04 | 2021-02-12 | 深圳市华星光电半导体显示技术有限公司 | Drive circuit, display panel and display device |
| CN113257171A (en) * | 2021-06-17 | 2021-08-13 | 北京京东方显示技术有限公司 | Grid driving circuit and method, display panel and time sequence controller |
| US11158228B1 (en) | 2020-04-20 | 2021-10-26 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display driving circuit and display device |
| CN114927113A (en) * | 2022-05-31 | 2022-08-19 | 长沙惠科光电有限公司 | Scanning drive circuit and display panel |
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| WO2020155453A1 (en) * | 2019-01-29 | 2020-08-06 | 深圳市华星光电技术有限公司 | Display driving circuit and display device |
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| CN112365857A (en) * | 2020-12-04 | 2021-02-12 | 深圳市华星光电半导体显示技术有限公司 | Drive circuit, display panel and display device |
| CN113257171A (en) * | 2021-06-17 | 2021-08-13 | 北京京东方显示技术有限公司 | Grid driving circuit and method, display panel and time sequence controller |
| CN114927113A (en) * | 2022-05-31 | 2022-08-19 | 长沙惠科光电有限公司 | Scanning drive circuit and display panel |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2020155453A1 (en) | 2020-08-06 |
| CN109559706B (en) | 2020-08-11 |
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