CN207458046U - A kind of programmable logic device and its internal logic function module time-sharing multiplex circuit - Google Patents
A kind of programmable logic device and its internal logic function module time-sharing multiplex circuit Download PDFInfo
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Abstract
The utility model provides a kind of programmable logic device and its internal logic function module time-sharing multiplex circuit, and signal selects an output circuit after logic functional block, the serial logic signal that the two is included inside programmable logic device select an input circuit and processing；Serial logic signal, which selects an input unit, includes m the first multiple selector and the n signal receiving interfaces for being used to receive serial logic signal；Signal, which selects an output circuit, after processing includes the n signal output interface and n that are used cooperatively with above-mentioned n signal receiving interface the second multiple selector.Serial logic signal, which selects an input circuit and reaches the logic functional block for selecting an input signal every time, to be handled, and signal is selected an output circuit and exported for the output signal of logic functional block to be selected a corresponding signal output interface every time after processing.This scheme reduces the wastes of the hardware resource of Design for Programmable Logic.
Description
Technical field
The utility model is related to programmable logic device fields, are specifically a kind of programmable logic device and its internal logic
Function module time-sharing multiplex circuit during for incoming serial logic in the programmable logic device, is realized to its internal logic work(
The time-sharing multiplex of energy module.
Background technology
The performance of programmable logic device (CPLD) (referred to as " CPLD ") and programmable logic device FPGA (referred to as " FPGA ")
Index mainly includes two aspect of speed and hardware resource, for this purpose, speed and resource are taken into account in the design, so that its performance reaches
It is optimal.
Wherein, to improve the speed of service of system, in CPLD designs and FPGA design, through frequently with Parallel Design.To the greatest extent
Pipe Parallel Design can improve the speed of service of system, but practice have shown that, it is relatively large to the consumption of hardware resource.And CPLD and
FPGA is limited for the hardware resource of consumption.For this purpose, also frequently with serial design in CPLD designs and FPGA design.
But in existing serial design, designer is often directly multiple to same logic functional block when being designed
Exampleization causes the corresponding multiple identical logic functional blocks of generation on CPLD and FPGA hardware circuit, this still can be certain
Hardware resource waste is caused in degree, and then increases hardware cost.
For this purpose, the utility model provides a kind of programmable logic device and its internal logic function module time-sharing multiplex electricity
Road, for solving the problems, such as above-mentioned hardware resource waste.
Utility model content
Technical problem to be solved in the utility model is, for it is recorded in background technology the technical issues of, provide one
Kind programmable logic device and its internal logic function module time-sharing multiplex circuit, for reducing in Design for Programmable Logic
The waste of hardware resource.
In order to solve the above technical problems, the utility model provides a kind of programmable logic device internal logic function module
Time-sharing multiplex circuit including the logic functional block inside programmable logic device, further includes serial logic signal and selects an input
Signal selects an output circuit after circuit and processing, wherein：
Serial logic signal is selected an input unit and is believed including m the first multiple selector and n for receiving serial logic
Number signal receiving interface, m the first multiple selector are 1 grade of first multiple selector, 2 grade of first multiple selector, ┅, m
The first multiple selector of grade, n signal receiving interface is the 1st signal receiving interface, the 2nd signal receiving interface, ┅, the n-th signal
Receiving interface；1st signal receiving interface and the 2nd signal receiving interface two input terminals with 1 grade of first multiple selector respectively
It is connected, the output terminal and the 3rd signal receiving interface of 1 grade of first multiple selector two with 2 grade of first multiple selector respectively
Input terminal is connected, the output terminal and the 4th signal receiving interface of 2 grade of first multiple selector respectively with 3 grade of first multiple selector
Two input terminals be connected, the output terminal and the n-th signal receiving interface of ┅, m-1 the first multiple selector of grade respectively with m grades first
Two input terminals of multiple selector are connected, the output terminal of m the first multiple selector of grade and the input of the logic functional block
End is connected；
Signal, which selects an output circuit, after processing includes n signal being used cooperatively with above-mentioned n signal receiving interface
Output interface and n the second multiple selector, n signal output interface be the 1st signal output interface, the 2nd signal output interface,
┅, the n-th signal output interface, n the second multiple selector are 1 grade of second multiple selector, 2 grade of second multiple selector, ┅,
N the second multiple selector of grade；The input with above-mentioned each second multiple selector respectively of the output terminal of the logic functional block
End is connected；The output terminal of i the second multiple selector of grade respectively with the i-th signal output interface and i+1 the second multiple selector of grade
Another input terminal is connected, wherein 1≤i≤n-1, i ∈ Ν；The output terminal and the n-th signal output interface of n the second multiple selector of grade
It is connected；
The output terminal of the logic functional block also respectively with the Enable Pin of above-mentioned each first multiple selector and above-mentioned each
The Enable Pin of second multiple selector is connected；
Above-mentioned n=m+1 >=3, n ∈ Ν and m ∈ Ν；
The programmable logic device is CPLD or FPGA.
Wherein, the logic functional block is time delay module.
Wherein, above-mentioned first multiple selector uses alternative multiple selector and/or above-mentioned second multiple selector
Use alternative multiple selector.
Wherein, above-mentioned signal receiving interface is connect using GPIO interface and/or above-mentioned signal output interface using GPIO
Mouthful.
The utility model additionally provides a kind of programmable logic device, is inside integrated with programmable logic device as described above
Part internal logic function module time-sharing multiplex circuit.
In the programmable logic device, the programmable logic device internal logic function module time-sharing multiplex electricity
First multiple selector on road uses alternative multiple selector and/or the programmable logic device internal logic function
Second multiple selector of array signal processing circuit uses alternative multiple selector.
In the programmable logic device, the programmable logic device internal logic function module time-sharing multiplex electricity
The signal receiving interface on road is answered using GPIO interface and/or the programmable logic device internal logic function module timesharing
GPIO interface is used with the signal output interface of circuit.
Compared with prior art, the utility model has the advantage of：
(1) programmable logic device internal logic function module time-sharing multiplex circuit described in the utility model, including can
Signal selects output electricity after logic functional block, serial logic signal inside programmed logic device select an input circuit and processing
Road realizes programmable logic device internal logic function module time-sharing multiplex, and then can reduce programmable logic device and set
The waste of hardware resource in meter；
(2) programmable logic device described in the utility model is internally integrated in the programmable logic device
Portion's logic functional block time-sharing multiplex circuit, it may have reduce the effect of hardware resource waste.
It can be seen that the utility model is compared with prior art, there is substantive distinguishing features and progress, the beneficial effect implemented
Fruit is also obvious.
Description of the drawings
Fig. 1 is that the circuit of programmable logic device internal logic function module time-sharing multiplex circuit described in the utility model is former
Manage schematic diagram；
Fig. 2 is the circuit theory schematic diagram of logic functional block shown in Fig. 1.
Wherein：1 be 1 grade of first multiple selector, 2 be 2 grade of first multiple selector, 3 be 3 grade of first multiple selector, 4
It is logic functional block for 4 grade of first multiple selector, 5,6 be 1 grade of second multiple selector, and 7 be 2 grade of second multi-path choice
Device, 8 be 3 grade of second multiple selector, and 9 be 4 grade of second multiple selector, and 10 be 5 grade of second multiple selector, and 11 be addition
Device, 12 be the 3rd multiple selector, and 13 be register, and 14 be comparator, and 15 be the 4th multiple selector.
Specific embodiment
To make the technical solution of the utility model and advantage clearer, below in conjunction with attached drawing, to the utility model
Technical solution is clearly and completely described.
Fig. 1 is a kind of tool of programmable logic device internal logic function module time-sharing multiplex circuit described in present embodiment
Body embodiment.Bis- road server FPGA internal delay times modules of embodiment Wei Dui have carried out module and have shared that (i.e. timesharing is answered
With), i.e., the programmable logic device is programmable logic device FPGA (referred to as " FPGA ").In view of the programmable logic device
Part internal logic function module time-sharing multiplex circuit is only used for carrying out time-sharing multiplex to " serial order " logical gate in FPGA, because
This its do not interfere with the speed ability of FPGA.
In this embodiment, the programmable logic device internal logic function module time-sharing multiplex circuit, including
Signal selects an output circuit after logic functional block, serial logic signal inside FPGA select an input circuit and processing.It is described
Logic functional block be above-mentioned time delay module.Wherein, serial logic signal, which selects an input circuit, includes 5 for receiving serially
The signal receiving interface of logical signal and 4 the first multiple selector, it is defeated including 5 signals to select an output circuit for signal after processing
Outgoing interface and 5 the second multiple selector.4 the first multiple selector are 1 grade of first multiple selector, 2 grade of first multichannel choosing
Select device, 3 grade of first multiple selector and 4 grade of first multiple selector.5 signal receiving interfaces are the 1st signal receiving interface, the
2 signal receiving interfaces, the 3rd signal receiving interface, the 4th signal receiving interface and the 5th signal receiving interface.5 signal outputs connect
Mouth is the 1st signal output interface, the 2nd signal output interface, the 3rd signal output interface, the 4th signal output interface and the 5th signal
Output interface.5 the second multiple selector are 1 grade of second multiple selector, 2 grade of second multiple selector, 3 grade of second multichannel are selected
Select device, 4 grade of second multiple selector and 5 grade of second multiple selector.Each signal receiving interface and each signal output interface are adopted
Use GPIO interface.
Specifically, the 1st signal receiving interface and the 2nd signal receiving interface two with 1 grade of first multiple selector respectively
Input terminal is connected, the output terminal and the 3rd signal receiving interface of 1 grade of first multiple selector respectively with 2 grade of first multiple selector
Two input terminals be connected, the output terminal and the 4th signal receiving interface of 2 grade of first multiple selector respectively with 3 grade of first multichannel
Two input terminals of selector are connected, the output terminal and the 5th signal receiving interface of 3 grade of first multiple selector respectively with 4 grade
Two input terminals of one multiple selector are connected, the input terminal of the output terminal of 4 grade of first multiple selector and the time delay module
It is connected；An input terminal of the output terminal of the time delay module respectively with above-mentioned each second multiple selector is connected；1 grade of second multichannel
Another input terminal of the output terminal of selector respectively with the 1st signal output interface and 2 grade of second multiple selector is connected, 2 grade
Another input terminal of the output terminal of two multiple selector respectively with the 2nd signal output interface and 3 grade of second multiple selector is connected,
The output terminal of 3 grade of second multiple selector respectively with the 3rd signal output interface and another input terminal of 4 grade of second multiple selector
It is connected, the output terminal of 4 grade of second multiple selector is another with the 4th signal output interface and 5 grade of second multiple selector respectively
Input terminal is connected, and the output terminal of 5 grade of second multiple selector is connected with the 5th signal output interface；The output of the time delay module
The Enable Pin also respectively with the Enable Pin of above-mentioned each first multiple selector and above-mentioned each second multiple selector is held to be connected.
In the present embodiment, each first multiple selector and each second multiple selector use two
Select a multiple selector, the signal that when use receives each via its Enable Pin is enable signal.
When the utility model is used, five input signals are received by 5 signal receiving interfaces, five input signals
For the signal with preset particular serial sequential relationship, which is the input letter of the Postponement module
Number, under the action of above-mentioned 4 the first multiple selector, according to above-mentioned preset serial sequential relationship, serially sequentially
It inputs and is handled to select the Postponement module described in an input every time；After Postponement module carries out logical process, Postponement module
Each output signal it is defeated can be correspondingly outputting to corresponding signal under the enabled control of above-mentioned 5 the second multiple selector
Outgoing interface, so that subsequent conditioning circuit is continuing with.As it can be seen that the programmable logic device internal logic function mould described in present embodiment
Block time-sharing multiplex circuit realizes the time-sharing multiplex of the time delay module, avoids repetition of the time delay module inside FPGA and goes out
It is existing, reduce the waste of hardware resource.
Wherein, above-mentioned time delay module can be arbitrary available delay circuit in existing FPGA, and those skilled in the art can
One is selected according to actual conditions to be realized.In the present embodiment, the time delay module is as shown in Fig. 2, the time delay module bag
Include adder 11, comparator 14, the 3rd multiple selector 12, the 4th multiple selector 15 and register Reg, above-mentioned 4 grade first
The output terminal of multiple selector is connected with the Enable Pin of the 3rd multiple selector 12.3rd multiple selector 12 and the choosing of the 4th multichannel
It selects device 15 and uses alternative multiple selector.As shown in Fig. 2, when " Signal_in " is effective, i.e., above-mentioned 4 grade of first multichannel
When the output of the output terminal of selector is effective, time delay module work.Wherein, adder 11 is set for delay time, when not
When reaching delay value, current count value is carried out plus 1 operates；3rd multiple selector 12 by judge " Signal_in ", and
When judging that Signal_in is effective, the count value Counter_Num to register Reg after output plus 1；Register Reg is to receiving
It is above-mentioned plus 1 after count value Counter_Num deposited, and as current count value, and by the current count value
Adder 11 is fed back to as input and is sent to comparator 14；Comparator 14 receives above-mentioned current count value, and will receive
To current count value compared with the expected delay number Delay_Num received, if comparative result to be unequal, follows
Ring above-mentioned steps, if comparative result is the current count value Counter_Num and expectation count value Delay_Num being currently received
It is equal, then send enable signal to the Enable Pin of the 4th multiple selector 15；4th multiple selector 15 is according to received
Enable signal enables the signal Signal_out (PWRGD_dly) after output delay.Letter after the delay of the enabled output
Number Signal_out (PWRGD_dly) signals after above-mentioned processing select the selection index system of an output circuit, corresponding by right with it
The signal output interface output answered.
Wherein, in the present embodiment, used FPGA models are MAX V 5M1270ZF256I5, through software synthesis,
It is as shown in table 1 that module shares the front and rear hardware resource consumed, it is seen that sees and shares that (i.e. the timesharing of time delay module is answered by module
With) each main resource index all decreases.
1 different schemes resource service condition of table
Programmable logic device described in the utility model, a kind of embodiment are programmable logic device FPGA, should
Programmable logic device internal logic function module time-sharing multiplex electricity as described above is integrated in programmable logic device FPGA
Road.In view of those skilled in the art are according to the prior art and above-mentioned to programmable logic device internal logic function module timesharing
Literature record and the attached drawing signal of multiplex circuit, it is easy to programmable logic device FPGA can be realized, to simplify specification
Structure no longer provides the structure diagram of programmable logic device FPGA.In addition, in view of on programmable logic device FPGA
It is similary that there is reduction hardware money equipped with programmable logic device internal logic function module time-sharing multiplex circuit as described above
The advantages of waste in source.
In addition, programmable logic device described in the utility model, another embodiment can also be programmable patrols
Device CPLD is collected, programmable logic device internal logic function mould as described above is integrated in the programmable logic device (CPLD)
The programmable logic device of block time-sharing multiplex circuit can also be programmable logic device (CPLD).With above-mentioned programmable logic device
Analogously, those skilled in the art are according to the prior art and above-mentioned to programmable logic device internal logic function mould by FPGA
Literature record and the attached drawing signal of block time-sharing multiplex circuit, it is easy to can realize the programmable logic device (CPLD).
To sum up, programmable logic device internal logic function module time-sharing multiplex circuit described in the utility model and
The programmable logic device of the programmable logic device internal logic function module time-sharing multiplex circuit is integrated in it, can
One input circuit is selected by serial logic signal, a corresponding input signal is selected to reach the logic functional block every time and is carried out
Processing；And can an output circuit be selected by signal after processing, the signal corresponding selection phase that logic functional block is exported every time
The signal output interface answered is exported.It is patrolled it can be seen that the utility model avoids circuit corresponding to logic functional block programmable
It collects and repeats in device, reduce the waste of the hardware resource of Design for Programmable Logic.
Embodiment of above is only to illustrate the technical solution of the utility model, rather than its limitations；Although with reference to foregoing
The utility model is described in detail in embodiment, it will be understood by those of ordinary skill in the art that：It still can be with
It modifies to the technical solution recorded in foregoing each embodiment or equivalent substitution is carried out to which part technical characteristic；
And these modifications or replacement, the essence of appropriate technical solution is not made to depart from each embodiment technical solution of the utility model
Scope.
Claims (7)
1. a kind of programmable logic device internal logic function module time-sharing multiplex circuit, inside programmable logic device
Logic functional block, which is characterized in that further include signal after serial logic signal selects an input circuit and processing and select output electricity
Road, wherein：
Serial logic signal selects an input unit and is used to receive serial logic signal including m the first multiple selector and n
Signal receiving interface, m the first multiple selector are 1 grade of first multiple selector, 2 grade of first multiple selector, ┅, m grade the
One multiple selector, n signal receiving interface is the 1st signal receiving interface, the 2nd signal receiving interface, ┅, the n-th signal receive
Interface；1st signal receiving interface and the 2nd signal receiving interface are connected respectively with two input terminals of 1 grade of first multiple selector,
The output terminal and the 3rd signal receiving interface of 1 grade of first multiple selector two input terminals with 2 grade of first multiple selector respectively
It is connected, the output terminal and the 4th signal receiving interface of 2 grade of first multiple selector two with 3 grade of first multiple selector respectively
Input terminal is connected, ┅, and the output terminal and the n-th signal receiving interface of m-1 the first multiple selector of grade select respectively with the first multichannel of m grades
Two input terminals for selecting device are connected, and the output terminal of m the first multiple selector of grade is connected with the input terminal of the logic functional block；
Signal, which selects an output circuit, after processing includes n signal output being used cooperatively with above-mentioned n signal receiving interface
Interface and n the second multiple selector, n signal output interface be the 1st signal output interface, the 2nd signal output interface, ┅,
N-th signal output interface, n the second multiple selector are 1 grade of second multiple selector, 2 grade of second multiple selector, ┅, n grades
Second multiple selector；The output terminal of the logic functional block input terminal phase with above-mentioned each second multiple selector respectively
Even；The output terminal of i the second multiple selector of grade is another with the i-th signal output interface and i+1 the second multiple selector of grade respectively
Input terminal is connected, wherein 1≤i≤n-1, i ∈ Ν；The output terminal of n the second multiple selector of grade and the n-th signal output interface phase
Even；
The output terminal of the logic functional block also respectively with the Enable Pin of above-mentioned each first multiple selector and above-mentioned each second
The Enable Pin of multiple selector is connected；
Above-mentioned n=m+1 >=3, n ∈ Ν and m ∈ Ν；
The programmable logic device is CPLD or FPGA.
2. programmable logic device internal logic function module time-sharing multiplex circuit according to claim 1, feature exist
In the logic functional block is time delay module.
3. programmable logic device internal logic function module time-sharing multiplex circuit according to claim 1 or 2, feature
It is, above-mentioned first multiple selector uses two using alternative multiple selector and/or above-mentioned second multiple selector
Select a multiple selector.
4. programmable logic device internal logic function module time-sharing multiplex circuit according to claim 1 or 2, feature
It is, above-mentioned signal receiving interface uses GPIO interface using GPIO interface and/or above-mentioned signal output interface.
5. a kind of programmable logic device, which is characterized in that programmable logic as claimed in claim 1 or 2 is integrated in it
Device inside logic functional block time-sharing multiplex circuit.
6. programmable logic device according to claim 5, which is characterized in that the programmable logic device internal logic
First multiple selector of function module time-sharing multiplex circuit is patrolled using alternative multiple selector and/or described may be programmed
The second multiple selector for collecting device inside logic functional block time-sharing multiplex circuit uses alternative multiple selector.
7. programmable logic device according to claim 5, which is characterized in that the programmable logic device internal logic
The signal receiving interface of function module time-sharing multiplex circuit is used inside GPIO interface and/or the programmable logic device
The signal output interface of logic functional block time-sharing multiplex circuit uses GPIO interface.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109905106A (en) * | 2019-03-15 | 2019-06-18 | 湖南国科微电子股份有限公司 | A kind of data selection circuit, chip and electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109905106A (en) * | 2019-03-15 | 2019-06-18 | 湖南国科微电子股份有限公司 | A kind of data selection circuit, chip and electronic equipment |
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