CN109669892A - A kind of MCBSP interface circuit based on FPGA - Google Patents
A kind of MCBSP interface circuit based on FPGA Download PDFInfo
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- CN109669892A CN109669892A CN201811264368.3A CN201811264368A CN109669892A CN 109669892 A CN109669892 A CN 109669892A CN 201811264368 A CN201811264368 A CN 201811264368A CN 109669892 A CN109669892 A CN 109669892A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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Abstract
The present invention provides a kind of MCBSP interface circuit based on FPGA, parallel data is written to and receives in fifo module by serioparallel exchange module, the write-in port for receiving fifo module connects serioparallel exchange module, the reading port for receiving fifo module connects local parallel bus management module, receive data bulk port disconnecting processing module in fifo module, overtime interrupt signal is overflowed and received to interruption processing module for generating to receive, and local parallel bus management module is responsible for the address latch decoding of local parallel bus, status register setting.The present invention completes local parallel bus and MCBSP general line system function, while the real-time to guarantee data communication, supports to interrupt receiving.By design, emulation, verifying, modular product is formed, with stronger flexibility ratio and scalability, it can be achieved that Rapid transplant between different product, in this way acceleration product development process.
Description
Technical field
The present invention relates to Embedded System Design technical field, especially a kind of MCBSP interface circuit.
Background technique
MCBSP is the multichannel buffer serial line interface integrated in the digital signal processing chip DSP of TI company production, including
One data channel and a control channel are connect by 7 pins with external equipment.MCBSP is in standard serial interface
On the basis of function is extended, it have basic function identical with common serial ports twoport, while support multichannel send and
The specific functions such as reception.
At present in airborne equipment, image, signal processing generally use the dsp chip of TI, and MCBSP interface is as such
Dsp chip external communication interface, DSP need by the data after image, signal processing by MCBSP interface be sent to PowerPC,
The application processors such as FPGA, but PowerPC and FPGA do not have MCBSP bus hardware interface, therefore how to design a kind of mould
The standard MCBSP interface circuit product of block realizes the Rapid transplant between different model product, improves research and development of products efficiency, is
There is an urgent need to the projects of research for we.
Summary of the invention
For overcome the deficiencies in the prior art, the present invention provides a kind of MCBSP interface circuit based on FPGA, realizes part
The conversion of parallel bus and MCBSP bus forms the modular product of standard, improves the versatility of interface circuit.
To achieve the above object, standard Verilog can be used in the present invention or VHDL language is completed, and is based on FPGA hardware platform
It realizes, using modular design method, to improve the flexibility and scalability of interface circuit.
The technical solution adopted by the present invention to solve the technical problems is:
A kind of MCBSP interface circuit based on FPGA includes serioparallel exchange module, receives fifo module, at interruption
It manages module, send fifo module, parallel serial conversion module and local parallel bus management module.
MCBSP serial input signals FSR, CLR and DR are converted to parallel data RX_DIN by the serioparallel exchange module,
And be written to and receive in fifo module, wherein FSR is to receive synchronization frame, and CLR is to receive synchronised clock, and DR is to receive serial data
Frame, RX_DIN connection receive the write-in port of fifo module, and serioparallel exchange module is realized by Verilog or VHDL code.
It receives fifo module and receives data for caching, realized by the IP that logic chip producer provides, receive FIFO mould
The parallel data of the write-in port connection serioparallel exchange module of block exports RX_DIN, receives the reading port connection office of fifo module
The input RX_DOUT of portion's parallel bus management module is received in fifo module at the DATA_CNT disconnecting of data bulk port
Manage module.
Interruption processing module receives spilling and reception overtime interrupt signal for generating, and interruption processing module passes through
DATA_CNT monitoring receives the data bulk in fifo module, when data bulk is more than down trigger set by user
When depth or reception time-out, interrupt signal IRQ is generated, while interruption processing module provides one group of status register, can receive office
The 16 parallel-by-bit signals of the IRQ_SET of portion's parallel bus management module are interrupted for down trigger depth and time-out time to be arranged
Processing module is realized by Verilog or VHDL code.
Local parallel bus management module is responsible for the address latch decoding of local parallel bus, status register setting, office
Portion's parallel bus management module is realized by Verilog code or VHDL.
It sends fifo module caching and sends data, realized by the IP that logic chip producer provides, send fifo module
Port TX_DIN connection local parallel bus management module is written, sends the reading port TX_DOUT and FIFO empty of fifo module
Indication signal EMPTY connection parallel serial conversion module.
Parallel input data is converted to serial data output by parallel serial conversion module, and output signal FSX, CLX, DX are respectively
Send synchronization frame, send synchronised clock, send data, parallel serial conversion module input terminal receive and send fifo module reading port and
FIFO empty indication signal EMPTY, when EMPTY is invalid, after parallel serial conversion module reads the data conversion sent in fifo module
Output, until EMPTY signal is effective, parallel serial conversion module is realized by Verilog or VHDL code.
It is complete the beneficial effects of the invention are as follows realizing a kind of bus interface circuit that can be transplanted on different fpga chips
At local parallel bus and MCBSP general line system function, while the real-time to guarantee data communication, support to interrupt receiving.It is logical
Design, emulation, verifying are crossed, modular product is formed.Its advantage is that having stronger flexibility ratio and scalability, it can be achieved that difference
Rapid transplant between product, in this way acceleration product development process.
Detailed description of the invention
Fig. 1 is that the present invention is based on the MCBSP interface circuit design block diagrams of FPGA.
Specific embodiment
Present invention will be further explained below with reference to the attached drawings and examples.
MCBSP interface circuit based on FPGA of the invention includes serioparallel exchange module, receives fifo module, interrupt processing
Module sends fifo module, parallel serial conversion module and local parallel bus management module.
MCBSP serial input signals FSR, CLR and DR are converted to parallel data RX_DIN by the serioparallel exchange module,
And be written to and receive in fifo module, wherein FSR is to receive synchronization frame, and CLR is to receive synchronised clock, and DR is to receive serial data
Frame, RX_DIN connection receive the write-in port of fifo module, and serioparallel exchange module is realized by Verilog or VHDL code.
It receives fifo module and receives data for caching, realized by the IP that logic chip producer provides, receive FIFO mould
The parallel data of the write-in port connection serioparallel exchange module of block exports RX_DIN, receives the reading port connection office of fifo module
The input RX_DOUT of portion's parallel bus management module is received in fifo module at the DATA_CNT disconnecting of data bulk port
Manage module.
Interruption processing module receives spilling and reception overtime interrupt signal for generating, and interruption processing module passes through DATA_
CNT monitoring receives the data bulk in fifo module, when data bulk is more than down trigger depth set by user or is received super
Constantly, interrupt signal IRQ is generated, while interruption processing module provides one group of status register, can receive the total spool of local parallel
The 16 parallel-by-bit signals of the IRQ_SET of module are managed, for down trigger depth and time-out time to be arranged, interruption processing module passes through
Verilog or VHDL code is realized.
Local parallel bus management module is responsible for the address latch decoding of local parallel bus, status register setting, office
Portion's parallel bus management module is realized by Verilog code or VHDL.
It sends fifo module caching and sends data, realized by the IP that logic chip producer provides, send fifo module
Port TX_DIN connection local parallel bus management module is written, sends the reading port TX_DOUT and FIFO empty of fifo module
Indication signal EMPTY connection parallel serial conversion module.
Parallel input data is converted to serial data output by parallel serial conversion module, and output signal FSX, CLX, DX are respectively
Send synchronization frame, send synchronised clock, send data, parallel serial conversion module input terminal receive and send fifo module reading port and
FIFO empty indication signal EMPTY, when EMPTY is invalid, after parallel serial conversion module reads the data conversion sent in fifo module
Output, until EMPTY signal is effective, parallel serial conversion module is realized by Verilog or VHDL code.
MCBSP interface circuit functional block diagram based on FPGA is as shown in Figure 1, comprising:
1. serioparallel exchange module
Serioparallel exchange module is responsible for MCBSP serial input signals FSR, CLR, DR being converted to parallel data RX_DIN, and
It is written to and receives in fifo module, wherein FSR is reception synchronization frame, CLR is reception synchronised clock, DR is to receive serial data
Frame, RX_DIN connection receive the write-in port of fifo module.The module is realized by Verilog or VHDL code.
2. receiving fifo module
It receives fifo module and receives data for caching, realized by the mature IP that logic chip producer provides, FIFO's
The parallel data that port connection serioparallel exchange module is written exports RX_DIN, reads port and connects local parallel bus management module
Input RX_DOUT, FIFO in data bulk port DATA_CNT connect interruption processing module.
3. interruption processing module
Interruption processing module is responsible for completing to receive overflowing and receiving the generation of overtime interrupt signal, which passes through
DATA_CNT monitoring receives data bulk in fifo module, when being more than down trigger depth or receiving time-out, produces
Raw interrupt signal IRQ.The module receives the 16 parallel-by-bit signal of IRQ_SET of local parallel bus management module simultaneously, for setting
Set down trigger depth and time-out time.The module is realized by Verilog or VHDL code.
4. parallel serial conversion module
Parallel serial conversion module is responsible for being converted to parallel input data into serial data output, and output signal FSX, CLX, DX points
Synchronization frame Wei not be sent, synchronised clock is sent, sends data.The module input receive and send fifo module reading port and
FIFO empty indication signal EMPTY, when EMPTY is invalid, which exports after reading the data conversion in FIFO, until EMPTY
Signal is effective.The module is realized by Verilog or VHDL code.
5. sending fifo module
It sends fifo module and sends data for caching, realized by the mature IP that logic chip producer provides, FIFO's
Port TX_DIN connection local parallel bus management module is written, reads port TX_DOUT and FIFO empty indication signal EMPTY and connects
Connect parallel serial conversion module.
6. local parallel bus management module
Local parallel bus management module is responsible for the address latch of local parallel bus, decoding, and function is arranged in status register
Can, which is realized by Verilog or VHDL code.
Claims (1)
1. a kind of MCBSP interface circuit based on FPGA, it is characterised in that:
A kind of MCBSP interface circuit based on FPGA includes serioparallel exchange module, receives fifo module, interrupt processing mould
Block sends fifo module, parallel serial conversion module and local parallel bus management module；
MCBSP serial input signals FSR, CLR and DR are converted to parallel data RX_DIN by the serioparallel exchange module, and are write
Enter to receiving in fifo module, wherein FSR is to receive synchronization frame, and CLR is to receive synchronised clock, and DR is to receive serial data frame,
RX_DIN connection receives the write-in port of fifo module, and serioparallel exchange module is realized by Verilog or VHDL code；
It receives fifo module and receives data for caching, realized by the IP that logic chip producer provides, receive fifo module
The parallel data that port connection serioparallel exchange module is written exports RX_DIN, receives the reading port connection part of fifo module simultaneously
The input RX_DOUT of row bus management module receives data bulk port DATA_CNT disconnecting in fifo module and handles mould
Block；
Overtime interrupt signal is overflowed and received to interruption processing module for generating to receive, and interruption processing module is supervised by DATA_CNT
The data bulk received in fifo module is surveyed, when data bulk is more than down trigger depth set by user or receives time-out,
Interrupt signal IRQ is generated, while interruption processing module provides one group of status register, can receive local parallel bus management module
IRQ_SET 16 parallel-by-bit signals, for down trigger depth and time-out time to be arranged, interruption processing module passes through
Verilog or VHDL code is realized；
Local parallel bus management module is responsible for the address latch decoding of local parallel bus, status register setting, and part is simultaneously
Row bus management module is realized by Verilog code or VHDL；
It sends fifo module caching and sends data, realized by the IP that logic chip producer provides, send the write-in of fifo module
TX_DIN connection local parallel bus management module in port sends reading port TX_DOUT and the FIFO empty instruction of fifo module
Signal EMPTY connection parallel serial conversion module；
Parallel input data is converted to serial data output by parallel serial conversion module, and output signal FSX, CLX, DX are respectively to send
Synchronization frame sends synchronised clock, sends data, and parallel serial conversion module input terminal receives and sends reading port and the FIFO of fifo module
Empty indication signal EMPTY, when EMPTY is invalid, parallel serial conversion module exports after reading the data conversion sent in fifo module,
Until EMPTY signal is effective, parallel serial conversion module is realized by Verilog or VHDL code.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114281728A (en) * | 2021-12-14 | 2022-04-05 | 中国航空工业集团公司洛阳电光设备研究所 | Modular standard UART interface logic IP core |
| CN114281736A (en) * | 2021-12-29 | 2022-04-05 | 天津光电通信技术有限公司 | Serial port arbitration communication device based on FPGA |
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