CN207150563U - A kind of circuit and drive system of fast reaction fault-signal - Google Patents
A kind of circuit and drive system of fast reaction fault-signal Download PDFInfo
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- CN207150563U CN207150563U CN201720903013.9U CN201720903013U CN207150563U CN 207150563 U CN207150563 U CN 207150563U CN 201720903013 U CN201720903013 U CN 201720903013U CN 207150563 U CN207150563 U CN 207150563U
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Abstract
The utility model discloses a kind of circuit and drive system of fast reaction fault-signal,The utility model includes the first NAND gate U11A,Second NAND gate U11C,3rd NAND gate U11D,An input of the first NAND gate U11A is as fault-signal low level Enable Pin,Another input input with the second NAND gate U11C respectively,3rd NAND gate U11D output end connection,3rd NAND gate U11D output end uploads end as fault-signal,Second NAND gate U11C another input is as control Enable Pin,Second NAND gate U11C output end is as low level Enable Pin,First NAND gate U11A output end is connected with a 3rd NAND gate U11D input,3rd NAND gate U11D another input is as fault-signal reset terminal.The advantages of utility model, is：Quick obtaining closes driving Acquisition Circuit, so as to protect part to be driven, and being capable of latch fault signal
Description
Technical field
The utility model is related to the field of driver in circuit, more particularly to a kind of circuit of fast reaction fault-signal and
Drive system.
Background technology
In the industry such as power supply or motor driver, the circuit structure of driving power device is as shown in figure 1, the circuit bag
Include single-chip microprocessor MCU, buffer, driving Acquisition Circuit, device to be driven.The single-chip microprocessor MCU includes the first output end, second defeated
Go out end, first input end.Buffer includes first input end, the second input, the first output end.Acquisition Circuit is driven to include the
One input, the second input, the first output end and the second output end.First output end of single-chip microprocessor MCU and the of buffer
The connection of one input, the first output end of buffer are with driving the first input end of Acquisition Circuit to be connected, driving Acquisition Circuit warp
The second input and the second output end is crossed to be bi-directionally connected with device to be driven.The first output end of Acquisition Circuit is driven as failure
The first input end of signal low level Enable Pin and single-chip microprocessor MCU connects, and the second output end of single-chip microprocessor MCU makes as low level
Second input of energy end and buffer connects.
In figureFor fault-signal,For enable signal.
The enable signal that single-chip microprocessor MCU exports low level Enable PinSet low, the output end of single-chip microprocessor MCU first is sent
Signal A is by the first output end of buffer output signal B, signal B by driving the first output end output signal of Acquisition Circuit
C, signal C driving powers device (power device includes the devices such as metal-oxide-semiconductor, IGBT, triode), driving Acquisition Circuit pass through sampling
The signal of power device determines whether there is the failures such as excessively stream, short circuit, the failure sent so as to fault-signal low level Enable Pin
SignalTo the first input end of single-chip microcomputer.In figureFor fault-signal low level Enable Pin receive for failure
Signal,The enable signal sent for low level Enable Pin.
It is by fault-signal in existing schemeSingle-chip microprocessor MCU is linked into, interrupt routine is performed by single-chip microprocessor MCU
To put high enable signalSo as to close driving Acquisition Circuit, and then close device work to be driven.Single-chip microprocessor MCU performs
Interrupt routine responds fault-signalIt is a veryer long process, because single-chip microprocessor MCU is needed first by data pressure
Enter storehouse, then perform corresponding interrupt service routine, at least need ten instruction cycles.Even if using than single-chip microprocessor MCU place
Manage for the DSP of data advantageously, with DSP --- TMS320F28335 more advanced at present, use 24MHZ clock frequencies
The speed of service, an instruction cycle 42ns, from receive fault-signalHigh enable signal is put to being sent to buffer
Instruction, this process at least needs the 420ns times, and this does not include the delay from buffer signal to power device also.At this
During sample, once shorted devices to be driven, energy Q caused by device to be driven, which is likely to allow, itself to be burnt.In addition, if
Fault-signalDuration is very short, and less than 100ns, single-chip microprocessor MCU is likely to inquiry less than fault-signalAlways
It, the response of fault-signal is realized by software, is very slow.Therefore it is badly in need of a kind of circuit of fast reaction fault-signal to solve
The certainly technical problem.
Utility model content
In order to overcome the above-mentioned deficiencies of the prior art, the purpose of this utility model is to solve real by software in the prior art
The corresponding speed of existing fault-signal may burn device to be driven slowly excessively, and single-chip microprocessor MCU very may be used in data processing
It can inquire about less than fault-signalThe problem of, therefore, the utility model provides a kind of circuit of fast reaction fault-signal
And drive system.
To achieve the above object, the utility model uses following technical scheme：
A kind of circuit of fast reaction fault-signal, including the first NAND gate U11A, the second NAND gate U11C, the 3rd with it is non-
Door U11D, the first NAND gate U11A an input are as fault-signal low level Enable Pin, another input difference
The output end of an input, the 3rd NAND gate U11D with the second NAND gate U11C is connected, the 3rd NAND gate U11D output
End uploads end as fault-signal, and the second NAND gate U11C another input is as control Enable Pin, the second NAND gate
U11C output end is as low level Enable Pin, the first NAND gate U11A output end and a 3rd NAND gate U11D input
End connection, the 3rd NAND gate U11D another input is as fault-signal reset terminal.
Optimization, in addition to power vd D, resistance R1, electric capacity C1, the power vd D successively by resistance R1, electric capacity C1 with
Ground is connected, and fault-signal low level Enable Pin is connected with resistance R1 and electric capacity C1 tie point.
Optimization, the electric capacity C1 is 100-1000pF.
Optimization, the first NAND gate U11A, the second NAND gate U11C, the 3rd NAND gate U11D are integrated in NAND gate
In U11, the model 74LS00 of chip where the NAND gate U11.
Optimization, the receiving terminal of NAND gate U11 the 1st pin as fault-signal, NAND gate U11 the 2nd pin, the 10th pin,
11st pin is connected, and end is uploaded as fault-signal after connection, and the 3rd pin is connected with the 12nd pin, the 8th pin as low level Enable Pin,
9th pin is connected to ground as control Enable Pin, the 7th pin, and the 13rd pin connects as fault-signal reset terminal, the 14th pin with power vd D
Connect.
A kind of drive system of the circuit including above-mentioned fast reaction fault-signal, in addition to single-chip microprocessor MCU, buffering
Device, driving Acquisition Circuit, the single-chip microprocessor MCU include first input end, the first output end, the second output end, the 3rd output end；
The buffer, which includes first input end, the second input, the first output end, driving Acquisition Circuit, includes first input end and the
One output end；
First output end of the single-chip microprocessor MCU and the first input end of buffer connect, the first output end of buffer
With driving the first input end of Acquisition Circuit to be connected；
The fault-signal uploads the first input of end, fault-signal reset terminal, control Enable Pin respectively with single-chip microprocessor MCU
Second input of end, the connection of the second output end, the 3rd output end, the low level Enable Pin and buffer connects, the drive
First output end of dynamic Acquisition Circuit is connected with fault-signal low level Enable Pin.
Optimization, in addition to device to be driven, it is described to drive Acquisition Circuit also to include the second input and the second output end,
Driving Acquisition Circuit is bi-directionally connected by the second input and the second output end with device to be driven.
Optimization, the device to be driven is metal-oxide-semiconductor, the grid of the metal-oxide-semiconductor and the second output of driving Acquisition Circuit
End connection, the source electrode of the metal-oxide-semiconductor are connected with the second input.
Optimization, the device to be driven is that IGBT is managed, and the second of the grids of the IGBT pipes and driving Acquisition Circuit is defeated
Go out end connection, the source electrode of the IGBT pipes is connected with the second input.
Optimization, the device to be driven be triode, the base stage of the triode and the second of driving Acquisition Circuit defeated
Go out end connection, the emitter stage of the triode is connected with the second input.
The utility model has the advantage of：
(1) circuit in the utility model can be with quick obtaining fault-signalHigh enable signal is put in controlClose
Driving Acquisition Circuit is closed, so as to protect part to be driven, and the circuit being capable of latch fault signalPrevent failure from believing
NumberLose.
It is emphasized that：The utility model is only protected by between above-mentioned physical unit and each physical unit of connection
The device or physical platform that circuit is formed, without regard to software section therein.
(2) the electric capacity C1 values in the utility model are bigger, accordingly slower, but it is better to filter out burr effect, according to more
Secondary experiment detection, determine C1 value size.
Brief description of the drawings
Fig. 1 is the module frame chart of drive system in the prior art.
Fig. 2 is a kind of circuit diagram of the circuit of fast reaction fault-signal of the utility model.
Fig. 3 is the module frame chart of the utility model drive system.
Each part is described as follows in figure：
1- buffers 2- drives the circuit of Acquisition Circuit 3- device 4- fast reaction fault-signals to be driven.
Embodiment
Embodiment 1
As shown in Fig. 2 a kind of circuit of fast reaction fault-signal, including power vd D, resistance R1, electric capacity C1, first with
NOT gate U11A, the second NAND gate U11C, the 3rd NAND gate U11D.First NAND gate U11A, the second NAND gate U11C, the 3rd with it is non-
Door U11D is integrated in NAND gate U11, the model 74LS00 of chip where NAND gate U11.
A first NAND gate U11A input is NAND gate U11 the 1st pin as fault-signal low level Enable Pin.
First NAND gate U11A another input respectively an input with the second NAND gate U11C, the 3rd NAND gate U11D it is defeated
Go out end connection, i.e. NAND gate U11 the 2nd pin, the 10th pin, the connection of the 11st pin, end is uploaded as fault-signal after connection.Second with
NOT gate U11C another input is NAND gate U11 the 9th pin as control Enable Pin, the second NAND gate U11C output end
I.e. NAND gate U11 the 8th pin is as low level Enable Pin, the first NAND gate U11A output end and the one of the 3rd NAND gate U11D
Individual input connection, i.e. NAND gate U11 the 3rd pin and the connection of the 12nd pin.3rd NAND gate U11D another input i.e. with
NOT gate U11 the 13rd pin is as fault-signal reset terminal.NAND gate U11 the 7th pin is connected to ground, and the 14th pin connects with power vd D
Connect.
In order to filter out fault-signal low level Enable Pin input burr, power vd D successively by resistance R1, electric capacity C1 with
Ground is connected, and fault-signal low level Enable Pin is connected with resistance R1 and electric capacity C1 tie point.Because electric capacity is bigger, response speed
It is slower, but filter out that burr effect is better, and after test of many times, it is 100pF to determine electric capacity C1.
The utility model when in use, can coordinate to be used with software of the prior art.With reference to existing
Operation principle of the present utility model is described software in technology, it must be noted that be：Match with the utility model
The software of conjunction is not innovative part of the present utility model, nor part of the present utility model.
In figureFor fault-signal low level Enable Pin receive for fault-signal, FAULT_RST be failure letter
Reset signal that number reset terminal receives, Contrl OE are the control enable signal that control Enable Pin receives,Enabled for low level
The enable signal sent is held, Contrl OE are controlEnabled, whenTri- FAULT_RST, Contrl OE letters
In the case of number being all high level, each pin can occur the following two kinds state at random after upper electricity：
State one：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 1 | 1 | 1 | 1 | 0 | 0 |
State two：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 1 | 1 | 1 | 0 | 1 | 1 |
After upper electricity, 1 pin, 9 pin, 13 pin are put by height by the control of external circuitry or chip first, then 13 pin start multiple
Position, is finally to set low 13 pin, the state change of each pin finally obtained is：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 1 | 1 | 0 | 1 | 0 | 0 |
13 pin are put into height again, each pin, which becomes, to be turned to：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 1 | 1 | 1 | 1 | 0 | 0 |
Now, the circuit of fast reaction fault-signal is in monitored state, onceFor low level, each feet state is stood
Horse changes, and is latched as：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 0 | 1 | 1 | 0 | 1 | 1 |
This process is from the enable signal started to the 8th pinHigh lasting several nanoseconds are put, then passes through the 11st pin failure and believes
Number upload end upload fault-signal.
Even if the 1st pin becomes again turns to high level, state is also to maintain original state and is latched as：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 0 | 1 | 1 | 0 | 1 | 1 |
To recover monitored state, repeat FAULT_RST and reset operation.
It is to put height that if control chip, which is actively closed enabled,Contrl OE need to only be set low, state change is as follows：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 1 | 0 | 1 | 0 | 1 | 1 |
Embodiment 2
As Figure 2-3, a kind of drive system, including single-chip microprocessor MCU, buffer 1, driving Acquisition Circuit 2, device to be driven
The circuit 4 of part 3, fast reaction fault-signal.Single-chip microprocessor MCU includes first input end, the second input, the first output end, the
Two output ends, the 3rd output end；Buffer 1 includes first input end, the second input, the first output end, driving Acquisition Circuit 2
Including first input end, the second input, the first output end and the second output end.
First output end of single-chip microprocessor MCU is connected with the first input end of buffer 1, the first output end of buffer 1 with
Drive the first input end connection of Acquisition Circuit 2, the first input end of the first output end and driving Acquisition Circuit 2 of buffer 1
Connection, driving Acquisition Circuit 2 are bi-directionally connected by the second input and the second output end with device 3 to be driven.Driving collection electricity
Road 2 determines whether there is the failures such as excessively stream, short circuit by the signal of sampled power device, so as to fault-signal low level Enable Pin
The fault-signal sent to single-chip microcomputer first input end.
Device 3 to be driven is power device, and part 3 to be driven can be metal-oxide-semiconductor, and the grid of metal-oxide-semiconductor and driving collection are electric
The second output end connection on road, the source electrode of the metal-oxide-semiconductor are connected with the second input.
Device 3 to be driven can also be that IGBT is managed, and the grid of IGBT pipes is connected with the second output end of driving Acquisition Circuit,
The source electrode of the IGBT pipes is connected with the second input.
Device 3 to be driven can also be triode, and the base stage of triode is connected with the second output end of driving Acquisition Circuit,
The emitter stage of the triode is connected with the second input.
The circuit 4 of fast reaction fault-signal includes NAND gate U11, power vd D, resistance R1, electric capacity C1, NAND gate U11
Chip model be 74LS00.The NAND gate chip includes the first NAND gate U11A, the second NAND gate U11C, the 3rd NAND gate
U11D。
A first NAND gate U11A input is NAND gate U11 the 1st pin as fault-signal low level Enable Pin
With driving the first output end of Acquisition Circuit 2 to be connected.First NAND gate U11A another input distinguishes the second NAND gate U11C
An input, the 3rd NAND gate U11D output end connection, i.e. NAND gate U11 the 2nd pin, the 10th pin, the 11st pin connect
Connect, the first input end for uploading end and single-chip microprocessor MCU after connection as fault-signal connects.Second NAND gate U11C another
Input is that NAND gate U11 the 9th pin connects as the 3rd input of control Enable Pin and single-chip microprocessor MCU, the second NAND gate
U11C output end be NAND gate U11 the 8th pin as low level Enable Pin, the second of low level Enable Pin and buffer 1 is defeated
Enter end connection.First NAND gate U11A output end is connected with a 3rd NAND gate U11D input, i.e. NAND gate U11's
3rd pin and the connection of the 12nd pin.3rd NAND gate U11D another input is NAND gate U11 the 13rd pin as fault-signal
The second input connection of reset terminal, fault-signal reset terminal and single-chip microprocessor MCU.NAND gate U11 the 7th pin is connected to ground, the
14 pin are connected with power vd D.
In order to filter out fault-signal low level Enable Pin input burr, power vd D successively by resistance R1, electric capacity C1 with
Ground is connected, and fault-signal low level Enable Pin is connected with resistance R1 and electric capacity C1 tie point.Because electric capacity is bigger, response speed
It is slower, but filter out that burr effect is better, and after test of many times, it is 100pF to determine electric capacity C1.
The utility model when in use, can coordinate to be used with software of the prior art.With reference to existing
Operation principle of the present utility model is described software in technology, it must be noted that be：Match with the utility model
The software of conjunction is not innovative part of the present utility model, nor part of the present utility model.
Fault-signal low level Enable Pin receives in figureFor fault-signal, what fault-signal reset terminal received
FAULT_RST be reset signal, control Enable Pin receive Contrl OE for control enable signal, low level Enable Pin hair
Go outFor enable signal, Contrl OE are controlEnabled.WhenTri- FAULT_RST, Contrl OE letters
In the case of number being all high level, each pin can occur the following two kinds state at random after upper electricity：
State one：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 1 | 1 | 1 | 1 | 0 | 0 |
State two：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 1 | 1 | 1 | 0 | 1 | 1 |
After upper electricity, 1 pin, 9 pin, 13 pin are put height by single-chip microprocessor MCU first, and then 13 pin start to reset, and are finally to set low 13
Pin, the state change of each pin finally obtained are：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 1 | 1 | 0 | 1 | 0 | 0 |
13 pin are put into height again, each pin, which becomes, to be turned to：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 1 | 1 | 1 | 1 | 0 | 0 |
Now, the circuit of fast reaction fault-signal is in monitored state, onceFor low level, each feet state is stood
Horse changes, and is latched as：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 0 | 1 | 1 | 0 | 1 | 1 |
This process from start toPut high lasting several nanoseconds, subsequent single-chip microprocessor MCU receives the failure letter of the 11st pin upload
Number.
Even if the 1st pin becomes again turns to high level, state is also to maintain original state and is latched as：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 0 | 1 | 1 | 0 | 1 | 1 |
To recover monitored state, repeat FAULT_RST and reset operation.
It is to put height that if single-chip microprocessor MCU, which is actively closed enabled,Contrl OE need to only be set low, state change is such as
Under：
| 1 pin | 9 pin | 13 pin | The pin of the pin of 2 pin/10/11 | The pin of 3 pin/12 | 8 pin |
| 1 | 0 | 1 | 0 | 1 | 1 |
Embodiment 3
It is with above-mentioned two embodiment difference, electric capacity C1 value is 1000PF.
Embodiment 4
It is with embodiment 1 and the difference of embodiment 2, electric capacity C1 value is 500PF.
The preferred embodiment only created above as the utility model, do not created to limit the utility model,
All any modification, equivalent and improvement made within all spirit and principle created in the utility model etc., should be included in
Within the protection domain that the utility model is created.
Claims (10)
1. a kind of circuit of fast reaction fault-signal, it is characterised in that including the first NAND gate U11A, the second NAND gate
U11C, the 3rd NAND gate U11D, an input of the first NAND gate U11A is as fault-signal low level Enable Pin, separately
An input with the second NAND gate U11C, the 3rd NAND gate U11D output end are connected one input respectively, the 3rd with it is non-
Door U11D output end uploads end as fault-signal, and the second NAND gate U11C another input is used as control Enable Pin,
Second NAND gate U11C output end is as low level Enable Pin, the first NAND gate U11A output end and the 3rd NAND gate U11D
An input connection, the 3rd NAND gate U11D another input is as fault-signal reset terminal.
A kind of 2. circuit of fast reaction fault-signal according to claim 1, it is characterised in that also including power vd D,
Resistance R1, electric capacity C1, the power vd D are connected to ground by resistance R1, electric capacity C1 successively, fault-signal low level Enable Pin with
Resistance R1 connects with electric capacity C1 tie point.
A kind of 3. circuit of fast reaction fault-signal according to claim 1, it is characterised in that the electric capacity C1 scopes
For 100-1000pF.
A kind of 4. circuit of fast reaction fault-signal according to claim 1, it is characterised in that first NAND gate
U11A, the second NAND gate U11C, the 3rd NAND gate U11D are integrated in NAND gate U11, the type of chip where the NAND gate U11
Number it is 74LS00.
A kind of 5. circuit of fast reaction fault-signal according to claim 4, it is characterised in that the 1st of NAND gate U11
Receiving terminal of the pin as fault-signal, NAND gate U11 the 2nd pin, the 10th pin, the connection of the 11st pin, is used as fault-signal after connection
End is uploaded, the 3rd pin is connected with the 12nd pin, and the 8th pin is as low level Enable Pin, and the 9th pin is as control Enable Pin, the 7th pin and ground
Connection, the 13rd pin are connected as fault-signal reset terminal, the 14th pin with power vd D.
6. a kind of drive system of the circuit of the fast reaction fault-signal including as described in claim 1-5 any one, its
It is characterised by, in addition to single-chip microprocessor MCU, buffer (1), driving Acquisition Circuit (2), the single-chip microprocessor MCU include the first input
End, the first output end, the second output end, the 3rd output end；The buffer (1) includes first input end, the second input, the
One output end, driving Acquisition Circuit (2) include first input end and the first output end；
First output end of the single-chip microprocessor MCU is connected with the first input end of buffer (1), the first output of buffer (1)
The first input end with driving Acquisition Circuit (2) is held to be connected；
The fault-signal upload end, fault-signal reset terminal, control Enable Pin respectively the first input end with single-chip microprocessor MCU,
Second output end, the connection of the 3rd output end, the low level Enable Pin are connected with the second input of buffer (1), the drive
First output end of dynamic Acquisition Circuit (2) is connected with fault-signal low level Enable Pin.
7. drive system according to claim 6, it is characterised in that also including device to be driven (3), the driving collection
Circuit (2) also includes the second input and the second output end, and driving Acquisition Circuit (2) passes through the second input and the second output end
It is bi-directionally connected with device to be driven (3).
8. drive system according to claim 7, it is characterised in that the device (3) to be driven is metal-oxide-semiconductor, the MOS
With driving the second output end of Acquisition Circuit to be connected, the source electrode of the metal-oxide-semiconductor is connected the grid of pipe with the second input.
9. drive system according to claim 7, it is characterised in that the device (3) to be driven is managed for IGBT, described
With driving the second output end of Acquisition Circuit to be connected, the source electrode of the IGBT pipes is connected the grid of IGBT pipes with the second input.
10. drive system according to claim 7, it is characterised in that the device (3) to be driven is triode, described
With driving the second output end of Acquisition Circuit to be connected, the emitter stage of the triode and the second input connect the base stage of triode
Connect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720903013.9U CN207150563U (en) | 2017-07-24 | 2017-07-24 | A kind of circuit and drive system of fast reaction fault-signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720903013.9U CN207150563U (en) | 2017-07-24 | 2017-07-24 | A kind of circuit and drive system of fast reaction fault-signal |
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| Publication Number | Publication Date |
|---|---|
| CN207150563U true CN207150563U (en) | 2018-03-27 |
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| CN201720903013.9U Active CN207150563U (en) | 2017-07-24 | 2017-07-24 | A kind of circuit and drive system of fast reaction fault-signal |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107395190A (en) * | 2017-07-24 | 2017-11-24 | 安徽力高新能源技术有限公司 | A kind of circuit and drive system of fast reaction fault-signal |
-
2017
- 2017-07-24 CN CN201720903013.9U patent/CN207150563U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107395190A (en) * | 2017-07-24 | 2017-11-24 | 安徽力高新能源技术有限公司 | A kind of circuit and drive system of fast reaction fault-signal |
| CN107395190B (en) * | 2017-07-24 | 2024-03-22 | 力高(山东)新能源技术股份有限公司 | Circuit and driving system for rapidly responding to fault signals |
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