CN207134348U - The embedded fan-out-type silicon pinboard of three-dimensional systematic package application - Google Patents
The embedded fan-out-type silicon pinboard of three-dimensional systematic package application Download PDFInfo
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- CN207134348U CN207134348U CN201721177329.0U CN201721177329U CN207134348U CN 207134348 U CN207134348 U CN 207134348U CN 201721177329 U CN201721177329 U CN 201721177329U CN 207134348 U CN207134348 U CN 207134348U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Abstract
The utility model discloses a kind of embedded fan-out-type silicon adapter plate structure of three-dimensional systematic package application, setting side wall in silicon substrate front has the cavity of certain slope, the back side sets the vertical interconnection architecture for extending to cavity bottom, and vertical interconnection architecture includes some mutual independent conductive poles；The front of silicon substrate and the side wall of cavity and bottom are provided with the first metal interconnection layer for being connected and making front exit with the microelectronic chip pad being placed in cavity；The back side of silicon substrate is provided with the second metal interconnection layer for making back side exit, and the first metal interconnection layer and the second metal interconnection layer are electrically connected with first metal interconnection layer and the second metal interconnection layer with silicon substrate insulation set, conductive pole respectively.The utility model combines vertical interconnection architecture using cavity, so as to further realize the application of three dimension system encapsulation on the basis of high density, small size, low cost is met, enhances product performance.
Description
Technical field
Microelectronics Packaging field is the utility model is related to, is more particularly related to a kind of towards three-dimensional systematic package application
New embedded fan-out-type silicon adapter plate structure.
Background technology
With the fast development of integrated circuit manufacturing industry, chip size is higher to density, speed faster, it is smaller, into
This more low direction is developed, and traditional fan-in type wafer-level packaging can not meet the requirement of interconnection, but fan-out-type wafer level
Encapsulation due to have the advantages that miniaturization, low cost and high integration, therefore fan-out wafer level package (FOWLP) meet the tendency of and
Raw, it is best suitable for the movement of high request or wireless market, and further promotes the development of high-performance, small size market.
Infineon utility model fan-out wafer level package (FOWLP) patent in 2004, and proposed wafer scale in 2008
EWLB encapsulation technologies are fanned out to, the eWLB technological processes of standard are as follows：The pad pasting first on a slide glass, then chip bonding pad face
It is positioned over down on film；Using wafer level Shooting Technique, by chip buried into moulding compound；Curing mold plastics, remove slide glass；It
Wafer scale technique is carried out to the moulding compound disk for being embedded with chip afterwards；It is passivated in the side of chip bonding pad exposure, metal cloth again
Line, bump bottom metal layer is prepared, plant ball, encapsulation is completed in finally section.At the same time, in the world on Fan-Out wafer levels
Other encapsulation new technologies of encapsulation occur like the mushrooms after rain, the integration fan-out-type proposed such as Taiwan Semiconductor Manufacturing Co. based on Die Up structures
The new technologies such as the SWIFT encapsulation that InFO (Integrated Fan-Out) WLP technologies, AMKOR are proposed based on RDL-First structures
So that Fan-Out Wafer-Level Packaging Technologies are further developed.
The fan-out package technology that Infineon is proposed not only solves requirement and the I/O of microelectronic chip miniature size
The demand of number, and enter multiple chip portfolios in single encapsulation relative to traditional IC package, fan-out package, solve line
The problem of road congestion；Fan-out package is also less than traditional IC encapsulation technology without intermediate plate in cost simultaneously.It is but traditional
Though wafer scale is fanned out to encapsulation technology with metal routing size is small, the accurate advantage of circuit, due to warpage and thermal stress
With the problems such as can not reach panel level and be fanned out to the packaging efficiency of encapsulation and its corresponding inexpensive target.
Should in order to solve the warpage issues of the moulding compound disk appeared in traditional fan-out wafer level package technique and heat
Power matching problem, magnificent day Kunshan develop embedded silicon substrate fan-out package technology (eSiFO).It is carrier using silicon substrate,
By etched recesses on a silicon substrate, chip front side is placed and is fixed in groove upwards so that chip surface and silicon wafer
Surface forms one and is fanned out to face, and multilayer wiring is carried out on this face, and makes exit soldered ball, finally cuts, separates, seals
Dress, so as to reach the operability for increasing encapsulation, reduction panel warpage, improve overall alignment precision, reduction production cost
Purpose.But as structure design becomes increasingly complex, performance requirement is more and more high, eSiFO technologies but can not further meet
The multi-layer three-dimension system application of complexity is realized in smaller package dimension.
Utility model content
To be fanned out in order to solve the above technical problems, we have proposed a kind of new embed towards three-dimensional systematic package application
Type silicon switching plate technique.Vertical interconnection architecture is combined using cavity, so as to meet the basis of high density, small size, low cost
On further realize three dimension system encapsulation application, enhance product performance.
The technical solution of the utility model is：
A kind of embedded fan-out-type silicon pinboard of three-dimensional systematic package application, including silicon substrate, the silicon substrate front
There is the cavity of certain slope provided with side wall, the back side is provided with the vertical interconnection architecture for extending to the cavity bottom, described vertical
Interconnection architecture includes some mutual independent conductive poles；The side wall of the positive and described cavity of the silicon substrate and bottom are provided with
First metal interconnection layer with the microelectronic chip pad being placed in cavity for being connected and make front exit；The silicon
The back side of substrate is provided with the second metal interconnection layer for making back side exit, first metal interconnection layer and the second metal
Interconnection layer is electrically connected with first metal interconnection layer and the second metal with the silicon substrate insulation set, the conductive pole respectively
Interconnection layer.
Optionally, the silicon substrate is the Ω cm of resistivity≤0.1 low-resistance silicon materials, and the silicon substrate back, which is provided with, prolongs
Extend the cavity bottom and separate some annular grooves, fill insulant in the annular groove, in the annular groove
Silicon column within circle forms the conductive pole, the upper and lower side of the silicon column respectively with first metal interconnection layer and the second metal
Interconnection layer forms Ohmic contact.
Optionally, the insulating materials is one kind in silica, glass paste, polypropylene or Parylene etc..
Optionally, the silicon substrate is the Ω cm of resistivity >=1000 high resistant silicon materials, and the silicon substrate back is provided with
The cavity bottom and separate some through holes are extended to, the through hole is filled up completely with or non-full filled conductive material shape
Into the conductive pole, the upper and lower side of the conductive pole electrically connects with first metal interconnection layer and the second metal interconnection layer respectively
Connect.
Optionally, insulating barrier, diffusion impervious layer and metal conducting layer, the expansion are set gradually in the through hole from outside to inside
Dissipate barrier layer and metal conducting layer and form the conductive pole, wherein the insulating barrier silica, silicon nitride, aluminum oxide, BCB, poly-
Acid imide, glass, one kind of polypropylene or Parylene, the diffusion impervious layer are Ta, TaN, TiW at least one, institute
State at least one that conductive metal layer is Cu, Al, Au, W.
Optionally, the front and back of the silicon substrate and the pocket surfaces are provided with insulating barrier, first metal interconnection layer
With the second metal interconnection layer on the insulating barrier, the insulating barrier is described to realize in the conductive pole both ends of the surface opening
The electric connection of first metal interconnection layer, the second metal interconnection layer and the conductive pole.
Optionally, the insulating barrier is silica, silicon nitride, aluminum oxide, BCB, polyimides, glass, polypropylene or poly-
One kind of paraxylene；
The beneficial effects of the utility model：
(1) compared with plastic packaging material, the warpage of encapsulating products can be significantly reduced due to cooking slide glass using silicon；
(2) silicon substrate has high intensity and the characteristic of low stress, it is possible to achieve large size chip encapsulates；
(3) more intensive circuit can be made using wafer equipment and technology, realizes that product minimizes；
(4) silicon substrate more matches with CET such as chip, metal interconnection layers (RDL), improves product reliability；
(5) complicated technologies such as interim bonding, plastic packaging reconciliation bonding are needed not move through, production cost can be reduced and shorten work
Skill flow, it is easier to realize industrialization；
(6) can solve the problems, such as three dimension system encapsulation stacking with vertical interconnection architecture by cavity, realize chip three-dimensional storehouse
With three-dimension packaging application.
Brief description of the drawings
Fig. 1 is the embedded fan-out-type silicon adapter plate structure schematic diagram of embodiment 1；
Fig. 2 is the intermediate structure schematic diagram that step (3) is formed in the preparation method of embodiment 1；
Fig. 3 is the intermediate structure top view that step (4) is formed in the preparation method of embodiment 1；
Fig. 4 is the intermediate structure schematic diagram that step (2) is formed in the package application method of embodiment 1；
Fig. 5 is the structural representation of the package application of embodiment 1；
Fig. 6 is the embedded fan-out-type silicon adapter plate structure schematic diagram of embodiment 2；
Fig. 7 is the intermediate structure top view that step (2) is formed in the preparation method of embodiment 2；
Fig. 8 is the structural representation of the package application of embodiment 2.
Embodiment
It is described in detail below in conjunction with drawings and examples.
Embodiment 1：
A kind of new embedded fan-out-type silicon adapter plate structure towards three-dimensional systematic package application is as shown in figure 1, bag
Silicon substrate 110 made of low-resistance silicon materials (≤0.1 Ω cm) is included, the silicon substrate 110 has a front 000 and a back side
001, front, which is provided with side wall, has the cavity 111 (preferably the bore of cavity 111 is reduced gradually by front to the back side) of certain slope,
The back side is provided with the vertical interconnection architecture for extending to the bottom of cavity 111.The vertical interconnection architecture is formed by following structure：
The back side 001 of silicon substrate 110 is provided with and extends to the bottom of cavity 111 and separate some annular grooves 112, the ring
Fill insulant forms annular insulating barrier 120 in shape groove 112, and the silicon column within the annular inner ring of insulating barrier 120 is formed and led
Electric post 113, that is, some separate conductive poles 113 are formed, and the upper surface of conductive pole 113 is exposed to the bottom of cavity 111
Portion.The front and back of the silicon substrate 110 and the pocket surfaces are provided with insulating barrier 130, wherein the front of the silicon substrate 110
000 and the side wall of the cavity 111 and bottom be provided with the first metal interconnection layer 140, the silicon substrate in insulating barrier 130
110 back side 001 is provided with the second metal interconnection layer 150 in insulating barrier 130.The insulating barrier 130 of front and back is led respectively at described
The electric both ends of the surface opening of post 113, the upper and lower end face of the conductive pole 113 respectively with the gold medal of the first metal interconnection layer 140 and second
Belong to interconnection layer 150 and form Ohmic contact.
The insulating materials of the annular insulating barrier 120 is silica, glass paste, polypropylene (polypropylene)
Or one kind of Parylene (Poly-p-xylene) etc..The insulating barrier 130 be silica, silicon nitride, aluminum oxide, BCB,
One kind of polyimides (PI), glass, polypropylene (polypropylene) or Parylene (Poly-p-xylene) etc..
The preparation method of above-mentioned silicon pinboard is：
(1) low-resistance silicon substrate 110 is provided, the back side 001 of low-resistance silicon substrate 110 carved by technologies such as DRIE, laser
Erosion acquires annular groove 112, is prepared to form silicon column 201；
(2) by either physically or chemically including at least one of PECVD, CVD, PVD, spin coating or spraying, will aoxidize
Silicon, silicon nitride, aluminum oxide, BCB, polyimides (PI), glass paste, polypropylene (polypropylene) or Parylene
Etc. (Poly-p-xylene) at least one insulating materials silicon substrate back 001 and the inwall of annular groove 112 deposit one layer it is fine and close
Insulating barrier 130；
(3) by either physically or chemically including at least one of PECVD, CVD, vacuum glue pouring by silica, nitridation
Silicon, aluminum oxide, BCB, polyimides (PI), glass paste, polypropylene (polypropylene) or Parylene (Poly-p-
) etc. xylene insulating materials is filled up completely with the cavity of annular groove 112, forms annular insulating barrier 120, in annular insulating barrier 120
Silicon column within circle forms conductive pole 113, such as Fig. 2；
(4) DIRE, ICP deep silicon etching are included by dry etching, and wet etching includes the corruption of organic or inorganic wet method
A kind of technology of erosion etc. carries out cavity 111 to the substrate front side 000 and prepared, and its top view is as shown in Figure 3；
(5) by either physically or chemically including at least one of PECVD, CVD, PVD, spin coating or spraying, transferring
Plate upper and lower surface 000,001 and cavity side walls and bottom cover one layer of fine and close insulating barrier 130；
(6) by either physically or chemically including at least one of RIE, plasma etching, wet etching, in silicon substrate
Conductive pole 113 (i.e. silicon column) both ends end of plate 110 realizes that insulating barrier opens a window, and exposes the end surfaces of silicon column two；
(7) the first metal interconnection layer 140 and the second metal are made respectively at the front and back deposited metal of said structure
By PVD sputterings or evaporation and diffusion barrier layer and plating seed layer, then interconnection layer 150, specifically, the way of metal interconnection layer are
Metal conducting layer is formed by process deposits the methods of plating or chemical plating.Wherein diffusion impervious layer be Ta, TaN, TiW etc. at least
One kind, metal conducting layer can be at least one of Cu, Al, Au, Sn.First metal interconnection layer 140 and the second metal interconnection
Layer 150 forms Ohmic contact by the windowing and silicon column upper and lower end face of insulating barrier 130 respectively.
Application of the above-mentioned silicon pinboard in three-dimensional systematic encapsulation comprises the following steps：
(1) some pads of microelectronic chip 3 are placed in cavity 111 upward, the first metal interconnection layer of bottom of cavity 111
140 are electrically connected with the pad of chip 3 by contacting, and are used as viscous glutinous agent 4 by organic material and are fixed in cavity 111
Bottom；Preferably, one kind that glutinous agent 4 is resin glue class etc. is glued；Microelectronic chip 3 is MEMS chip, IC chip etc.
It is at least one；
(2) gap between cavity 111 and microelectronic chip 3, such as Fig. 4 are filled using organic filler 5；Organic filler
5 materials are the one of glass paste, resin, polypropylene (polypropylene) or Parylene (Poly-p-xylene) etc.
Kind；
(3) by either physically or chemically including at least one of PECVD, CVD, PVD, spin coating or spraying in above-mentioned knot
Structure just, the back of the body two sides cover a layer insulating 6；Preferably, insulating barrier 6 is silica, silicon nitride, aluminum oxide, BCB, polyamides Asia
At least one such as amine (PI), glass, polypropylene (polypropylene) or Parylene (Poly-p-xylene)；To insulation
The windowing of layer 6 forms window；
(4) the front deposited metal of said structure makes the 3rd metal interconnection layer 7, specifically, the material of the 3rd metal interconnection layer 7
Material and way refer to the first metal interconnection layer 140 and the second metal interconnection layer 150.3rd metal interconnection layer 7 passes through the insulation
6 window of layer are electrically connected with the first metal interconnection layer 140；
(5) by either physically or chemically including at least one of PECVD, CVD, PVD, spin coating or spraying in above-mentioned knot
One layer of passivation layer 8 of structure front covering；Preferably, passivation layer 8 be silica, silicon nitride, aluminum oxide, BCB, polyimides (PI),
At least one such as glass, polypropylene (polypropylene) or Parylene (Poly-p-xylene)；The windowing shape of passivation layer 8
Into the connector 81 drawn for the 3rd metal interconnection layer 7；
(6) made at the said structure back side made at the window of insulating barrier 6 microbonding ball, micro welded pad, microbonding point etc. be referred to as it is micro-
Welding structure 9 is fixed on the metal interconnecting layer 150 of substrate back 001 second, realizes electrical connection, such as Fig. 5；Preferably, it is described micro-
At least one such as including AgSn, AuSn, CuSn of welding structure 9.
Embodiment 2
A kind of new embedded fan-out-type silicon adapter plate structure towards three-dimensional systematic package application is as shown in fig. 6, bag
Silicon substrate 210 made of high resistant silicon materials (>=1000 Ω cm) is included, the silicon substrate 210 has a front 000 and a back of the body
Face 001, front, which is provided with side wall, to be had the cavity 211 of certain slope (preferably the bore of cavity 211 is contracted gradually by front to the back side
It is small), the back side is provided with the vertical interconnection architecture for extending to the bottom of cavity 211.The vertical interconnection architecture passes through following structure
Formed：The back side of silicon substrate 210, which is provided with, extends to the bottom of cavity 211 and separate some through holes 212, described logical
Fill conductive material and form the conductive pole 220 in hole 212.The front and back of the silicon substrate 210 and the pocket surfaces are provided with exhausted
Edge layer 230, wherein the front 000 of the silicon substrate 210 and the side wall of the cavity 211 and bottom are set on insulating barrier 230
There is the first metal interconnection layer 240, the back side 001 of the silicon substrate 210 is provided with the second metal interconnection layer 250 in insulating barrier 230.
The insulating barrier 230 of front and back respectively at the both ends of the surface opening of conductive pole 220, the upper and lower end face of the conductive pole 220 respectively with
The metal interconnection layer 150 of first metal interconnection layer 140 and second is electrically connected with.
Further, insulating barrier 230, diffusion impervious layer and metal conducting layer are set gradually from outside to inside in the through hole 212,
The diffusion impervious layer and metal conducting layer form the conductive pole 220, wherein the diffusion impervious layer is Ta, TaN, TiW
At least one, the conductive metal layer are Cu, Al, Au, W at least one.The insulating barrier 230 is silica, silicon nitride, oxygen
Change aluminium, BCB, polyimides (PI), glass, polypropylene (polypropylene) or Parylene (Poly-p-xylene) etc.
One kind.
The preparation method of above-mentioned silicon pinboard is：
(1) high resistant silicon substrate 210 is provided, DIRE, ICP deep silicon etching, and wet etching bag are included by dry etching
A kind of technology for including organic or inorganic wet etching etc. is prepared to the progress cavity 211 of the front of high resistant silicon substrate 210 000；
(2) substrate back 001 is performed etching by technologies such as DRIE, laser and acquires small size, silicon of high aspect ratio is led to
Hole (TSV) 212, prepared to form solid or hollow metal TSV, the structure top view of formation is as shown with 7；
(3) by either physically or chemically including at least one of PECVD, CVD, PVD, spin coating or spraying, will aoxidize
Silicon, silicon nitride, aluminum oxide, BCB, polyimides (PI), glass paste, polypropylene (polypropylene) or Parylene
Etc. (Poly-p-xylene) at least one insulating materials descend on a silicon substrate two sides 000,001, the side wall of cavity 211 and bottom with
And the continuous insulating barrier 230 of one layer of densification of TSV side wall depositions；
(4) the first metal interconnection layer 240 and the second metal are made respectively at the front and back deposited metal of said structure
Interconnection layer 250 and solid or hollow metal column is made in deposited metal in through hole 212 to form conductive pole 220.Specifically do
Method is：Evaporation and diffusion barrier layer and plating seed layer, then form metal by process deposits the methods of plating or chemical plating and lead
Electric layer.Wherein diffusion impervious layer is at least one such as Ta, TaN, TiW, metal conducting layer can be in Cu, Al, Au etc. at least
It is a kind of.First metal interconnection layer 240 and the second metal interconnection layer 250 are electrically connected with the upper and lower end face of conductive pole 220 respectively, are realized
Vertical interconnection.In addition, the second metal interconnection layer 250 can also be made in package application further according to demand.
Application reference implementation example 1 of the above-mentioned silicon pinboard in three-dimensional systematic encapsulation, its encapsulating structure with reference to figure 8, with
The difference of embodiment 1 is that embodiment 2 is realized and the first metal interconnection layer by the conductive pole 220 of metal deposit formation
240 and second metal interconnection layer 250 electric connection, the first metal interconnection layer 240 and the pad of chip 3 carry out electricity by contacting
Connection, so as to realize the three-dimensional systematic package application of vertical interconnection and both sides exit.
Above-described embodiment is only of the present utility model a kind of towards the new of three-dimensional systematic package application for further illustrating
Type embeds fan-out-type silicon adapter plate structure, but the utility model is not limited to embodiment, every according to skill of the present utility model
Any simple modification, equivalent change and modification that art is substantially made to above example, each falls within technical solutions of the utility model
Protection domain in.
Claims (7)
- A kind of 1. embedded fan-out-type silicon pinboard of three-dimensional systematic package application, it is characterised in that：Including silicon substrate, the silicon Substrate front side, which is provided with side wall, has the cavity of certain slope, and the back side is provided with the vertical interconnection architecture for extending to the cavity bottom, The vertical interconnection architecture includes some mutual independent conductive poles；The side wall of the positive and described cavity of the silicon substrate and Bottom is provided with the first metal interconnection layer for being connected and making front extraction with the microelectronic chip pad being placed in cavity End；The back side of the silicon substrate is provided with the second metal interconnection layer for making back side exit, first metal interconnection layer First metal interconnection layer is electrically connected with the second metal interconnection layer with the silicon substrate insulation set, the conductive pole respectively With the second metal interconnection layer.
- 2. the embedded fan-out-type silicon pinboard of three-dimensional systematic package application according to claim 1, it is characterised in that：Institute The low-resistance silicon materials that silicon substrate is the Ω cm of resistivity≤0.1 are stated, the silicon substrate back is provided with and extends to the cavity bottom And separate some annular grooves, fill insulant in the annular groove, the silicon column within the annular groove inner ring are formed The conductive pole, the upper and lower side of the silicon column form ohm with first metal interconnection layer and the second metal interconnection layer respectively and connect Touch.
- 3. the embedded fan-out-type silicon pinboard of three-dimensional systematic package application according to claim 2, it is characterised in that：Institute It is the one kind such as silica, glass paste, polypropylene or Parylene to state insulating materials.
- 4. the embedded fan-out-type silicon pinboard of three-dimensional systematic package application according to claim 1, it is characterised in that：Institute The high resistant silicon materials that silicon substrate is the Ω cm of resistivity >=1000 are stated, the silicon substrate back is provided with and extends to the cavity bottom And separate some through holes, the through hole is filled up completely with or non-full filled conductive material forms the conductive pole, described The upper and lower side of conductive pole is electrically connected with first metal interconnection layer and the second metal interconnection layer respectively.
- 5. the embedded fan-out-type silicon pinboard of three-dimensional systematic package application according to claim 4, it is characterised in that：Institute State and set gradually insulating barrier, diffusion impervious layer and metal conducting layer in through hole from outside to inside, the diffusion impervious layer and metal are led Electric layer forms the conductive pole, and the diffusion impervious layer is Ta, TaN, TiW at least one, the conductive metal layer be Cu, Al, Au, W at least one.
- 6. the embedded fan-out-type silicon pinboard of three-dimensional systematic package application according to claim 1, it is characterised in that：Institute State the front and back of silicon substrate and the pocket surfaces are provided with insulating barrier, first metal interconnection layer and the second metal interconnection layer On the insulating barrier, the insulating barrier in the conductive pole both ends of the surface opening with realize first metal interconnection layer, The electric connection of second metal interconnection layer and the conductive pole.
- 7. the embedded fan-out-type silicon pinboard of the three-dimensional systematic package application according to claim 5 or 6, its feature exist In：The insulating barrier is one kind of silica, silicon nitride, aluminum oxide, polyimides, glass, polypropylene or Parylene.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107452689A (en) * | 2017-09-14 | 2017-12-08 | 厦门大学 | The embedded fan-out-type silicon pinboard and preparation method of three-dimensional systematic package application |
| CN109019504A (en) * | 2018-06-22 | 2018-12-18 | 北京时代民芯科技有限公司 | A kind of new producing method of the adjustable interconnection through silicon via of resistance |
| CN112234027A (en) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | 2.5D electronic packaging structure |
| CN113629020A (en) * | 2021-06-25 | 2021-11-09 | 北京大学 | Millimeter wave packaging structure and preparation method thereof |
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2017
- 2017-09-14 CN CN201721177329.0U patent/CN207134348U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107452689A (en) * | 2017-09-14 | 2017-12-08 | 厦门大学 | The embedded fan-out-type silicon pinboard and preparation method of three-dimensional systematic package application |
| CN109019504A (en) * | 2018-06-22 | 2018-12-18 | 北京时代民芯科技有限公司 | A kind of new producing method of the adjustable interconnection through silicon via of resistance |
| CN109019504B (en) * | 2018-06-22 | 2020-02-21 | 北京时代民芯科技有限公司 | Manufacturing method of interconnected silicon through hole with adjustable resistance |
| CN112234027A (en) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | 2.5D electronic packaging structure |
| CN113629020A (en) * | 2021-06-25 | 2021-11-09 | 北京大学 | Millimeter wave packaging structure and preparation method thereof |
| CN113629020B (en) * | 2021-06-25 | 2023-09-19 | 北京大学 | Millimeter wave packaging structure and preparation method thereof |
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