CN206892854U - A kind of mainboard of raising PCIE data channel utilization rates - Google Patents
A kind of mainboard of raising PCIE data channel utilization rates Download PDFInfo
- Publication number
- CN206892854U CN206892854U CN201720415665.8U CN201720415665U CN206892854U CN 206892854 U CN206892854 U CN 206892854U CN 201720415665 U CN201720415665 U CN 201720415665U CN 206892854 U CN206892854 U CN 206892854U
- Authority
- CN
- China
- Prior art keywords
- slot
- lanes
- pcie
- mainboard
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Time-Division Multiplex Systems (AREA)
Abstract
The utility model provides a kind of mainboard of raising PCIE data channel utilization rates, mainboard includes port number and lanes quantity the first slot of identical of root bridge device, the lanes of described bridge device is all connected with the first slot, and all lanes of other PCIE slots contact is linked in sequence on the first slot on respective numbers lanes contact successively；In place signals of the PCH GPIO respectively with each PCIE slots is connected, and is pulled up outside all GPIO signals by resistance R；The signal wire being connected with each slot passes through resistance eutral grounding.The technical solution of the utility model, according to the situation in place of slot equipment, the width of bridge device is configured, bridge device width is obtained maximized utilization rate.
Description
Technical field
The utility model belongs to field of computer technology, more particularly to a kind of master of raising PCIE data channel utilization rates
Plate.
Background technology
On mainboard, PCIE every a data passage, it is called a Lane, by transmission signal Tx and reception signal Rx groups
Into.The PCIE data channel Lane of the processor of different frameworks quantity is different, typically between 16 to 48 Lanes, data
16 Lanes can be configured to one group by passage maximum, 8 Lanes can also be configured to one group, minimum can be by 4
Lanes is configured to one group.After configuration is good, each group can link an outside PCIE device.Processor has been possible to multiple
Bridge device, so that processor one has 16 Lanes bridge device as an example, mainboard can design four kinds of configurations, configure 1 one x16
Slot, either configure 2 two x8 slot or configure 3 one x8 and two x4 slot, or 4 four x4 of configuration
Slot.
It is necessary to which which kind of specifically used configuration selected during motherboard design, design mainboard selectes PCIE with postponing, produces material object
After mainboard, it is not possible to hardware PCIE slots are modified again.If client insert mainboard PCIE device width just and
The Breadth Maximum that PCIE slots are supported is consistent, maximization use could be carried out to PCIE data channel, but mainboard is in client
Applicable cases are numerous, and the situation of PCIE slot access devices is varied, and the limitation for PCIE data channel wastes, and just compares
It is common.Such as the bridge device for having a 16 data passage Lanes of processor, when option and installment 1, one is had on mainboard
Individual width is x16 PCIE slot interfaces, and client may be inserted into width x16 and following PCIE device, when client needs to insert
When width is x1 PCIE device, other 15 data passages will be idle waste, even if needing to meet x1 PCIE again
Equipment can not also be realized；There are the PCIE slot interfaces that two width are x8 when option and installment 2, on mainboard, client may be inserted into
Width x8 and following PCIE device, when it is x1 PCIE device that client, which needs insertion width, two slots, which amount to, 14
Data channel is idle to be wasted, while it is that x16 PCIE devices will insert mainboard that client operates in width if necessary, and
It is irrealizable；There are x8 and two x4 PCIE slot interfaces when option and installment 3, on mainboard, client may be inserted into three
X1 PCIE device is opened, will have 13 data passages are idle to waste, while a width x16 or same can not be accessed on mainboard
When two PCIE devices for opening width x8；There are four PCIE slot interfaces when option and installment 4, on mainboard, client can access four
X1 PCIE device is opened, will have 12 data passages are idle to waste, while the PCIE device that width is x16 or x8 can not insert
Enter mainboard.As can be seen here, PCIE socket designs of mainboard at present, to the PCIE device flexible Application of client, limitation and idle wave
Expense is all than more serious.
Utility model content
For above technical problem, the utility model discloses a kind of mainboard of raising PCIE data channel utilization rates, root
According to the PCIE device width of insertion slot, realize that PCIE data channel utilization rate maximizes.
On the other hand, the technical solution adopted in the utility model is：
A kind of mainboard of raising PCIE data channel utilization rates, it include PCH integrate South Bridge chip, mainboard processor and
The basic input/output modules of BIOS；The data channel lanes of the root bridge device of mainboard processor quantity is n；On mainboard
PCIE slots are m, including port number and lanes quantity the first slot of identical of root bridge device, described bridge device
Lanes be all connected with the first slot, all lanes of other PCIE slots contact is linked in sequence in the first slot successively
On respective numbers lanes contact on；
PCH integrates South Bridge chip and includes m GPIO, respectively GPIO0~GPIOm-1, the GPIO0~GPIOm-1Respectively with respectively
The signal PRSNT1# in place electrical connections of individual PCIE slots, and connected outside all GPIO signals by resistance R and pull-up power supply
Tap into capable pull-up；Pass through resistance eutral grounding with each slot lanes signal wires being connected.
Wherein, BIOS input/output modules are during starting up, the signal PRSNT1# in place obtained according to GPIO,
The quantity of PCIE device is obtained, so as to configure the data channel width of root bridge device.
For current processor, the n is 16 or 8.
Using this technical scheme, PCIE data channel can be fully used as needed, flexibly tackles various PCIE devices
Use.GPIO0 ~ GPIOm-1, the signal in place of each PCIE slots is linked to respectively（PRSNT1#）Above, all GPIO letters
Extra portion is pulled up by resistance R, if all slots do not have an equipment insertion, all GPIO input high levels signals,
If PCIE device is inserted into slot, PRSNT1#, which is dragged down, indicates PCIE device in slot.
As further improvement of the utility model, the PCIE slots on the mainboard include width and are less than the first slot
Second slot, the 3rd slot and the 4th slot, the width of second slot are more than the 3rd slot and the 4th slot, and described second
Slot, the lanes contact of the 3rd slot are linked in sequence on the lanes of the respective width of the first slot contact successively；Institute
Contact of the lanes of the 4th slot contact respectively with the lanes of the respective width of the second slot is stated to be linked in sequence successively.
As further improvement of the utility model, every data passage lanes's of the root bridge device of mainboard processor
Tx and Rx passes through DN the and DP signals and PCIE slot contact portions, DN the and DP signals and PCIE slots of differential signal line
The position lead line of contact is grounded by resistance R.
This technical scheme, per data passage lane, it is made up of Tx and Rx, Tx and Rx signals are all DP（Data
Positive）And DN（Data Negative）Difference signal pair, therefore every lane has four signal lines.Data channel
When having data transfer above lane, what DN and DP were transmitted above is symmetrical rectangle square wave, by every lane DN and DP signals
With the position of slot contact point, lead line is grounded by resistance R, when there is equipment in slot, DN and DP transmission square-wave signals,
Grounding resistance is on signal quality without influence, and when slot does not have equipment, DN and DP signals are grounded by resistance R, to other slot strings
Joining DN the and DP signals to come does not influence.
Preferably, all slot all of the above lanes are grounded by resistance R.
As further improvement of the utility model, the n is 16, and first slot is x16, and second slot is
X8, the 3rd slot and the 4th slot are x4, all lanes of second slot contact respectively successively with the first slot
The 9th article of all contact portions to the 16th article of lanes；All lanes of 3rd slot contact is respectively successively with first
The 5th article of lanes to the 8th articles of lanes of slot all contact portions；All lanes of 4th slot contact difference
Successively with the 5th article of lanes to the 8th articles of lanes of the second slot all contact portions.
After so designing, possess the ability of four kinds of designs of configuration above, may be inserted into the PCIE that 1 width is x16 and set
It is standby, the PCIE device that 2 width are x8 or the equipment that 1 width x8 of insertion and 2 width are x4 are either inserted, or insert
Enter the PCIE device that 4 width are x4 or x1, fully use PCIE data channel, flexibly tackle making for various PCIE devices
With.
As further improvement of the utility model, the PCIE slots on the mainboard include the first slot and second and inserted
Groove, the n are 8, and first slot is x8, and second slot is x4, the lanes of second slot contact respectively according to
Secondary order and the 5th article of lanes to the 8th articles of all contact portions of lanes of the first slot.
The mainboard of above-mentioned raising PCIE data channel utilization rates improves PCIE data channel utilization rates using following steps：
Step S1, start bios program, initialize GPIO, GPIO0 ~ GPIOm-1 is arranged to input function, then read
The data value of GPIO0 ~ GPIOm-1 inputs, obtains the signal PRSNT1# in place of PCIE slots；
The signal PRSNT1# in place of step S2, PCIE slot passes to the basic input/output modules of BIOS, root by GPIO
According to the situation in place of each slot equipment, bios program configures the width of bridge device.
Using this technical scheme, designed by hardware circuit design and bios program, according to the PCIE device of insertion slot
Width, realize that PCIE data channel utilization rate maximizes.In this method, PCIE device number is detected by bios program start process
Amount and width, the data channel width of flexible configuration root bridge device, are allowed to and the external apparatus PC IE data channel width goodnesses of fit
Optimize, fully use the PCIE data channel of root bridge device, while different PCIE device demands are inserted to client and reach maximum
Change and meet.
Further, in step S1, the data value inputted according to GPIO0 ~ GPIOm-1 detects the defeated of GPIO0 ~ GPIOm-1
Enter level conditions；In step S2, if all GPIO0 ~ GPIOm-1 level is high level, all slots are not any
PCIE device is inserted, and the basic input/output modules of BIOS configure the default bandwidth that is configured to of bridge device；As GPIO0 ~ GPIOm-
When low level occurs in 1 level, then there is PCIE device access, the basic input/output modules of BIOS configure the bandwidth of root bridge device,
Connect all PCIE devices and complete to initialize.
Further, the n is 16, m 4, and the PCIE slots on the mainboard include the first slot with a width of x16,
The second slot with a width of x8, with a width of x4 the 3rd slot and the 4th slot；All lanes of second slot contact
Distinguish the 9th article of all contact portions to the 16th article of lanes with the first slot successively；All lanes' of 3rd slot
Distinguish all contact portions with the 5th article of lanes to the 8th articles of lanes of the first slot successively in contact；The institute of 4th slot
Distinguish all contact portions with the 5th article of lanes to the 8th articles of lanes of the second slot successively in the contact for having lanes；It is described
The basic input/output modules of BIOS configure the width of root bridge device in the following ways：
When four slots have equipment, the PRSNT1# of four slots is dragged down, and is configured to x4 x4 x4 x4；
When only first slot has equipment, width configuration x16；
When the first slot and the 3rd slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x4 x4 x4
x4；
When the first slot and the second slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x8 x8；
When the first slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x8 x4 x4；
When only the 3rd slot has equipment, width configuration x4 x4 x4 x4；
When the 3rd slot and the second slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x4 x4 x8；
When the 3rd slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x4 x4 x4
x4；
When only the second slot has equipment, width configuration x8 x8；
When the second slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x8 x4 x4；
When only the 4th slot has equipment, width configuration x8 x4 x4.
Compared with prior art, the beneficial effects of the utility model are：
First, the technical solution of the utility model, designed by hardware circuit design and bios program, according to insertion slot
PCIE device width, realize PCIE data channel utilization rate maximize.PCIE is detected by bios program start process to set
Standby quantity and width, the data channel width of flexible configuration root bridge device, it is allowed to kiss with external apparatus PC IE data channel width
Right optimization, the PCIE data channel of root bridge device is fully used, while different PCIE device demands are inserted to client and reached
Maximize and meet.
Second, the technical solution of the utility model, pass through DN and DP differential signal lines and slot contact point, lead connecting resistance
R is to the mode on ground, the hardware design of innovation, then signal PRSNT1# in place is passed into bios program by GPIO, according to each
The situation in place of slot equipment, allows the width of bios program flexible configuration bridge device, bridge device width is maximumlly made
With rate, the performance of processor is given full play to, fully meets the diversified demand of client.
Brief description of the drawings
Fig. 1 is a kind of attachment structure schematic diagram of the PCIE slots of embodiment of the utility model.
Fig. 2 is the attachment structure schematic diagram of the PCIE slots and PCH and mainboard processor of a kind of embodiment of the utility model.
Embodiment
Preferably embodiment of the present utility model is described in further detail below.
Embodiment 1
So that one of processor has 16 lanes root bridge devices as an example, 16 lanes, minimal configuration is 4 lanes.
As shown in Fig. 1 ~ Fig. 2, the PCIE slots on the mainboard include the first slot 1 with a width of x16, with a width of x8's
Second slot 2, with a width of x4 the 3rd slot 3 and the 4th slot 4；16 lanes of mainboard processor are all linked first
To above the first slot 1, second group of 4 lanes is linked to above the second slot 2, by third and fourth group of 8 lanes chain
It is connected to above the 3rd slot 3, while 4 articles of lanes of the 4th slot is linked to above the 4th slot 4.I.e. described second slot 2
Distinguish the 9th article of all contact portions to the 16th article of lanes with the first slot 1 successively in all lanes contact；Described 3rd
All contacts of 3 all lanes of the slot contact respectively successively with the 5th article of lanes to the 8th articles of lanes of the first slot 1 connect
Connect；Distinguish the 5th article of lanes to the 8th articles of lanes with the second slot 3 successively in all lanes of 4th slot 4 contact
All contact portions.After so designing, possess the first slot 1 of configuration, the second slot 2, the 3rd slot the 3, the 4th above and insert
The ability of 4 four kinds of designs of groove, the PCIE device that 1 width is x16 is may be inserted into, or the PCIE that 2 width of insertion are x8 is set
It is standby, the PCIE device that 4 width of equipment or insertion that 1 width x8 and 2 width are x4 are x4 or x1 is either inserted,
PCIE data channel fully is used, flexibly tackles the use of various PCIE devices.In Fig. 1, the lanes of slot head and the tail illustrate only
Connecting line, other lanes of slot are also so to connect.
As shown in Fig. 2 so that one of processor has 16 lanes bridge device as an example, 4 GPIO are selected, GPIO0 ~
GPIO3, the signal in place of x16 slots, x4 slots, x8 slots, x4 slots is linked to respectively（PRSNT1#）Above, all GPIO
Pulled up outside signal by resistance R, the situation for the slot being wherein connected with GPIO0 is only depicted in Fig. 2, other slots
And so.
If all slots do not have equipment insertion, all GPIO input high levels signals, if PCIE device is inserted
Into slot, PRSNT1#, which is dragged down, indicates PCIE device in slot.
As shown in Fig. 2 per data passage lane, it is made up of Tx and Rx, Tx and Rx signals are all DP（Data
Positive）And DN（Data Negative）Difference signal pair, therefore every lane has four signal lines.Data channel
When having data transfer above lane, what DN and DP were transmitted above is symmetrical rectangle square wave, by every lane DN and DP signals
With the position of slot contact point, lead line is grounded by resistance R, when there is equipment in slot, DN and DP transmission square-wave signals,
Grounding resistance is on signal quality without influence, and when slot does not have equipment, DN and DP signals are grounded by resistance R, to other slot strings
Joining DN the and DP signals to come does not influence.First slot, the second slot, the 3rd slot, the 4th slot all of the above lanes
It is grounded by resistance R.
The basic input/output modules of BIOS in the mainboard of above-mentioned raising PCIE data channel utilization rates of the present utility model
Using following steps configure the width of bridge device：
So that one of processor has 16 lanes bridge device as an example, after bios program starts, initialize first
GPIO, GPIO0 ~ GPIO3 is arranged to input function, then the data value of reading GPIO0 ~ GPIO3 inputs, detection GPIO0 ~
GPIO3 incoming level situation, if all level are high level, all slots do not have any equipment to insert, and bridge is set
Standby to be configured to give tacit consent to width configuration, such as x4x4x4x4 configurations, when there is equipment access, situation is relatively more, due to GPIO with
It is corresponding during PRSNT# signals, just illustrated with PRSNT# signals, more understood.
1）When four slots have equipment, four slot PRSNT1# are dragged down, and are configured to x4x4x4x4；
2）When only first slot has equipment, width configuration x16；
3）When first slot and second slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to
x4x4x4x4；
4）When first slot and the 3rd slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to
x8x8；
5）When first slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to
x8x4x4；
6）When only second slot has equipment, width configuration x4x4x4x4；
7）When second slot and the 3rd slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to
x4x4x8；
8）When second slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to
x4x4x4x4；
9）When only the 3rd slot has equipment, width configuration x8x8；
10）When the 3rd slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to
x8x4x4；
11）When only the 4th slot has equipment, width configuration x8x4x4；
All slot insertion equipment situations, the width configuration situation of root bridge device are covered above.Configure bridge device
After width, start to link PCIE device, and carry out Initialize installation, complete PCIE device function.
Involved Essential Terms are explained as follows in the utility model：
BIOS (Basic Input Output System)：Basic input output system, it is mainly used in computer booting
During various hardware devices initialization and detection.
PCH (Platform Controller Hub)：The integrated south bridge of Intel Company.
PCIE（PCI-Express）：A kind of high-speed serial bus interfacing standard.
GPIO（General Purpose Input Output）：Universal input/output.
Above content is to combine specific preferred embodiment further detailed description of the utility model, it is impossible to
Assert that specific implementation of the present utility model is confined to these explanations.For the ordinary skill of the utility model art
For personnel, without departing from the concept of the premise utility, some simple deduction or replace can also be made, should all be regarded
To belong to the scope of protection of the utility model.
Claims (5)
- A kind of 1. mainboard of raising PCIE data channel utilization rates, it is characterised in that：It includes PCH and integrates South Bridge chip, mainboard Processor and the basic input/output modules of BIOS；The data channel lanes of the root bridge device of mainboard processor quantity is n；It is main PCIE slots on plate are m, including port number and lanes quantity the first slot of identical of root bridge device, described The lanes of bridge device is all connected with the first slot, and all lanes of other PCIE slots contact is linked in sequence successively On the contact of respective numbers lanes on one slot；PCH integrates South Bridge chip and includes m GPIO, respectively GPIO0~GPIOm-1, the GPIO0~GPIOm-1Respectively with it is each The signal PRSNT1# in place electrical connections of PCIE slots, and be connected outside all GPIO signals by resistance R with pull-up power supply Pulled up；Pass through resistance eutral grounding with each slot lanes signal wires being connected.
- 2. the mainboard of raising PCIE data channel utilization rates according to claim 1, it is characterised in that：On the mainboard PCIE slots include the second slot, the 3rd slot and the 4th slot that width is less than the first slot, the width of second slot More than the 3rd slot and the 4th slot, second slot, the 3rd slot lanes contact be linked in sequence successively first insert On the lanes of the respective width of groove contact；The lanes of 4th slot contact respective width with the second slot respectively Lanes contact be linked in sequence successively.
- 3. the mainboard of raising PCIE data channel utilization rates according to claim 2, it is characterised in that：Mainboard processor DN and DP signals and PCIE slot contact of every data passage lanes of the root bridge device Tx and Rx by differential signal line Connection, DN the and DP signals and the position lead line of PCIE slots contact are grounded by resistance R.
- 4. the mainboard of raising PCIE data channel utilization rates according to claim 3, it is characterised in that：The n is 16, institute It is x16 to state the first slot, and second slot is x8, and the 3rd slot and the 4th slot are x4, the institute of second slot Distinguish the 9th article of all contact portions to the 16th article of lanes with the first slot successively in the contact for having lanes；Described 3rd inserts Distinguish all contact portions with the 5th article of lanes to the 8th articles of lanes of the first slot successively in all lanes of groove contact；Institute Touched successively with all of the 5th article of lanes to the 8th articles of lanes of the second slot respectively the contact for stating all lanes of the 4th slot Point connection.
- 5. the mainboard of raising PCIE data channel utilization rates according to claim 1, it is characterised in that：The n is 8, institute Stating the PCIE slots on mainboard includes the first slot and the second slot, and first slot is x8, and second slot is x4, institute Distinguish the 5th article of lanes to the 8th articles of all contacts of lanes of order and the first slot successively in the contact for stating the lanes of the second slot Connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720415665.8U CN206892854U (en) | 2017-04-19 | 2017-04-19 | A kind of mainboard of raising PCIE data channel utilization rates |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720415665.8U CN206892854U (en) | 2017-04-19 | 2017-04-19 | A kind of mainboard of raising PCIE data channel utilization rates |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206892854U true CN206892854U (en) | 2018-01-16 |
Family
ID=61323381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720415665.8U Active CN206892854U (en) | 2017-04-19 | 2017-04-19 | A kind of mainboard of raising PCIE data channel utilization rates |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206892854U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113220618A (en) * | 2021-04-23 | 2021-08-06 | 山东英信计算机技术有限公司 | Bit width regulation and control method, system and medium |
-
2017
- 2017-04-19 CN CN201720415665.8U patent/CN206892854U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113220618A (en) * | 2021-04-23 | 2021-08-06 | 山东英信计算机技术有限公司 | Bit width regulation and control method, system and medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106951383A (en) | The mainboard and method of a kind of raising PCIE data channel utilization rates | |
| CN100468378C (en) | SPI apparatus telecommunication circuit | |
| US9043528B2 (en) | Bridge between a peripheral component interconnect express interface and a universal serial bus 3.0 device | |
| GB2450591A (en) | USB port and plug that uses the PCI Express interface data transfer specification by having two pairs of data lines. | |
| EP2987087A1 (en) | Device, method and system for operation of a low power phy with a pcie protocol stack | |
| CN207408936U (en) | A kind of multiplex roles PCIE device adapter | |
| CN208188815U (en) | BMC module system | |
| CN103577362B (en) | Method for improving data transmission and related computer system | |
| CN204576500U (en) | A kind of usb communication circuit of compatible I2C communication and system | |
| CN211427337U (en) | Computer mainboard based on explain majestic treaters | |
| CN107480085A (en) | Multiplex roles integrated test system | |
| CN206892854U (en) | A kind of mainboard of raising PCIE data channel utilization rates | |
| US20110106975A1 (en) | Data transfer apparatus | |
| CN204480237U (en) | A kind of connector, universal serial bus device and intelligent terminal | |
| CN205809774U (en) | A kind of server and the server master board of inside thereof | |
| CN105354165A (en) | PCIE network card and server system | |
| US8954623B2 (en) | Universal Serial Bus devices supporting super speed and non-super speed connections for communication with a host device and methods using the same | |
| CN112821156B (en) | Electronic tags chip and TYPE-C data line | |
| CN108536633A (en) | A kind of interface circuit and terminal of plug and play OTG equipment | |
| CN211628236U (en) | Bandwidth configuration device of PCIE Slimline connector | |
| CN210924562U (en) | Backboard communication device | |
| CN210123977U (en) | Relay cable and augmented reality system | |
| CN210324198U (en) | Embedded core board and equipment | |
| CN107704403B (en) | Device and method for optimizing signal transmission of main back plate | |
| CN207319794U (en) | A kind of I for strengthening antijamming capability2C buses |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |