CN206878690U - Total harmonic distortion optimization circuit, drive control device and switch power supply system - Google Patents
Total harmonic distortion optimization circuit, drive control device and switch power supply system Download PDFInfo
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Abstract
The utility model discloses a kind of total harmonic distortion optimization circuit, drive control device and switch power supply system.Circuit includes：Compensate current generating unit, it is coupled to the inductance of switch power supply system, the sampled voltage that electric current in each switch periods of the power tube in switch power supply system, receiving sampling inductance obtains, so as to obtain crest voltage according to the peak point current of inductance to generate total harmonic distortion compensation electric current；Ramp voltage generation unit, for compensating electric current and a reference current according to total harmonic distortion, ramp voltage is generated, further to adjust the ON time of power tube；Wherein, the peak point current of inductance is higher, and total harmonic distortion compensation electric current is bigger, and the ON time of power tube is also longer, so as to reduce the total harmonic distortion of switch power supply system.The utility model reduces the total harmonic distortion of switch power supply system, improves power factor value, so as to improve the efficiency of switch power supply system.
Description
Technical Field
The utility model relates to a power electronic technology field especially relates to total harmonic distortion optimization circuit, drive controller and switching power supply system suitable for AC/DC switching power supply system.
Background
The Power Factor (PF) is an important technical data of power electronic systems, and is a coefficient for measuring the efficiency of power electronic equipment, and more power electronic equipment requires higher power factor. The power factor PF and the total harmonic distortion THD have the following relationship:
wherein,for the phase shift between the input voltage and the input current, at a phase shift factorWhen unchanged, the power factor can be improved by reducing the total harmonic distortion THD.
The high power factor AC/DC switching power supply generally adopts peak current control or constant conduction time control, and the two are essentially the same.
Referring to fig. 1-2, fig. 1 is a schematic diagram of a constant on-time control circuit of a conventional typical BUCK architecture, and fig. 2 is a waveform diagram of an input current of the circuit shown in fig. 1 varying with time.
The driving controller 11 controls the power transistor M0 to turn on and off. Due to the inherent characteristics of the BUCK architecture, when the power transistor M0 is turned on, current flows into the AC input terminal at the rear stage, and when the power transistor M0 is turned off, no current flows into the AC input terminal at the rear stage, that is, the input current at the AC terminal is a pulse current. The AC input current Iin during a switching cycle is:
wherein, Ipk is the peak current of the inductor, Ton is the conduction time of the power tube, and T is the switching period.
The critical conduction mode inductor peak current Ipk and duty cycle Ton/T are calculated as follows:
substituting the formulas (2) and (3) into the formula (1) to obtain:
where Vin is the input voltage, Vo is the output voltage, L is the inductance of inductor L0, and θ is the phase angle of the sine wave of the input voltage.
According to equation (4), the waveform of the input current Iin at the AC terminal varies with time t as shown in fig. 2, where the abscissa is time t (unit: millisecond) and the ordinate is input voltage Vin (unit: milliamp). As can be seen from fig. 2, at a set input voltage Vin and output voltage Vo, the input current Iin is not an ideal sine wave, and there is a large total harmonic distortion.
Therefore, it is desirable to provide a total harmonic distortion optimization method, so that the input current is closer to an ideal sine wave, the total harmonic distortion of the switching power supply is reduced, the power factor value is increased, and the efficiency of the switching power supply is improved.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a total harmonic distortion optimization circuit, drive controller and switching power supply system changes the power tube on-time through sampling inductance peak current for input current more is close ideal sinusoidal wave, realizes reducing switching power supply's total harmonic distortion, and the raising power is because of numerical value, thereby improves switching power supply's efficiency.
In order to achieve the above object, the utility model provides a total harmonic distortion optimization circuit is applicable to switching power supply system, switching power supply system includes: an inductor and a power tube; the circuit comprises: a compensation current generation unit and a ramp voltage generation unit; the compensation current generation unit is coupled to the inductor and used for receiving sampling voltage obtained by sampling the current of the inductor in each switching period of the power tube, so that peak voltage is obtained according to the peak current of the inductor to generate total harmonic distortion compensation current; the ramp voltage generating unit is used for generating a ramp voltage according to the total harmonic distortion compensation current and a reference current so as to further adjust the conduction time of the power tube; the higher the peak current of the inductor is, the larger the total harmonic distortion compensation current is, and the longer the conduction time of the power tube is, so that the total harmonic distortion of the switching power supply system is reduced.
In order to achieve the above object, the utility model also provides a drive controller is applicable to switching power supply system, switching power supply system includes: an inductor and a power tube; the drive controller includes: transconductance amplifier, voltage comparator, logic unit, drive circuit, signal phase inverter and the utility model discloses a total harmonic distortion optimization circuit; the transconductance amplifier has a positive input end for receiving a reference voltage, a negative input end for receiving a sampling voltage obtained by sampling a current of the inductor, and an output end connected to the floating ground end through a compensation capacitor, and is used for converting a difference value between the reference voltage and the sampling voltage into a current to be injected into the compensation capacitor to generate a compensation voltage; the positive input end of the voltage comparator is used for receiving the ramp voltage generated by the total harmonic distortion optimization circuit, the negative input end of the voltage comparator is used for receiving the compensation voltage, and the output end of the voltage comparator outputs a turn-off pulse of the power tube; the logic unit is used for receiving the turn-off pulse, and outputting a logic signal for controlling the conduction of the power tube after logic operation; the driving circuit is used for receiving the logic signal and driving the power tube to be conducted; the signal phase inverter is used for receiving the logic signal, and feeding the logic signal back to the total harmonic distortion optimization circuit after phase inversion; the higher the peak current of the inductor is, the larger the total harmonic distortion compensation current is, and the longer the conduction time of the power tube is, so that the total harmonic distortion of the switching power supply system is reduced.
In order to achieve the above object, the utility model also provides a switching power supply system, include: the power supply comprises an input voltage end, an output voltage end, a sampling resistor, a compensation capacitor, an inductor and a power tube, wherein the drain electrode of the power tube is electrically connected with the input voltage end, and the source electrode of the power tube is electrically connected with the output voltage end through the sampling resistor and the inductor; the system further comprises the drive controller of the present invention; the transconductance amplifier of the driving controller has a positive input end for receiving a reference voltage, a negative input end connected to the floating ground end through the sampling resistor, and an output end connected to the floating ground end through the compensation capacitor; the total harmonic distortion optimization circuit of the drive controller is coupled to the inductor and used for receiving sampling voltage obtained by sampling current of the inductor in each switching period of the power tube, so that peak voltage is obtained according to the peak current of the inductor to generate total harmonic distortion compensation current, ramp voltage is generated according to the total harmonic distortion compensation current and reference current, and the conduction time of the power tube is adjusted; the driving circuit of the driving controller is electrically connected with the grid electrode of the power tube; the higher the peak current of the inductor is, the larger the total harmonic distortion compensation current is, and the longer the conduction time of the power tube is, so that the total harmonic distortion of the switching power supply system is reduced.
The utility model has the advantages of, change power tube on-time through sampling inductance peak current, the peak current Ipk of inductance is higher, total harmonic distortion compensating current ith is big more, the on-time Ton of power tube is also longer to reduce switching power supply system's total harmonic distortion, make input current more be close ideal sinusoidal wave, reduced switching power supply system's total harmonic distortion, improved power because of numerical value, thereby improved switching power supply system's efficiency.
Drawings
FIG. 1 is a schematic diagram of a constant on-time control circuit of a conventional BUCK architecture;
FIG. 2 is a waveform of the input current of the circuit of FIG. 1 over time;
fig. 3 is a schematic diagram of the total harmonic distortion optimization circuit according to the present invention;
fig. 4 is a schematic diagram of a first embodiment of a switching power supply system according to the present invention;
FIG. 5 is a waveform of the peak inductor current in the embodiment of FIG. 4 during one half of the power frequency cycle;
FIG. 6 is a schematic diagram of one embodiment of a peak voltage sample and hold module of the embodiment shown in FIG. 4;
FIG. 7 is a waveform diagram of the related signals in the embodiment of FIG. 6;
FIG. 8 is a schematic diagram of one embodiment of a voltage/current conversion module of the embodiment shown in FIG. 4;
FIG. 9 is a waveform diagram of the input current over time for the embodiment shown in FIG. 4;
fig. 10 is a schematic diagram of a second embodiment of a switching power supply system according to the present invention;
fig. 11 is a schematic diagram of a switching power supply system according to a third embodiment of the present invention;
fig. 12 is a schematic diagram of an embodiment of a clamp current generation module in the embodiment shown in fig. 11.
Detailed Description
The following describes the total harmonic distortion optimization circuit, the driving controller, and the switching power supply system provided by the present invention in detail with reference to the accompanying drawings.
Referring to fig. 3, the present invention provides a schematic diagram of a total harmonic distortion optimization circuit. The total harmonic distortion optimization circuit is suitable for a switching power supply system, and the switching power supply system comprises: inductor L0 and power tube M0. The total harmonic distortion optimization circuit comprises: a compensation current generation unit 32 and a ramp voltage generation unit 34.
The compensation current generation unit 32 is coupled to the inductor L0, and configured to receive a sampled voltage CS obtained by sampling a current of the inductor L0 in each switching cycle of the power transistor M0, so as to obtain a peak voltage CSpk according to a peak current Ipk of the inductor L0 to generate an thd compensation current.
The RAMP voltage generating unit 34 is configured to generate a RAMP voltage RAMP according to the total harmonic distortion compensation current Ithd and a reference current Iref, so as to further adjust the on-time Ton of the power transistor M0. The higher the peak current Ipk of the inductor L0, the higher the total harmonic distortion compensation current Ithd, the longer the on-time Ton of the power tube M0, thereby reducing the total harmonic distortion of the switching power supply system.
The conduction time of the power tube is changed by sampling the peak current of the inductor, so that the input current is closer to an ideal sine wave, the total harmonic distortion of the switching power supply system is reduced, the power factor value is improved, and the efficiency of the switching power supply system is improved.
Referring to fig. 4-9, wherein fig. 4 is a schematic diagram of a first embodiment of a switching power supply system according to the present invention; FIG. 5 is a waveform of the peak inductor current in the embodiment of FIG. 4 during one half of the power frequency cycle; FIG. 6 is a schematic diagram of one embodiment of a peak voltage sample and hold module of the embodiment shown in FIG. 4; FIG. 7 is a waveform diagram of the related signals in the embodiment of FIG. 6; FIG. 8 is a schematic diagram of one embodiment of a voltage/current conversion module of the embodiment shown in FIG. 4; fig. 9 is a waveform diagram of the input current over time for the embodiment shown in fig. 4. In this embodiment, the switching power supply system is an AC/DC switching power supply system with a BUCK topology; it should be noted that the present invention is not limited to be used in BUCK topology, and can also be used in switching power supply systems with topologies such as BUCK-BOOST and FLYBACK.
In this embodiment, the switching power supply system includes: the circuit comprises an input voltage end, an output voltage end, a sampling resistor Rcs, a compensation capacitor Ccomp, an inductor L0 and a power tube M0; the system further includes a drive controller 40.
As shown in fig. 4, an AC input AC is input to the bus capacitor Cin through the rectifier bridge circuit 41 to obtain an input voltage Vin, which is input to the input voltage terminal, and the input voltage terminal is connected to the drain of the power transistor M0. The grid of the power tube M0 is connected with the driving controller 40, and the source of the power tube M0 is electrically connected with the output voltage end through the sampling resistor Rcs and the inductor L0; specifically, the source of the power transistor M0 is connected to one end of the sampling resistor Rcs and the cathode of the freewheeling diode D0; one end of the sampling resistor Rcs is simultaneously connected to the drive controller 40, and the other end of the sampling resistor Rcs is connected to the floating ground end and one end of the inductor L0, and is simultaneously connected to the drive controller 40 through the compensation capacitor Ccomp; the anode of the freewheeling diode D0 is grounded; the other end of the inductor L0 is connected with an output voltage end. The output voltage is terminated with the output capacitor C0 and the load 49, and the output voltage V0 is provided for the output capacitor C0 and the load.
The driving controller 40 includes: transconductance amplifier Gm, voltage comparator 402, logic unit 403, driving circuit 404, signal inverter 405, and total harmonic distortion optimization circuit 401.
The positive input end of the transconductance amplifier Gm is used for receiving a reference voltage VREF, the negative input end of the transconductance amplifier Gm is connected with the floating ground end through the sampling resistor Rcs and is used for receiving a sampling voltage CS obtained by sampling the current of the inductor L0 by the sampling resistor Rcs, and the output end of the transconductance amplifier Gm is connected with the floating ground end through the compensation capacitor Ccomp; the transconductance amplifier Gm is used for converting the difference value between the reference voltage VREF and the sampling voltage CS into current to be injected onto the compensation capacitor Ccomp to generate a compensation voltage COMP; when the system is in steady-state operation, the compensation voltage COMP is a direct current level.
The total harmonic distortion optimization circuit 401, coupled to the inductor L0, is configured to receive a sampled voltage obtained by sampling a current of the inductor L0 in each switching cycle of the power transistor M0, so as to obtain a peak voltage CSpk according to a peak current Ipk of the inductor L0 to generate a total harmonic distortion compensation current Ithd, and generate a RAMP voltage RAMP according to the total harmonic distortion compensation current Ithd and a reference current Iref. In this embodiment, specifically, the compensation current generating unit 32 of the total harmonic distortion optimizing circuit 401 is connected to the inductor L0 through a sampling resistor Rcs, and configured to receive a sampling voltage CS obtained by sampling a current of the inductor L0 in each switching cycle of the power transistor M0, so as to obtain a peak voltage CSpk according to a peak current Ipk of the inductor L0 to generate a total harmonic distortion compensation current Ithd; the RAMP voltage generating unit 34 of the total harmonic distortion optimizing circuit 401 is configured to generate a RAMP voltage RAMP according to the total harmonic distortion compensating current Ithd and a reference current Iref; the on-time Ton of the power transistor M0 is adjusted according to the generated RAMP voltage RAMP in combination with other components of the driving controller. The higher the peak current Ipk of the inductor L0, the higher the total harmonic distortion compensation current Ithd, the longer the on-time Ton of the power tube M0, thereby reducing the total harmonic distortion of the switching power supply system.
The positive input end of the voltage comparator 402 is configured to receive the RAMP voltage RAMP generated by the total harmonic distortion optimization circuit, the negative input end of the voltage comparator is configured to receive the compensation voltage COMP, and the output end of the voltage comparator outputs the OFF pulse OFF _ pulse of the power transistor M0. After the RAMP voltage RAMP and the compensation voltage COMP are compared, an OFF signal OFF _ pulse of the power tube M0 is generated, and a time period from the RAMP voltage RAMP rising from the initial value RAMP to the compensation voltage COMP being equal to the on time Ton of the power tube M0 is obtained.
The logic unit 403 is configured to receive the OFF pulse OFF _ pulse of the power transistor M0, and output a logic signal GATE _ ON for controlling the power transistor M0 to be turned ON after logic operation. When GATE _ ON is high, the power transistor M0 is ON; when GATE _ ON is low, power transistor M0 is off.
The driving circuit 404 is electrically connected to the GATE of the power transistor M0, and is configured to receive a logic signal GATE _ ON for controlling the conduction of the power transistor M0, and drive the power transistor M0 to conduct. After the GATE _ ON is input to the driving circuit 404, the GATE of the power transistor M0 is directly driven, and when the GATE _ ON is at a high level, the power transistor M0 is turned ON; when GATE _ ON is low, power transistor M0 is off.
The signal inverter 405 is configured to receive a logic signal GATE _ ON for controlling the conduction of the power transistor M0, and feed back the logic signal GATE _ ON to the total harmonic distortion optimization circuit 401 after inverting the logic signal GATE _ ON.
In this embodiment, the compensation current generation unit 32 of the total harmonic distortion optimization circuit 401 further includes: a peak voltage sample-and-hold module 321 and a voltage/current conversion module 322. The peak voltage sample-and-hold module 321 is configured to receive an OFF pulse OFF _ pulse of the power transistor M0 and a logic signal GATE _ ON for controlling the power transistor M0 to be turned ON, and at the same time, is electrically connected to the inductor L0 through a sampling resistor Rcs, and receives a sampling voltage CS obtained by sampling a current of the inductor L0 by the sampling resistor Rcs in each switching period of the power transistor M0, so as to obtain and hold a peak voltage CSpk according to a peak current Ipk of the inductor L0. The voltage/current conversion module 322 is configured to receive the peak voltage CSpk and convert the peak voltage CSpk into a total harmonic distortion compensation current Ithd.
As shown in fig. 5, the abscissa is time t, the ordinate is input voltage Vin, the solid line is the waveform of the peak current of the inductor L0 in a half power frequency period, and the dotted line is the envelope of the peak current of the inductor L0. As can be seen from fig. 5, the higher the input voltage Vin, the larger the peak current Ipk of the inductor L0.
One implementation of the peak voltage sample-and-hold module 321 is shown in fig. 6, and in the embodiment shown in fig. 6, the peak voltage sample-and-hold module 321 includes: a first inverter 61, an and gate 62, a second inverter 63, a first hold switch S61, a first sample-and-hold capacitor C61, a second hold switch S62, and a second sample-and-hold capacitor C62.
The first inverter 61 is configured to receive and invert the OFF pulse OFF _ pulse of the power transistor M0. And GATE 62, configured to receive the logic signal GATE _ ON for controlling the power transistor M0 to be turned ON and the inverted off signal, perform an and operation, and output a first control signal T61. The second inverter 63 is configured to receive the first control signal T61, perform inversion, and output a second control signal T62. The first end of the first holding switch S61 is used for receiving a sampling voltage CS obtained by sampling the current of the inductor L0 by the sampling resistor Rcs, the control end is used for receiving a first control signal T61, and the second end is connected to the floating ground end through the first sampling holding capacitor C61 and is also electrically connected to the first end of the second holding switch S62. A second hold switch S62, having a control terminal for receiving a second control signal T62, and a second terminal electrically connected to the floating ground terminal through a second sample-and-hold capacitor C62 and to the output terminal of the peak voltage sample-and-hold module. Wherein, in each switching period of the power transistor M0, the sampling voltage CS passes through the first holding switch S61, the first sample-and-hold capacitor C61, the second holding switch S62 and the second sample-and-hold capacitor C62, so as to obtain a peak voltage CSpk according to a peak current Ipk of the inductor L0 at the end of the switching period and hold the peak voltage CSpk on the second sample-and-hold capacitor C62, and the peak voltage CSpk is output through an output terminal of the peak voltage sample-and-hold module.
As shown in fig. 7, the peak voltage sample-and-hold module samples and holds the peak current of the inductor L0 in each switching period, so as to obtain a peak voltage CSpk signal. Specifically, after the OFF pulse OFF _ pulse output by the voltage comparator 402 of the driving controller 40 is inverted by the first inverter 61, and then the OFF pulse OFF _ pulse is and-operated with the GATE _ ON signal output by the logic unit 403 of the driving controller 40, so as to obtain the control signal T61 of the first holding switch S61; the control signal T61 is inverted by the second inverter 63 to obtain the control signal T62 of the second hold switch S62. When the power tube M0 is turned on, the sampling voltage CS is the product of the current of the inductor L0 and the resistance of the sampling resistor Rcs, and the sampling voltage CS is zero at other times. The sampled voltage CS passes through S61, C61, S62, and C62, and the peak voltage CSpk of the sampled voltage CS is held on the capacitor C62.
One implementation of the voltage/current conversion module 322 is shown in fig. 8, and in the embodiment shown in fig. 8, the voltage/current conversion module 322 includes: a first operational amplifier Amp1, a first MOS transistor M81, a first current mirror 802, and a second current mirror 803.
A positive input terminal of the first operational amplifier Amp1 is configured to receive the peak voltage CSpk output by the peak voltage sample-and-hold module 321, a negative input terminal of the first operational amplifier Amp is electrically connected to the first terminal of the first MOS transistor M81 and is also connected to the floating ground terminal through a first resistor R81, and an output terminal of the first operational amplifier Amp is electrically connected to the control terminal of the first MOS transistor. A second terminal of the first MOS transistor M81 is electrically connected to the first terminal of the first current mirror 801. The second terminal of the first current mirror 801 is used for receiving the VDD voltage, and the output terminal is electrically connected to the first terminal of the second current mirror 802. A second current mirror 802, a second terminal of which is connected to the floating ground, and an output terminal of which generates a total harmonic distortion compensation current Ithd; the thd compensation current flows to the floating ground through the output terminal of the second current mirror 802.
In the embodiment shown in fig. 8, the first MOS transistor M81 is a first NMOS transistor, wherein the source of the NMOS transistor is used as the first terminal, the drain of the NMOS transistor is used as the second terminal, and the gate of the NMOS transistor is used as the control terminal. The first current mirror 801 adopts a first PMOS transistor M82 and a second PMOS transistor M83 which share a gate, wherein a source of the first PMOS transistor M82 and a gate of the first PMOS transistor M82 and a gate of the second PMOS transistor M83 share a first end, a drain of the first PMOS transistor M82 and a drain of the second PMOS transistor M83 share a second end, and a source of the second PMOS transistor M83 serves as an output end. The second current mirror 802 adopts a second NMOS transistor M84 and a third NMOS transistor M85 which share a gate, wherein a drain of the second NMOS transistor M84, a gate of the second NMOS transistor M84, and a gate of the third NMOS transistor M85 share a first terminal, a source of the second NMOS transistor M84 and a source of the third NMOS transistor M85 share a second terminal, and a drain of the third NMOS transistor M85 serves as an output terminal. That is, the thd current flows to the floating ground through the drain of the third NMOS transistor M85.
Specifically, after the peak voltage sample-and-hold module 321 obtains the peak voltage CSpk reflecting the peak current signal of the inductor L0, the CSpk is input into the voltage/current conversion module 322 to generate the total harmonic distortion compensation current Ithd. The CSpk is input to the positive input end of the first operational amplifier Amp1, the first operational amplifier Amp1 is connected to a negative feedback form, the negative input end of the first operational amplifier Amp1 is connected to the source electrode of the first NMOS transistor M81, and is also connected to one end of the first resistor R81. According to the virtual short principle of the operational amplifier, the voltage drop on R81 is CSpk, so that current CSpk/R81 is generated, and the current passes through a first current mirror consisting of PMOS tubes M82 and M83; assuming that the mirror ratio of the first current mirror is K1, the current flowing through M83 is K1 × CSpk/R2, and the current also passes through the second current mirror composed of NMOS transistors M84 and M85, and assuming that the mirror ratio of the second current mirror is K2, the current flowing through M85 is the total harmonic distortion compensation current Ithd.
The total harmonic distortion compensation current ith is:
Ithd＝K1*K2*CSpk/R81＝K1*K2*Ipk*Rcs/R81 (5)
wherein, Ithd is total harmonic distortion compensation current, K1 is a mirror ratio of the first current mirror, K2 is a mirror ratio of the second current mirror, CSpk is a peak voltage obtained by sampling a peak current of the inductor, Ipk is a peak current of the inductor, Rcs is a resistance value of the sampling resistor, and R81 is a resistance value of the first resistor. As can be seen from equation (5), the total harmonic distortion compensation current Ithd is approximately proportional to the peak current Ipk of the inductor L0.
With continuing reference to fig. 4, in the embodiment shown in fig. 4, the ramp voltage generating unit 34 further includes: a first charging capacitor C1 and a first control switch S1. A first charging capacitor C1, having one end electrically connected to the charging current input terminal Q1 and the other end connected to the floating ground, for generating a RAMP voltage RAMP according to the charging current; wherein the charging current is the difference between the reference current Iref and the total harmonic distortion compensation current Ithd. A first control switch S1, having a first end electrically connected to the charging current input end Q1 and a second end for receiving the RAMP voltage initial value RAMPiniThe control end is used for receiving a logic signal GATE _ ON which is inverted and controls the conduction of the power tube M0; the first terminal of the first control switch is also used as the output terminal of the RAMP voltage generating unit 34 for outputting the generated RAMP voltage RAMP. That is, the charging current of the RAMP voltage generating unit 34 is (Iref-Ithd), and the slope of the output RAMP voltage RAMP of the RAMP voltage generating unit 34 is (Iref-Ithd)/C1.
The RAMP voltage RAMP signal without the compensation for the total harmonic distortion is a RAMP signal with a fixed slope, while the RAMP voltage RAMP signal with the compensation for the total harmonic distortion is a RAMP signal with a nonlinear non-fixed slope. The on-time Ton of the power transistor M0 with total harmonic distortion compensation can be expressed by the following formula:
Ton＝C1*(COMP-RAMPini)/(Iref-Ithd) (6)
wherein Ton is the conduction time of the power transistor M0, C1 is the capacitance of the first charging capacitor, COMP is the compensation voltage of the switching power supply system, RAMPiniFor the initial value of the ramp voltage, Iref is the reference current, and Ithd is the total harmonic distortion compensation current.
The formula (6) is introduced into the formula (4) to obtain:
as can be seen from fig. 5, equation (5), equation (6), and equation (7), in a power frequency cycle, the higher the input voltage Vin is, the higher the peak current Ipk of the inductor L0 is, and thus the larger the total harmonic distortion compensation current Ithd is, the longer the on-time Ton of the power tube M0 is, so that the input current Iin with total harmonic distortion compensation is closer to an ideal sine wave.
As shown in fig. 9, where the abscissa is time t (unit: msec), the ordinate is input voltage Vin (unit: ma), the solid line is the waveform of input current Iin with total harmonic distortion compensation, and the dotted line is the waveform of input current Iin without total harmonic distortion compensation. As can be seen from fig. 9, the input current Iin waveform with total harmonic distortion compensation is closer to an ideal sine wave. The measured THD of the system with total harmonic distortion compensation is also significantly lower than the THD of the system without total harmonic distortion compensation.
Switching power supply system, change power tube on-time through sampling inductance peak current, the peak current Ipk of inductance is higher, total harmonic distortion compensating current ith is big more, the on-time Ton of power tube is also longer to reduce switching power supply system's total harmonic distortion, make input current more be close ideal sinusoidal wave, reduced switching power supply system's total harmonic distortion, improved power because of numerical value, thereby improved switching power supply system's efficiency.
Referring to fig. 10, a schematic diagram of a second embodiment of a switching power supply system according to the present invention; in this embodiment, the switching power supply system is an AC/DC switching power supply system with a FLYBACK topology. The difference from the embodiment shown in fig. 4 is that in this embodiment, the input voltage terminal magnetic device 101 is connected to the drain of the power transistor M0 and the output voltage terminal, respectively, and the source of the power transistor M0 is grounded through the sampling resistor Rcs. In each switching period of the power tube M0, a sampling voltage CS obtained by sampling the current of the magnetic device 101 through the power tube M0 by the sampling resistor Rcs is input to the total harmonic distortion optimization circuit 401. The driving controller 40 further includes: a peak voltage and demagnetization duty ratio multiplication circuit 408 and a demagnetization detection unit 409; the demagnetization detection unit 409 obtains an output feedback voltage FB through an upper voltage division resistor and a lower voltage division resistor which are connected in parallel, and demagnetization time is obtained according to the detection of the output feedback voltage FB; the peak voltage and demagnetization duty ratio multiplication circuit 408 receives a logic signal GATE _ ON output by the logic unit 403 and controlling the conduction of the power tube M0, multiplies the proportion of the demagnetization time detected by the demagnetization detection unit 409 in the whole switching period by the peak voltage CSpk output by the total harmonic distortion optimization circuit 401, and outputs the multiplication result of the peak voltage and the demagnetization duty ratio to the negative input end of the transconductance amplifier Gm. Moreover, since the switching power supply system is an AC/DC switching power supply system with a FLYBACK topology, the lower plate of the first charging capacitor C1 in the ramp voltage generating unit 34 is connected to the system GND.
The total harmonic distortion optimization method of the switching power supply system described in this embodiment is similar to that of fig. 4, and is not repeated here.
Referring to fig. 11-12, wherein fig. 11 is a schematic diagram of a switching power supply system according to a third embodiment of the present invention; fig. 12 is a schematic diagram of an embodiment of a clamp current generation module in the embodiment shown in fig. 11. In this embodiment, the switching power supply system is an AC/DC switching power supply system with a BUCK topology. The difference from the embodiment shown in fig. 4 is that, in this embodiment, the total harmonic distortion optimization circuit 401 is connected to the inductor L0 through the upper and lower voltage dividing resistors RFBH and RFBL connected in parallel; the compensation current generation unit 32 of the total harmonic distortion optimization circuit 401 further includes: a clamp current generation module 111 and a current ratio mirror module 112.
The clamp current generating module 111 is electrically connected to a floating ground end through a lower voltage dividing resistor RFBL, and is also electrically connected to one end of the inductor L0, and is electrically connected to the other end of the inductor L0 through an upper voltage dividing resistor RFBH; the clamp current generating module 111 is configured to receive a clamp voltage FB obtained by sampling a current of the inductor L0 through the upper and lower voltage dividing resistors RFBH and RFBL connected in parallel in each switching cycle of the power transistor M0, and generate a corresponding clamp current Ifb.
The current proportional mirroring module 112 is configured to receive the clamp current Ifb, and obtain a total harmonic distortion compensation current Ithd through proportional mirroring.
One implementation of the clamp current generation module 111 is shown in fig. 12, and in the embodiment shown in fig. 12, the clamp current generation module 111 includes: a second operational amplifier Amp2 and a second MOS transistor M12. The positive input end of the second operational amplifier Amp2 is electrically connected to the floating ground, the negative input end of the second operational amplifier Amp2 is used for receiving the clamping voltage FB, and the output end of the second operational amplifier Amp is electrically connected to the control end of the second MOS transistor M12; and a first end of the second MOS transistor M12 is configured to receive the clamp voltage FB, and a second end is configured to output a clamp current Ifb. The working principle is as follows: when the power tube M0 is turned on, according to the virtual short principle of the operational amplifier, the FB potential is the same as the Floating _ GND potential, and at this time, the two ends of the lower voltage-dividing resistor RFBL are at the same potential and no current flows through; however, a current flows through the upper voltage-dividing resistor RFBH, and the current is outputted as an output current of the clamp current generation block 111 through the second MOS transistor M12.
At the end of the switching cycle, the clamp current is:
Ifb＝(Vin-Vo)/RFBH＝L*Ipk/(RFBH*Ton) (8)
then, at the end of the switching period, the total harmonic distortion compensation current is:
Ithd＝K3*Ifb＝K3*L*Ipk/(RFBH*Ton) (9)
wherein Ifb is a clamping current, Vin is an input voltage, Vo is an output voltage, RFBH is a resistance value of the upper voltage dividing resistor, L is an inductance value of the inductor L0, Ipk is a peak current of the inductor, Ton is a turn-on time of the power transistor M0, Ithd is a total harmonic distortion compensation current, and K3 is a mirror ratio of the current ratio mirror module 112.
As can be seen from equation (9), the total harmonic distortion compensation current Ithd is approximately proportional to the peak current Ipk of the inductor L0. After generating the total harmonic distortion compensation current Ithd, the influence of the total harmonic distortion compensation current Ithd on the on-time Ton and the total harmonic distortion is the same as that in fig. 4, and is not described herein again.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (15)
1. A total harmonic distortion optimization circuit adapted for use in a switching power supply system, the switching power supply system comprising: an inductor and a power tube; it is characterized by comprising: a compensation current generation unit and a ramp voltage generation unit;
the compensation current generation unit is coupled to the inductor and used for receiving sampling voltage obtained by sampling the current of the inductor in each switching period of the power tube and outputting total harmonic distortion compensation current;
the ramp voltage generating unit is used for receiving the total harmonic distortion compensation current and a reference current and outputting a ramp voltage for adjusting the conduction time of the power tube.
2. The circuit of claim 1, wherein the compensation current generation unit further comprises: a peak voltage sampling and holding module and a voltage/current conversion module;
the peak voltage sampling and holding module is used for receiving a turn-off pulse of the power tube and a logic signal for controlling the conduction of the power tube, is electrically connected with the inductor through a sampling resistor, receives sampling voltage obtained by sampling the current of the inductor by the sampling resistor in each switching period of the power tube, outputs peak voltage and holds the peak voltage;
and the voltage/current conversion module is used for receiving the peak voltage and outputting total harmonic distortion compensation current.
3. The circuit of claim 2, wherein the peak voltage sample-and-hold module comprises:
the first inverter is used for receiving the turn-off signal and outputting the inverted turn-off signal;
the AND gate is used for receiving the logic signal and the inverted turn-off signal and outputting a first control signal;
the second inverter is used for receiving the first control signal and outputting a second control signal;
the first end of the first holding switch is used for receiving the sampling voltage, the control end of the first holding switch is used for receiving the first control signal, and the second end of the first holding switch is connected with the floating ground end through a first sampling holding capacitor and is also electrically connected with the first end of the second holding switch;
and the control end of the second holding switch is used for receiving the second control signal, and the second end of the second holding switch is connected with the floating ground end through a second sampling holding capacitor and is also electrically connected to the output end of the peak voltage sampling holding module.
4. The circuit of claim 2, wherein the voltage/current conversion module comprises: the current mirror circuit comprises a first operational amplifier, a first MOS (metal oxide semiconductor) tube, a first current mirror and a second current mirror;
the positive input end of the first operational amplifier is used for receiving the peak voltage, the negative input end of the first operational amplifier is electrically connected with the first end of the first MOS tube and is also connected with the floating ground end through a first resistor, and the output end of the first operational amplifier is electrically connected with the control end of the first MOS tube;
the second end of the first MOS tube is electrically connected with the first end of the first current mirror;
the second end of the first current mirror is used for receiving VDD voltage, and the output end of the first current mirror is electrically connected with the first end of the second current mirror;
the second end of the second current mirror is connected with the floating ground end, and the output end generates total harmonic distortion compensation current;
wherein the total harmonic distortion compensation current flows through the second terminal of the second current mirror to a floating ground terminal.
5. The circuit of claim 4, wherein the first MOS transistor is a first NMOS transistor, wherein a source of the first NMOS transistor is used as a first terminal, a drain of the first NMOS transistor is used as a second terminal, and a gate of the first NMOS transistor is used as a control terminal;
the first current mirror adopts a first PMOS tube and a second PMOS tube which share a grid electrode, wherein a source electrode of the first PMOS tube, the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are jointly used as a first end, a drain electrode of the first PMOS tube and a drain electrode of the second PMOS tube are jointly used as a second end, and a source electrode of the second PMOS tube is used as an output end;
the second current mirror adopts a second NMOS tube and a third NMOS tube which share a grid electrode, wherein a drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the third NMOS tube are jointly used as a first end, a source electrode of the second NMOS tube and a source electrode of the third NMOS tube are jointly used as a second end, and a drain electrode of the third NMOS tube is used as an output end.
6. The circuit of claim 4, wherein the total harmonic distortion compensation current is:
Ithd＝K1*K2*CSpk/R81＝K1*K2*Ipk*Rcs/R81；
wherein, Ithd is total harmonic distortion compensation current, K1 is a mirror ratio of the first current mirror, K2 is a mirror ratio of the second current mirror, CSpk is a peak voltage obtained by sampling a peak current of the inductor, Ipk is a peak current of the inductor, Rcs is a resistance value of the sampling resistor, and R81 is a resistance value of the first resistor.
7. The circuit of claim 1, wherein the compensation current generation unit further comprises: the device comprises a clamping current generation module and a current proportion mirror image module;
the clamping current generation module is connected with a floating ground end through a lower divider resistor and is also electrically connected with one end of the inductor, and is electrically connected with the other end of the inductor through an upper divider resistor, and is used for receiving clamping voltage obtained by sampling the current of the inductor through the upper divider resistor and the lower divider resistor which are connected in parallel in each switching period of the power tube and generating corresponding clamping current;
and the current proportion mirror image module is used for receiving the clamping current and obtaining total harmonic distortion compensation current through proportion mirror image.
8. The circuit of claim 7, wherein the clamp current generation module comprises: the second operational amplifier and the second MOS tube;
the positive input end of the second operational amplifier is electrically connected with the floating ground end, the negative input end of the second operational amplifier is used for receiving the clamping voltage, and the output end of the second operational amplifier is electrically connected with the control end of the second MOS tube;
and the first end of the second MOS tube is used for receiving the clamping voltage, and the second end of the second MOS tube is used for outputting clamping current.
9. The circuit of claim 7, wherein at the end of a switching cycle, the clamping current is:
Ifb＝(Vin-Vo)/RFBH＝L*Ipk/(RFBH*Ton)；
at the end of the switching period, the total harmonic distortion compensation current is:
Ithd＝K3*Ifb＝K3*L*Ipk/(RFBH*Ton)；
wherein Ifb is a clamping current, Vin is an input voltage, Vo is an output voltage, RFBH is a resistance value of the upper voltage-dividing resistor, L is an inductance value of the inductor, Ipk is a peak current of the inductor, Ton is a power tube on-time, Ithd is a total harmonic distortion compensation current, and K3 is a mirror ratio of the current ratio mirror module.
10. The circuit of claim 1, wherein the ramp voltage generating unit further comprises: a first charging capacitor and a first control switch;
one end of the first charging capacitor is electrically connected with a charging current input end, and the other end of the first charging capacitor is connected with a floating ground end and used for generating a ramp voltage according to a charging current, wherein the charging current is a difference value between the reference current and the total harmonic distortion compensation current;
the first end of the first control switch is electrically connected with the charging current input end, the second end of the first control switch is used for receiving a slope voltage initial value, and the control end of the first control switch is used for receiving a logic signal which is conducted by the inverted control power tube; and the first end of the first control switch is simultaneously used as the output end of the ramp voltage generating unit and used for outputting the generated ramp voltage.
11. The circuit of claim 10, wherein the power tube on-time is:
Ton＝C1*(COMP-RAMPini)/(Iref-Ithd)；
wherein Ton is the conduction time of the power tube, C1 is the capacitance of the first charging capacitor, COMP is the compensation voltage of the switching power supply system, RAMPiniFor the initial value of the ramp voltage, Iref is the reference current, and Ithd is the total harmonic distortion compensation current.
12. A drive controller adapted for use in a switching power supply system, the switching power supply system comprising: an inductor and a power tube; characterized in that the drive controller comprises: a transconductance amplifier, a voltage comparator, a logic unit, a driving circuit, a signal inverter, and the total harmonic distortion optimization circuit of claim 1;
the transconductance amplifier has a positive input end for receiving a reference voltage, a negative input end for receiving a sampling voltage obtained by sampling a current of the inductor, and an output end connected to a floating ground end through a compensation capacitor for converting a difference between the reference voltage and the sampling voltage into a current to be injected into the compensation capacitor to generate a compensation voltage;
the positive input end of the voltage comparator is used for receiving the ramp voltage generated by the total harmonic distortion optimization circuit, the negative input end of the voltage comparator is used for receiving the compensation voltage, and the output end of the voltage comparator outputs a turn-off pulse of the power tube;
the logic unit is used for receiving the turn-off pulse, and outputting a logic signal for controlling the conduction of the power tube after logic operation;
the driving circuit is used for receiving the logic signal and driving the power tube to be conducted;
the signal phase inverter is used for receiving the logic signal, and feeding the logic signal back to the total harmonic distortion optimization circuit after phase inversion;
the higher the peak current of the inductor is, the larger the total harmonic distortion compensation current is, and the longer the conduction time of the power tube is, so that the total harmonic distortion of the switching power supply system is reduced.
13. The drive controller of claim 12, wherein the total harmonic distortion optimization circuit employs the total harmonic distortion optimization circuit of any one of claims 2-11.
14. A switching power supply system comprising: the power supply comprises an input voltage end, an output voltage end, a sampling resistor, a compensation capacitor, an inductor and a power tube, wherein the drain electrode of the power tube is electrically connected with the input voltage end, and the source electrode of the power tube is electrically connected with the output voltage end through the sampling resistor and the inductor; wherein the system further comprises the drive controller of claim 12;
the transconductance amplifier of the driving controller has a positive input end for receiving a reference voltage, a negative input end connected to the floating ground end through the sampling resistor, and an output end connected to the floating ground end through the compensation capacitor;
the total harmonic distortion optimization circuit of the driving controller is coupled to the inductor and used for receiving sampling voltage obtained by sampling current of the inductor in each switching period of the power tube and outputting ramp voltage for adjusting the conduction time of the power tube;
the driving circuit of the driving controller is electrically connected with the grid electrode of the power tube.
15. The system of claim 14, wherein the total harmonic distortion optimization circuit employs the total harmonic distortion optimization circuit of any one of claims 2-11.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106953508A (en) * | 2017-04-19 | 2017-07-14 | 上海晶丰明源半导体股份有限公司 | Total harmonic distortion optimization circuit, method, drive control device and switch power supply system |
| CN108683334A (en) * | 2018-08-20 | 2018-10-19 | 无锡麟力科技有限公司 | A kind of switching-on and switching-off state detection circuit for ground wire BUCK type Switching Power Supplies of floating |
| CN110098720A (en) * | 2018-08-22 | 2019-08-06 | 上海权策微电子技术有限公司 | Reduce the circuit of total harmonic distortion and increase power factor |
| CN113452269A (en) * | 2021-04-20 | 2021-09-28 | 成都芯源***有限公司 | Switching power supply circuit and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106953508A (en) * | 2017-04-19 | 2017-07-14 | 上海晶丰明源半导体股份有限公司 | Total harmonic distortion optimization circuit, method, drive control device and switch power supply system |
| CN106953508B (en) * | 2017-04-19 | 2024-03-08 | 上海晶丰明源半导体股份有限公司 | Total harmonic distortion optimization circuit and method, driving controller and switching power supply system |
| CN108683334A (en) * | 2018-08-20 | 2018-10-19 | 无锡麟力科技有限公司 | A kind of switching-on and switching-off state detection circuit for ground wire BUCK type Switching Power Supplies of floating |
| CN108683334B (en) * | 2018-08-20 | 2024-03-12 | 无锡麟力科技有限公司 | Power switch state detection circuit for floating ground wire BUCK type switching power supply |
| CN110098720A (en) * | 2018-08-22 | 2019-08-06 | 上海权策微电子技术有限公司 | Reduce the circuit of total harmonic distortion and increase power factor |
| CN113452269A (en) * | 2021-04-20 | 2021-09-28 | 成都芯源***有限公司 | Switching power supply circuit and method |
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