CN206489177U

CN206489177U - System when a kind of multi-channel high-speed is surveyed

Info

Publication number: CN206489177U
Application number: CN201720028679.4U
Authority: CN
Inventors: 吴镝; 王广军; 周青
Original assignee: Chengdu Sheng Ying Observation And Control Technology Co Ltd
Current assignee: Chengdu Sheng Ying Observation And Control Technology Co Ltd
Priority date: 2017-01-10
Filing date: 2017-01-10
Publication date: 2017-09-12
Anticipated expiration: 2027-01-10

Abstract

System when being surveyed the utility model discloses a kind of multi-channel high-speed in information detection technology field, including FPGA processing systems, electrically input connection pumping signal detects subsystem to the FPGA processing systems respectively, clock unit and isolation break-make trigger element, the FPGA processing systems electrically export connection memory module, the memory module electrically inputs connection power-down protection circuit, the FPGA processing systems are electrically bi-directionally connected Network Communication Sub system, system when this kind of multi-channel high-speed is surveyed, it is reasonable in design, pickup that can be to useful signal, voltage signal sampling is changed to be sampled loop current signal from traditional, greatly improve the signal to noise ratio of signal, integrality and antijamming capability, isolation processing is used between multichannel, low signal interference drops, and change conventional driver and signal transmission form, form unitary design.

Description

System when a kind of multi-channel high-speed is surveyed

Technical field

The utility model is related to information detection technology field, system when specially a kind of multi-channel high-speed is surveyed.

Background technology

In large-scale warhead and huge Artillery experiment, blindage range measurement target position is mostly in 200-400m positions.In detonation In test, the ON time of its ionic plasma often is measured using the method for serial electric probe is placed, so as to obtain detonation Speed.Break-make target or electric probe are passive devices, it is necessary to which extra driving source enters row energization to it, to produce electric signal. In field trial, a large amount of long test cables are buried in multimetering, driving source needs, connect up time and effort consuming, the precision measured also very Card is difficult to ensure, experimental data can be often measured and influence the key factor of quality of experiments, in addition, containing a large amount of in stimulus Interference signal, causes the very big puzzlement to analysis of experimental results.It must take anti-interference in a variety of methods, such as hardware design Measure, filtering, the pattern-recognition in software post processing etc., but result is barely satisfactory, and survey can be improved by how inventing one kind Accuracy of measurement, and system and chronometric data when integrated driving source and measurement integration, the multi-channel high-speed survey of drop low signal interference Processing method, is current those skilled in the art's urgent problem to be solved.

Utility model content

The purpose of this utility model is to provide system when a kind of multi-channel high-speed is surveyed, to solve to carry in above-mentioned background technology Go out in field trial, multimetering, driving source need embedded a large amount of long test cables, wiring time and effort consuming, the essence of measurement Degree also is difficult to ensure, and anti-interference energy profit, it is impossible to collect the problem of excitation and measurement integration.

To achieve the above object, the utility model provides following technical scheme：System when a kind of multi-channel high-speed is surveyed, including FPGA processing systems, the FPGA processing systems respectively electrically input connection pumping signal detection subsystem, clock unit and every From break-make trigger element, the FPGA processing systems electrically export connection memory module, and the memory module is electrically inputted Power-down protection circuit is connected, the FPGA processing systems are electrically bi-directionally connected Network Communication Sub system.

It is preferred that, the clock unit is made up of temperature compensation active crystal oscillator.

It is preferred that, the pumping signal detection subsystem includes pumping signal measurement processor, the pumping signal detection Processor electrically exports connection digital information memory cell, and the pumping signal measurement processor electrically inputs connection high-speed a/d Converting unit, the high-speed a/d converting unit electrically inputs connection high-speed photoelectric coupler, and the high-speed photoelectric coupler is electrical Input connection isolation boosting circuit, the isolation boosting circuit electrically inputs connection excitation power supply.

It is preferred that, the Network Communication Sub system includes network communication processor, and the network communication processor is electrically defeated Enter connection communication instruction reception unit, the network communication processor is electrically bi-directionally connected MUC network communication units, the MUC Network communication unit is electrically bi-directionally connected TCP/IP units, and the TCP/IP units are electrically bi-directionally connected I/O ports.

Compared with prior art, the beneficial effects of the utility model are：System when this kind of multi-channel high-speed is surveyed, design is closed Reason, pickup that can be to useful signal is changed to be sampled loop current signal, greatly from traditional to voltage signal sampling The signal to noise ratio for improving signal, integrality and antijamming capability, isolation processing is used between multichannel, low signal interference is dropped, And change conventional driver and signal transmission form, form unitary design.

Brief description of the drawings

Fig. 1 is the utility model system principle diagram；

Fig. 2 is that the utility model pumping signal detects subsystem diagram；

Fig. 3 is the utility model Network Communication Sub system block diagram.

In figure：1 FPGA processing systems, 2 pumping signals detection subsystem, 21 pumping signal measurement processors, 22 numeral letters Cease memory cell, 23 high-speed a/d converting units, 24 high-speed photoelectric couplers, 25 isolation boosting circuits, 26 excitation power supplies, 3 clocks Unit, 4 isolation break-make trigger elements, 5 memory modules, 6 Network Communication Sub systems, 61 network communication processors, 62 communications refer to Make receiving unit, 63 MUC network communication units, 64 TCP/IP units, 65 I/O ports, 7 power-down protection circuits.

Embodiment

Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the utility model, rather than whole Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made The every other embodiment obtained, belongs to the scope of the utility model protection.

Fig. 1-3 are referred to, the utility model provides a kind of technical scheme：System when a kind of multi-channel high-speed is surveyed, including FPGA processing systems 1, FPGA processing systems 1 respectively electrically input connection pumping signal detection subsystem 2, clock unit 3 and every From break-make trigger element 4, electrically output connects memory module 5, the electrically input connection of memory module 5 to FPGA processing systems 1 Power-down protection circuit 7, FPGA processing systems 1 are electrically bi-directionally connected Network Communication Sub system 6.

Wherein, clock unit 3 is made up of temperature compensation active crystal oscillator, and pumping signal detection subsystem 2, which includes excitation, to be believed Number measurement processor 21, pumping signal measurement processor 21 electrically output connection digital information memory cell 22, pumping signal inspection Survey the electrically input connection high-speed a/d converting unit 23 of processor 21, the electrical input connection high speed optoelectronic of high-speed a/d converting unit 23 Coupler 24, electrically input connects isolation boosting circuit 25 to high-speed photoelectric coupler 24, and electrically input connects isolation boosting circuit 25 Excitation power supply 26 is connect, Network Communication Sub system 6 includes network communication processor 61, the electrically input connection of network communication processor 61 Communication instruction receiving unit 62, network communication processor 61 is electrically bi-directionally connected MUC network communication units 63, MUC network services Unit 63 is electrically bi-directionally connected TCP/IP units 64, and TCP/IP units 64 are electrically bi-directionally connected I/O ports 65.

FPGA processing systems 1 are responsible for receiving the data signal that pumping signal detection subsystem 2 is detected, and signal is divided Analysis, compression and calculating processing, and be responsible for sending instruction；

Pumping signal detection subsystem 2 includes pumping signal measurement processor 21, digital information memory cell 22, high speed A/ D conversion unit 23, high-speed photoelectric coupler 24, isolation boosting circuit 25 and excitation power supply 26, isolation boosting circuit 25 will be encouraged Power supply 26 carries out isolation boosting, voltage stabilizing and filtering, and the driving source to target mesh, high speed optoelectronic are formed by high-speed photoelectric coupler 24 Coupler 24 detected to target mesh by electric current, is isolated while being realized by photoelectric effect, and by the current analog after isolation Signal is conveyed to high-speed a/d converting unit 23, and current analog signal is converted into current digital and believed by high-speed a/d converting unit 23 Number, and current digital signal is conveyed to digital information memory cell 22, digital information memory cell 22 is by current digital information Stored, digital information memory cell 22 is connected with FPGA processing systems 1；

Clock unit 3 provides the clock that stability is less than or equal to ten minus seven power, clock unit 3 and FPGA processing systems 1 connection；

Isolation break-make trigger element 4 is used for connecting trigger signal and for break trigger signal, isolation break-make trigger element 4 It is connected with FPGA processing systems 1, the object of systematic survey is transient process, it is necessary to which trigger signal is electric during survey to open during due to survey Road, to obtain useful signal to greatest extent, devises the two-way trigger signal of isolation in this instrument, can both be believed with connecting Number triggering, it is also possible to cut-off signal trigger, selection is set with software；

Memory module 5 provides height and stored for storing speed per hour data message, memory module 5 and FPGA processing systems 1 Connection；

Network Communication Sub system 6 includes network communication processor 61, communication instruction receiving unit 62, MUC network service lists Member 63, TCP/IP units 64 and I/O ports 65, communication instruction receiving unit 62 receive the network company that FPGA processing systems 1 are sent Lead to instruction, and network-in-dialing instruction is sent to the network communication processor 61 of network communication processor 61 and control MUC network services Unit 63 is connected, the drop low signal interference of MUC network communication units 63, and passes through TCP/IP units 64 and I/O ports 65 and the external world Network line is connected；

Power-down protection circuit 7 is that memory module 5 provides stand-by power supply circuit, when main electricity power-off, power down protection Circuit 7 is connected, it is ensured that the information in a period of time built-in storage module 5 will not lose, power-down protection circuit 7 and memory mould Group 5 is connected.

Operation principle：Software control isolation break-make trigger element 4 connects signal triggering, and sends a signal to FPGA processing System 1, afterwards isolation boosting circuit 25 excitation power supply 26 is subjected to isolation boosting, voltage stabilizing and filtering, coupled by high speed optoelectronic Device 24 forms the driving source to target mesh, and high-speed photoelectric coupler 24 is detected to target mesh by electric current, while being imitated by photoelectricity Isolation should be realized, and the current analog signal after isolation is conveyed to high-speed a/d converting unit 23, high-speed a/d converting unit 23 Current analog signal is converted into current digital signal, and current digital signal is conveyed to digital information memory cell 22, number Word information memory cell 22 is stored current digital information, and FPGA processing systems 1 obtain digital information memory cell afterwards The current digital information of 22 storages, and to digital information analysis, conversion and compression, current digital information is converted into time figure After information, time figure information is sent to memory module 5 by FPGA processing systems 1, and memory module 5 is by time figure information Storage, and FPGA processing systems 1 pass through network communication processor 61, communication instruction receiving unit 62, MUC network communication units 63rd, TCP/IP units 64 connect network with I/O ports 65, and send information to high in the clouds.

While there has been shown and described that embodiment of the present utility model, for the ordinary skill in the art, It is appreciated that these embodiments can be carried out in the case where not departing from principle of the present utility model and spirit a variety of changes, repaiies Change, replace and modification, scope of the present utility model is defined by the appended claims and the equivalents thereof.

Claims

System when 1. a kind of multi-channel high-speed is surveyed, including FPGA processing systems (1), it is characterised in that：The FPGA processing systems (1) electrically input connection pumping signal detects subsystem (2), clock unit (3) and isolation break-make trigger element (4), institute respectively State FPGA processing systems (1) electrically output connection memory module (5), the memory module (5) electrically input connection power down Protection circuit (7), the FPGA processing systems (1) are electrically bi-directionally connected Network Communication Sub system (6).
System when 2. a kind of multi-channel high-speed according to claim 1 is surveyed, it is characterised in that：The clock unit (3) by Temperature compensation active crystal oscillator is constituted.
System when 3. a kind of multi-channel high-speed according to claim 1 is surveyed, it is characterised in that：Pumping signal detection System (2) includes pumping signal measurement processor (21), and electrically output connection is digital for the pumping signal measurement processor (21) Information memory cell (22), electrically input connects high-speed a/d converting unit (23), institute to the pumping signal measurement processor (21) State high-speed a/d converting unit (23) electrically input connection high-speed photoelectric coupler (24), high-speed photoelectric coupler (24) electricity Property input connection isolation boosting circuit (25), the isolation boosting circuit (25) electrically input connection excitation power supply (26).
System when 4. a kind of multi-channel high-speed according to claim 1 is surveyed, it is characterised in that：The Network Communication Sub system (6) network communication processor (61) is included, the network communication processor (61) electrically inputs connection communication instruction reception unit (62), the network communication processor (61) is electrically bi-directionally connected MUC network communication units (63), the MUC network services list First (63) are electrically bi-directionally connected TCP/IP units (64), and the TCP/IP units (64) are electrically bi-directionally connected I/O ports (65).