CN206479868U - Low temperature drift reference voltage circuit - Google Patents

Abstract

The utility model provides a low temperature drift reference voltage circuit, which comprises a first voltage unit, a second voltage unit and a K-time amplifying unit; the first voltage unit is used for generating a first voltage, and the first end of the first voltage unit is grounded; the K-time amplifying unit is used for amplifying the first voltage by K times, a first end of the K-time amplifying unit is connected with a second end of the first voltage unit, a second end of the K-time amplifying unit is connected with a first end of the second voltage unit, and K is a constant greater than zero; and the second voltage unit is used for generating a second voltage, a first end of the second voltage unit is connected with the current source circuit, and a second end of the second voltage unit is connected with a third end of the first voltage unit and then is used as an output end of the reference voltage. The output reference voltage has extremely low temperature dependence, the circuit structure is simple in design, the types of required devices are few, the design difficulty and risk are greatly reduced, and the high practicability and universality are achieved.

Description

Low Drift Temperature reference voltage circuit

Technical field

The utility model is related to semiconductor integrated circuit field, more particularly to a kind of Low Drift Temperature reference voltage circuit.

Background technology

With the development and growth in the living standard of science and technology, portable set has been one of necessity in life.And Hydrid integrated circuit is configured as the brain of mancarried device, while being used widely, and is also faced with more complicated many The requirement and challenge of change.The quality of the foundation stone of hydrid integrated circuit-reference voltage performance, directly influences that terminal is portable to be set Standby performance experience.The temperature characterisitic of reference voltage, directly determines the temperature in use scope of terminal device, and reference circuit is most Low-work voltage then limits another important performance-endurance of terminal device.

The design philosophy of traditional bandgap voltage reference is the voltage for producing positive and negative temperature coefficient respectively, then passes through fortune Calculate the reference voltage for obtaining zero-temperature coefficient.The voltage generation of negative temperature coefficient is more convenient, but positive temperature coefficient benchmark is electric Pressure is then not readily available.Using the base of two triodes being operated under unequal current density in traditional implementation The difference of pole-emitter voltage is realized.But the circuit design of its operational amplifier included is difficult in low-voltage, such as：2V Normal work under following voltage conditions.And in order to reduce matching error, generally select large-size and greater number of three pole Pipe, the integrated circuit diagram being so fabricated to is larger and spends cost also higher.

Normal work of the circuit under extremely low voltage is realized in conventional art using tubular construction is exhausted, but is due to its temperature Degree coefficient can not ensure, the reference voltage of output varies with temperature that fluctuation is also larger, temperature on the output influence of reference voltage compared with Greatly, it is difficult to meet high-precision application demand.

Utility model content

Based on this, it is necessary to circuit is realized using pipe is exhausted under extremely low voltage during normal work for tradition, temperature , can be under extremely low voltage just there is provided a kind of Low Drift Temperature reference voltage circuit the problem of larger on the reference voltage influence of output Often while work, additionally it is possible to so that the reference voltage and temperature dependency of output are extremely low.

To reach utility model purpose there is provided a kind of Low Drift Temperature reference voltage circuit, the circuit includes first voltage list Member, second voltage unit and K times of amplifying unit；

The first voltage unit, for producing first voltage, its first end ground connection；

The K times of amplifying unit, for the first voltage to be amplified into K times, its first end and the first voltage unit The connection of the second end, the second end is connected with the first end of the second voltage unit, wherein, K is the constant more than zero；

The second voltage unit, for producing second voltage, its first end access current source circuit, the second end with it is described The output end of reference voltage is used as after the three-terminal link of first voltage unit.

In one of the embodiments, the first voltage unit includes NMOS tube MN, and the second voltage unit includes PMOS MP, the K times of amplifying unit includes resistance R1 and resistance R2, wherein：

The source electrode of the NMOS tube MN is grounded after being connected with the first end of the resistance R2, the grid of the NMOS tube MN with It is connected after the second end connection of the resistance R2 with the first end of the resistance R1, drain electrode and the PMOS of the NMOS tube MN The output end of the reference voltage is used as after pipe MP drain electrode and grid connection；

The source electrode of the PMOS MP accesses the current source circuit after being connected with the second end of the resistance R1.

In one of the embodiments, the first voltage unit includes NPN type triode QN, the second voltage unit Including PNP type triode QP, the K times of amplifying unit includes resistance R1 and resistance R2, wherein：

The emitter stage of the NPN type triode QN is grounded after being connected with the first end of the resistance R2, the pole of NPN type three Pipe QN base stage is connected after being connected with the second end of the resistance R2 with the first end of the resistance R1, the NPN type triode QN colelctor electrode be connected with the colelctor electrode and base stage of the PNP type triode QP after as the reference voltage output end；

The emitter stage of the PNP type triode QP accesses the current source electricity after being connected with the second end of the resistance R1 Road.

In one of the embodiments, the current source circuit includes current mirroring circuit.

In one of the embodiments, the current mirroring circuit includes PMOS MP1, PMOS MP2, PMOS MP3, NMOS tube MN1, NMOS tube MN2 and resistance Rs, wherein：

The PMOS MP1, the PMOS MP2 and the PMOS MP3 source electrode access same power supply, the PMOS Grid of pipe MP2 and the PMOS MP3 grid with the PMOS MP1 is connected, and the grid of the PMOS MP3 with The drain electrode connection of the PMOS MP2；

The drain electrode of the PMOS MP1 is connected with the drain and gate of the NMOS tube MN1, the source of the NMOS tube MN1 Pole is grounded；

The drain electrode of the PMOS MP2 is connected with the drain electrode of the NMOS tube MN2, the grid of the NMOS tube MN2 and institute State NMOS tube MN1 grid connection, and the source electrode of the NMOS tube MN2 be connected with the resistance Rs after ground connection；

The drain electrode of the PMOS MP3 is connected with the first end of the second voltage unit.

The utility model also provides a kind of Low Drift Temperature reference voltage circuit, and the system includes first voltage unit, second Voltage cell and K times of amplifying unit；

The first voltage unit, for producing first voltage, its first end ground connection；

The K times of amplifying unit, for the first voltage to be amplified into K times, its first end and the first voltage unit The connection of the second end, access current source circuit after the three-terminal link of the second end and the first voltage unit, wherein, K is big In zero constant；

The second voltage unit, for producing second voltage, its first end and the 3rd end of the first voltage unit Access the current source circuit after connection, the second end as reference voltage output end.

In one of the embodiments, the first voltage unit includes PMOS MP and metal-oxide-semiconductor M1, the second voltage Unit includes NMOS tube MN and metal-oxide-semiconductor M2, and the K times of amplifying unit includes resistance R1 and resistance R2, wherein：

The grid of the PMOS MP is connected with the first end of the resistance R1 and the first end of the resistance R2, described PMOS MP source electrode accesses current source circuit, the drain electrode of the PMOS MP and institute after being connected with the second end of the resistance R1 The grid and drain electrode for stating metal-oxide-semiconductor M1 are connected, the source ground of the metal-oxide-semiconductor M1, the second end ground connection of the resistance R2；

The grid and the drain electrode access current source circuit of the NMOS tube MN, the source electrode of the NMOS tube MN is as described The output end of reference voltage, and be connected with the drain electrode of the metal-oxide-semiconductor M2, the grid of the grid of the metal-oxide-semiconductor M2 and the metal-oxide-semiconductor M1 Pole and drain electrode are connected, the source ground of the metal-oxide-semiconductor M2.

In one of the embodiments, the first voltage unit includes PNP type triode QP and triode Q1, the second electricity Unit is pressed to include NPN type triode QN and triode Q2, the K times of amplifying unit includes resistance R1 and resistance R2, wherein：

The base stage of the PNP type triode QP is connected with the first end of the resistance R1 and the first end of the resistance R2, The emitter stage of the PNP type triode QP accesses current source circuit, the positive-negative-positive three after being connected with the second end of the resistance R1 Pole pipe QP colelctor electrode is connected with the base stage and colelctor electrode of the triode Q1, and the grounded emitter of the triode Q1 is described Resistance R2 the second end ground connection；

The base stage and colelctor electrode of the NPN type triode QN accesses the current source circuit, the NPN type triode QN's Emitter stage and is connected, the base of the triode Q2 as the output end of the reference voltage with the colelctor electrode of the triode Q2 Pole is connected with the base stage and colelctor electrode of the triode Q1, the grounded emitter of the triode Q2.

In one of the embodiments, the current source circuit includes current mirroring circuit.

In one of the embodiments, the current mirroring circuit includes PMOS MP1, PMOS MP2, PMOS MP3, NMOS tube MN1, NMOS tube MN2 and resistance Rs, wherein：

The PMOS MP1, the PMOS MP2 and the PMOS MP3 source electrode access same power supply, the PMOS Grid of pipe MP2 and the PMOS MP3 grid with the PMOS MP1 is connected, and the grid of the PMOS MP3 with The drain electrode connection of the PMOS MP2；

The drain electrode of the PMOS MP1 is connected with the drain and gate of the NMOS tube MN1, the source of the NMOS tube MN1 Pole is grounded；

The drain electrode of the PMOS MP2 is connected with the drain electrode of the NMOS tube MN2, the grid of the NMOS tube MN2 and institute State NMOS tube MN1 grid connection, and the source electrode of the NMOS tube MN2 be connected with the resistance Rs after ground connection；

The drain electrode of the PMOS MP3 is connected with the first end of the second voltage unit.

The beneficial effects of the utility model include：

Above-mentioned Low Drift Temperature reference voltage circuit, directly has using two and is all positive temperature coefficient or is all negative temperature system Several first voltage units and second voltage unit, calculating is causedK values, then The K times of amplifying unit that design one calculates obtained K value sizes, and K times of amplifying unit is accessed in circuit, so that output Reference voltage is extremely low with temperature dependency, or even unrelated, realizes circuit temperature difference output during normal work under extremely low voltage Reference voltage also indifference effect, disclosure satisfy that high-precision application demand, and its circuit structure design is simple, it is required Type of device is few, greatly reduces design difficulty and risk, has very high practicality in integrated circuit field And versatility.

Brief description of the drawings

Fig. 1 be one embodiment in Low Drift Temperature reference voltage circuit circuit diagram；

Fig. 2 is the circuit diagram of a specific embodiment of Low Drift Temperature reference voltage circuit shown in Fig. 1；

Fig. 3 is the circuit diagram of the another specific embodiment of Low Drift Temperature reference voltage circuit shown in Fig. 1；

Fig. 4 is the circuit diagram of the still another embodiment of Low Drift Temperature reference voltage circuit shown in Fig. 1；

Fig. 5 is the circuit diagram for the Low Drift Temperature reference voltage circuit that one embodiment includes current source circuit；

Fig. 6 be another embodiment in Low Drift Temperature reference voltage circuit circuit diagram；

Fig. 7 is the circuit diagram of a specific embodiment of Low Drift Temperature reference voltage circuit shown in Fig. 6；

Fig. 8 be one embodiment in Low Drift Temperature reference voltage circuit DC voltage analysis chart；

Fig. 9 be one embodiment in Low Drift Temperature reference voltage circuit temperature analysis figure；

Figure 10 be one embodiment in Low Drift Temperature reference voltage circuit PSRR analysis chart.

Embodiment

In order that the purpose of this utility model, technical scheme and advantage are more clearly understood, below in conjunction with accompanying drawing and implementation The utility model Low Drift Temperature reference voltage circuit is further elaborated example.It should be appreciated that described herein specific Embodiment only to explain the utility model, is not used to limit the utility model.

In one embodiment, as shown in Figure 1 there is provided a kind of Low Drift Temperature reference voltage circuit, the circuit includes first Voltage cell, second voltage unit and K times of amplifying unit.First voltage unit, for producing first voltage, its first termination Ground；K times of amplifying unit, for first voltage to be amplified into K times, its first end is connected with the second end of first voltage unit, and second End is connected with the first end of second voltage unit, wherein, K is the constant more than zero；Second voltage unit, for producing the second electricity Pressure, its first end access current source circuit, the second end after the three-terminal link of first voltage unit with being used as the defeated of reference voltage Go out end.

First voltage V is produced during first voltage cell operation in the Low Drift Temperature reference voltage circuit in the present embodiment₁, the Second voltage V is produced when two voltage cells work₂, and in circuit A points voltage V_ABy K times of amplifying unit and first voltage unit Together decide on：V_A=K*V₁, and the reference voltage V exported_REF=K*V₁-V₂, in order that the reference voltage V of output_REFWith temperature without Close, it is necessary to so that I.e. so that And first, second usually used voltage cell, such as：Metal-oxide-semiconductor, the temperature coefficient of the voltage of triode are the rises with temperature And decline, i.e., first, second usually used voltage cell is the temperature coefficient with equidirectional, i.e., In order to ensureIt can set up, K value needs to be greater than zero constant It is only possible to set up (if K value is negative, both members then can not possibly be equal), i.e. basis Size calculate obtain making formulaThe K values of establishment, are then designed according to the size of K values One K times of amplifying unit, so that the reference voltage V of output_REFIt is temperature independent.

Low Drift Temperature reference voltage circuit in the present embodiment, directly has using two and is all positive temperature coefficient or is all The first voltage unit and second voltage unit of negative temperature coefficient, calculating are caused K Value, then designs a K times of amplifying unit for calculating obtained K value sizes, accesses the second end and second of first voltage unit Between the first end of voltage cell, so that the reference voltage and temperature dependency of output are extremely low or even unrelated, that is, output is realized Reference voltage even if the also effect of indifference at different temperatures, disclosure satisfy that high-precision application demand, and its circuit knot Structure design is simple, and required type of device is few, greatly reduces design difficulty and risk, in integrated circuit field tool There is very high practicality and versatility.

Wherein, first voltage unit and second voltage unit can be respectively metal-oxide-semiconductor or triode.

In one embodiment, referring to Fig. 2, first voltage unit includes NMOS tube MN, and second voltage unit includes PMOS Pipe MP, K times of amplifying unit includes resistance R1 and resistance R2.Wherein：After NMOS tube MN source electrode is connected with resistance R2 first end Ground connection, NMOS tube MN grid is connected after being connected with resistance R2 the second end with resistance R1 first end, NMOS tube MN drain electrode Drain electrode and grid with PMOS MP be connected after as reference voltage output end.PMOS MP source electrode and the second of resistance R1 Current source circuit is accessed after the connection of end.

The embodiment is to realize the particular circuit configurations of the circuit diagram shown in Fig. 1, and it is preferably a kind of embodiment.At this Its in circuit mainly includes PMOS MP (correspondence second voltage unit), NMOS tube MN (correspondence first voltage unit) and ratio electricity Hinder R1 and R2 (K times of amplifying unit of correspondence).When the power source is activated, current source circuit produces electric current I, and electric current I first flows through ratio Resistance R1 and R2, when electric current I, resistance R2 and NMOS tube MN unlatching threshold value Vthn meet I*R2=Vgsn>During Vthn, wherein Vgsn is the voltage of NMOS tube MN grids, and NMOS tube MN is turned on, and now PMOS MP grid voltage is pulled low, as PMOS MP Gate source voltage | Vgsp |>| Vthp | when, PMOS conducting, now PMOS MP is shunted to electric current I, and reduction flows through ratio Resistance R1, R2 electric current.When the electric current for flowing through proportion resistor R1, R2 is less than normal, by I*R2=Vgsn>Knowable to Vthn, NMOS tube MN grid voltage Vgsn can reduce, and it is shunted by PMOS MP to electric current I can also reduce, so as to increase the ratio of flowing through Resistance R1, R2 electric current, so finally cause whole circuit to tend towards stability repeatedly, when circuit is finally stablized, reference voltage V_REF Determined by following formula：V_REF=(1+R1/R2) Vgsn- ︱ Vgsp ︱, wherein, Vgsp is PMOS MP gate source voltage.

And have for NMOS tube MN and PMOS MP：Vgsn=Vdsatn+Vthn, ︱ Vgsp ︱=︱ Vdsatp ︱+︱ Vthp ︱, Wherein, Vdsatn is the changing value of the voltage of NMOS tube, and Vdsatp is the changing value of the voltage of PMOS.By above-mentioned V_REF=(1+ R1/R2) Vgsn- ︱ Vgsp ︱ and Vgsn=Vdsatn+Vthn, ︱ Vgsp ︱=︱ Vdsatp ︱+︱ Vthp ︱ formulas are understood, as electric current I It is constant, when resistance R1, R2 value is sufficiently large, reference voltage V_REFIt is unrelated with supply voltage.And when current Iconst, NMOS tube MN With PMOS MP breadth length ratio it is sufficiently large when, influences of the voltage change Vdsatn and Vdsatp to NMOS tube MN and PMOS MP Very little (similar water pipe, when water pipe breadth length ratio is sufficiently large, the changing value of water flow influences very little to water pipe), Vgsn, ︱ Vgsp ︱ and electric current I correlation very little, is mainly determined by Vthn and ︱ Vthp ︱, and Vthn and ︱ Vthp ︱ be by NMOS tube MN and What technique when PMOS MP is produced was determined.For most techniques, Vgsn and ︱ Vgsp ︱ temperature coefficient Tgsn and Tgsp It is negative, and meets ︱ Tgsn ︱<︱ Tgsp ︱, therefore, when R1 and the setting of R2 ratios are suitable, meet (1+R1/R2) ︱ Tgsn ︱=︱ Tgsp ︱, then, reference voltage V REF performances are temperature independent.

Low Drift Temperature reference voltage circuit in the embodiment, is transported using two same voltages with negative temperature coefficient Calculate, obtain zero-temperature coefficient voltage.Supply voltage only needs to be higher than (1+R1/R2) Vgsn ≈ Vthn+Vthp, you can produce benchmark electricity Press, and the circuit in the embodiment only needs PMOS MP, NMOS tube MN and tetra- devices of resistance R1, R2 to can be achieved, structure It is extremely simple, easily realize, domain occupancy size is small in integrated circuit, with very high industrial application value.

In one embodiment, referring to Fig. 3, first voltage unit includes NPN type triode QN, and second voltage unit includes PNP type triode QP, K times of amplifying unit includes resistance R1 and resistance R2.Wherein：NPN type triode QN emitter stage and resistance R2 first end connection after be grounded, NPN type triode QN base stage be connected with resistance R2 the second end after with resistance R1 first End connection, NPN type triode QN colelctor electrode be connected with PNP type triode QP colelctor electrode and base stage after as reference voltage Output end.PNP type triode QP emitter stage accesses current source circuit after being connected with resistance R1 the second end.

The embodiment is to realize the particular circuit configurations of the circuit diagram shown in Fig. 1, and it substitutes foregoing implementation using triode Metal-oxide-semiconductor in example, can play the effect for saving circuit devcie cost.Because it is similar to the principle in previous embodiment, this Place is repeated no more.

In one embodiment, referring to Fig. 4, Low Drift Temperature reference voltage circuit can be that the mixing of triode and metal-oxide-semiconductor makes For realizing that the reference voltage of output is temperature independent.

In one embodiment, referring to Fig. 5, current source circuit includes current mirroring circuit.Specifically, current mirroring circuit includes PMOS MP1, PMOS MP2, PMOS MP3, NMOS tube MN1, NMOS tube MN2 and resistance Rs.Wherein：PMOS MP1, PMOS Pipe MP2 and PMOS MP3 source electrode accesses same power supply, and PMOS MP2 and the PMOS MP3 grid are and PMOS MP1 grid is connected, and PMOS MP3 grid is connected with PMOS MP2 drain electrode.PMOS MP1 drain electrode and NMOS tube MN1 drain and gate connection, NMOS tube MN1 source ground.PMOS MP2 drain electrode is connected with NMOS tube MN2 drain electrode, NMOS tube MN2 grid is connected with NMOS tube MN1 grid, and NMOS tube MN2 source electrode be connected with resistance Rs after be grounded.PMOS Pipe MP3 drain electrode is connected with the first end of second voltage unit.

An electric current I particular circuit configurations are produced in above-described embodiment, current mirroring circuit can produce stablize and power supply Unrelated electric current I.Its mainly include PMOS MP1, MP2 and NMOS tube MN1, MN2 and resistance Rs, wherein PMOS MP1, MP2 has identical physical dimension, and the physical dimension ratio of NMOS tube MN1, MN2 is 1：k.

It can be write out by NMOS tube MN1, MN2 and resistance Rs：Vgs1=Vgs2+I*Rs, wherein, I is to flow through NMOS tube MN1 With MN2 electric current.Vgs1 and Vgs2 are NMOS tube MN1 and MN2 grid voltage respectively.By above-mentioned formula combination saturation region NMOS The calculation formula of pipe drain current and grid voltage, draws I=2/ (u_n C_ox(W/L)_N) * 1/ (Rs^2) * (1-1/ √ k) ^2, its In, W/L is the breadth length ratio of NMOS tube, U_nFor the migration rate of NMOS tube electronics, C_oxFor NMOS tube unit area gate oxide electricity Hold, be not difficult to find out in the formula, electric current I (but still being the function of temperature and technique) unrelated with supply voltage, its size is by electricity Rs resistance and the dimension scale coefficient k of NMOS tube MN2, MN1 is hindered to determine.

PMOS MP, MP3, NMOS tube MN and proportion resistor R1, R2 in Fig. 5 circuits is mainly for generation of reference voltage V_REF.Wherein PMOS MP3 is identical with PMOS MP1, MP2 size, and collectively forms current-mirror structure, PMOS MP3 outputs Size of current is equal with the electric current I of PMOS MP1, MP2.

Based on the design of same utility model, a kind of Low Drift Temperature reference voltage circuit is also provided, as shown in fig. 6, the circuit bag Include first voltage unit, second voltage unit and K times of amplifying unit.First voltage unit, for producing first voltage, it first End ground connection.K times of amplifying unit, for first voltage to be amplified into K times, its first end is connected with the second end of first voltage unit, Current source circuit is accessed after the three-terminal link of second end and first voltage unit, wherein, K is the constant more than zero.Second electricity Unit is pressed, for producing second voltage, current source circuit is accessed after the three-terminal link of its first end and first voltage unit, the Two ends as reference voltage output end.

Low Drift Temperature reference voltage electricity in the operation principle and previous embodiment of Low Drift Temperature reference voltage circuit in the present embodiment Road is similar, and first voltage V is produced during first voltage cell operation₁, second voltage V is produced during second voltage cell operation₂, and in circuit The voltage V of A points_ATogether decided on by K times of amplifying unit and first voltage unit：V_A=K*V₁, and the reference voltage V exported_REF=K*V₁- V₂, in order that the reference voltage V of output_REFIt is temperature independent, it is necessary to so that I.e. so thatAnd first, second usually used voltage cell, such as：Metal-oxide-semiconductor, triode The temperature coefficient of voltage is declined with the rise of temperature, i.e., first, second usually used voltage cell is with phase Equidirectional temperature coefficient, i.e.,In order to ensureEnergy Enough to set up, K value needs the constant for being greater than zero to be only possible to establishment.Low Drift Temperature reference voltage circuit in design the present embodiment When, it is necessary to according toSize calculate obtain making formula The K values of establishment, then design a K times of amplifying unit according to the size of K values, so that the reference voltage V of output_REFWith temperature Degree is unrelated.

Low Drift Temperature reference voltage circuit in the present embodiment, directly has using two and is all positive temperature coefficient or is all The first voltage unit and second voltage unit of negative temperature coefficient, calculating are caused K values, then design one and calculate obtained K times of amplifying unit of K value sizes, and K times of amplifying unit is linked into circuit, So that the reference voltage and temperature dependency of output are extremely low or even unrelated, that is, realize the reference voltage of output even in difference At a temperature of effect also without big difference, disclosure satisfy that high-precision application demand, and its circuit structure design is simple, required device Part type is few, greatly reduces design difficulty and risk, have in integrated circuit field very high practicality and Versatility.

In one embodiment, referring to Fig. 7, first voltage unit includes PMOS MP and metal-oxide-semiconductor M1, second voltage unit Including NMOS tube MN and metal-oxide-semiconductor M2, K times of amplifying unit includes resistance R1 and resistance R2.Wherein：PMOS MP grid and resistance R1 first end and resistance R2 first end connection, PMOS MP source electrode access current source after being connected with resistance R1 the second end Circuit, PMOS MP drain electrode is connected with metal-oxide-semiconductor M1 grid and drain electrode, metal-oxide-semiconductor M1 source ground, resistance R2 the second end Ground connection.NMOS tube MN grid and drain electrode access current source circuit, NMOS tube MN source electrode as reference voltage output end, and Drain electrode with metal-oxide-semiconductor M2 is connected, and metal-oxide-semiconductor M2 grid is connected with metal-oxide-semiconductor M1 grid and drain electrode, metal-oxide-semiconductor M2 source ground.

The embodiment is to realize the particular circuit configurations of the circuit diagram shown in Fig. 6, its for it is a kind of preferred embodiment. Mainly include PMOS MP and metal-oxide-semiconductor M1 (correspondence first voltage unit) in the circuit, NMOS tube MN and metal-oxide-semiconductor M2 (correspondence the Two voltage cells) and proportion resistor R1 and R2 (K times of amplifying unit of correspondence).When the power source is activated, current source circuit produces electric current I, electric current first flows through proportion resistor R1 and R2, when electric current I flows through resistance R1, due to there is resistance R1 pressure drop, can cause PMOS MP grid voltage is less than source voltage, as PMOS MP grid voltage Vgsp=IR1 ＜ Vthp, wherein, Vthp Threshold value is opened for PMOS MP voltage, PMOS MP is turned on, after POMS pipes MP conductings, metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2 (metal-oxide-semiconductor M1 Be preferably NMOS tube with M2) grid voltage be driven high, now metal-oxide-semiconductor M1 and M2 conducting, metal-oxide-semiconductor M2 conducting after so that NMOS Pipe MN source voltages are pulled low, and its grid voltage is A point voltages, as NMOS tube MN gate source voltage Vgsn>During Vthn, NMOS Pipe MN is also switched on, and now PMOS MP and NMOS tube MN are shunted to electric current I, reduces the electric current for flowing through proportion resistor R1, R2. When the electric current for flowing through proportion resistor R1, R2 is less than normal, the pressure drop that resistance R1 is brought will reduce, now the voltage of PMOS MP grids It is close with source voltage, by Vgsp=V_A- I*R1, PMOS MP grid voltage will increase, and it passes through PMOS MP and NMOS Pipe MN is shunted to electric current I can also reduce, so that increase the electric current for flowing through proportion resistor R1, R2, it is so repeatedly final to cause Whole circuit tends towards stability, when circuit is finally stablized, reference voltage V_REFDetermined by following formula：V_REF=(1+R1/R2) Vgsp- ︱ Vgsn ︱.

And have for NMOS tube MN and PMOS MP：Vgsn=Vdsatn+Vthn, ︱ Vgsp ︱=︱ Vdsatp ︱+︱ Vthp ︱, Wherein, Vdsatn is the changing value of the voltage of NMOS tube, and Vdsatp is the changing value of the voltage of PMOS.By above-mentioned V_REF=(1+ R1/R2) Vgsp- ︱ Vgsn ︱ and Vgsn=Vdsatn+Vthn, ︱ Vgsp ︱=︱ Vdsatp ︱+︱ Vthp ︱ formulas are understood, as electric current I It is constant, when resistance R1, R2 value is sufficiently large, reference voltage V_REFIt is unrelated with supply voltage.And when current Iconst, NMOS tube MN With PMOS MP breadth length ratio it is sufficiently large when, voltage change Vdsatn. and Vdsatp is to NMOS tube MN and PMOS MP shadow Very little is rung, Vgsn, ︱ Vgsp ︱ and electric current I correlation very little are mainly determined by Vthn and ︱ Vthp ︱, and Vthn and ︱ Vthp ︱ are What technique when being produced by NMOS tube MN and PMOS MP was determined.For most techniques, Vgsn and ︱ Vgsp ︱ temperature system Number Tgsn and Tgsp is negative, and meets ︱ Tgsn ︱>︱ Tgsp ︱, therefore, when R1 and the setting of R2 ratios are suitable, meet (1+R1/ R2) ︱ Tgsp ︱=︱ Tgsn ︱, then, reference voltage V REF performances are temperature independent.

Low Drift Temperature reference voltage circuit in the embodiment, is transported using two same voltages with negative temperature coefficient Calculate, obtain zero-temperature coefficient voltage.Supply voltage only needs to be higher than (1+R1/R2) Vgsp ≈ Vthn+Vthp, you can produce benchmark electricity Press, and the circuit in the embodiment only needs PMOS MP, NMOS tube MN, metal-oxide-semiconductor M1, tetra- devices of metal-oxide-semiconductor M2 and resistance R1, R2 Part is that can be achieved, and structure is extremely simple, is easily realized, domain occupancy size is small in integrated circuit, with very high commercial Application Value.

In one embodiment, first voltage unit includes PNP type triode QP and triode Q1, second voltage unit bag NPN type triode QN and triode Q2 are included, K times of amplifying unit includes resistance R1 and resistance R2.Wherein：PNP type triode QP's Base stage is connected with resistance R1 first end and resistance R2 first end, PNP type triode QP emitter stage and the second of resistance R1 Current source circuit is accessed after the connection of end, PNP type triode QP colelctor electrode is connected with triode Q1 base stage and colelctor electrode, three poles Pipe Q1 grounded emitter, resistance R2 the second end ground connection.NPN type triode QN base stage and colelctor electrode access current source electricity Road, NPN type triode QN emitter stages and are connected, triode Q2 as the output end of reference voltage with triode Q2 colelctor electrode Base stage be connected with triode Q1 base stage and colelctor electrode, triode Q2 grounded emitter.

The embodiment is to realize the particular circuit configurations of the circuit diagram shown in Fig. 6, and it substitutes foregoing implementation using triode Metal-oxide-semiconductor in example, can play the effect for saving circuit devcie cost.Because it is similar to the principle in previous embodiment, this Place is repeated no more.

In one embodiment, current source circuit includes current mirroring circuit.Specifically, current mirroring circuit includes PMOS MP1, PMOS MP2, PMOS MP3, NMOS tube MN1, NMOS tube MN2 and resistance Rs.Wherein：PMOS MP1, PMOS MP2 Same power supply is accessed with PMOS MP3 source electrode, and the grid of PMOS MP2 and PMOS MP3 grid with PMOS MP1 connects Connect, and PMOS MP3 grid is connected with PMOS MP2 drain electrode.PMOS MP1 drain electrode and NMOS tube MN1 drain electrode and Grid is connected, NMOS tube MN1 source ground.PMOS MP2 drain electrode is connected with NMOS tube MN2 drain electrode, NMOS tube MN2's Grid is connected with NMOS tube MN1 grid, and NMOS tube MN2 source electrode be connected with resistance Rs after be grounded.PMOS MP3 drain electrode It is connected with the first end of second voltage unit.

The embodiment is produces the stable electric current I unrelated with power supply particular circuit configurations, and it produces electric current I principle It is described in detail in the aforementioned embodiment, here is omitted.

In order to further illustrate Low Drift Temperature reference voltage circuit in above-described embodiment, below in conjunction with to above-mentioned Low Drift Temperature benchmark The simulation result that the relevant parameter of potential circuit is emulated is illustrated：Fig. 8 is the Low Drift Temperature benchmark electricity in one embodiment In the DC voltage analysis chart of volt circuit, figure display reference voltage in supply voltage from 1V~6V situation of change.It is most upper in figure What lines were emulated in the square frame in face is mains voltage variations situation, it can be seen that the mains voltage variations and reality of simulation The supply voltage on border is consistent, and the changing value of supply voltage becomes for 4.4V, i.e. supply voltage from 1.607V turns to 6V.In in figure Between square frame in lines emulate be reference voltage with the situation of change of supply voltage, wherein M5 points represent that supply voltage is Indication circuit is during foundation before corresponding reference voltage is 679.1mV, M5 points during 1.595V, and now circuit is in shakiness Fixed state；M6 points represent that supply voltage corresponding reference voltage in 4.724V is 702.6mV；M3 points represent that supply voltage becomes The changing value of reference voltage is 37.91mV when changing 4.4V.What lines were emulated in the square frame below in figure is reference current with electricity The situation of change of source voltage, wherein M9 point represent that supply voltage is 1.696 μ A, M10 point tables in the corresponding reference currents of 1.598V Show corresponding reference current when supply voltage is 5V be 2.019 μ A, M6 points represent be mains voltage variations 4.396V when correspondence Reference current change 565.6nA.Understand to find out from the figure, when supply voltage is 1.595V, reference voltage just can be normal Work, i.e., reference voltage can be in pole operation at low power supply voltage, and the operating voltage of reference voltage can be with as little as 1.595V.

Fig. 9 is the temperature analysis figure of the Low Drift Temperature reference voltage circuit in one embodiment, which show reference voltage and The variation relation of temperature, wherein, what M0 points were represented is corresponding reference voltage during 95.2 DEG C of temperature change in positive temperature coefficient Change 13.75mV, understand to find out from the figure, when temperature change is very big, reference voltage has only changed a bit, i.e., temperature is to benchmark The data influence very little of voltage, the reference voltage of output it is extremely low with the correlation of temperature.Figure 10 is low in one embodiment When frequency is shown in the PSRR analysis chart of temperature drift reference voltage circuit, the figure less than 43.13kHz, the noise of power supply Signal can narrow down to 1% (- 41.97dB), thus, the circuit in the present embodiment under certain bandwidth when (43.13kHz), The antijamming capability of power supply very well, can preferably output reference voltage, (such as exceed when circuit exceeds certain bandwidth When 43.13kHz), the antijamming capability of power supply is poor, therefore, and the optimal use environment of the circuit in above-described embodiment is limited to 43.13kHz bandwidth below.Can be with it is clearly noted not only that when temperature change be very big into Figure 10 by above-mentioned analogous diagram 8, benchmark Voltage has only changed a bit, i.e., Low Drift Temperature reference voltage circuit realizes the reference voltage and temperature phase of output in above-described embodiment The extremely low effect of closing property, and under certain use environment, it has very strong antijamming capability, disclosure satisfy that high-precision Application demand.

Low Drift Temperature reference voltage circuit in above-described embodiment, it is all positive temperature coefficient or same directly to have using two For the first voltage unit and second voltage unit of negative temperature coefficient, calculating is caused 's K values, then design a K times of amplifying unit for calculating obtained K value sizes, and K times of amplifying unit is accessed in circuit, so that Make the reference voltage and temperature dependency of output extremely low or even unrelated, realize circuit temperature during normal work under extremely low voltage Effect of the reference voltage of difference output also without big difference, disclosure satisfy that high-precision application demand, and its circuit structure design Simply, required type of device is few, greatly reduces design difficulty and risk, has very in integrated circuit field High practicality and versatility.

Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited In contradiction, the scope of this specification record is all considered to be.

Embodiment described above only expresses several embodiments of the present utility model, and it describes more specific and detailed, But therefore it can not be interpreted as the limitation to utility model patent scope.It should be pointed out that for the common skill of this area For art personnel, without departing from the concept of the premise utility, various modifications and improvements can be made, these are belonged to Protection domain of the present utility model.Therefore, the protection domain of the utility model patent should be determined by the appended claims.

Claims (10)

1. a kind of Low Drift Temperature reference voltage circuit, it is characterised in that the Low Drift Temperature reference voltage circuit includes first voltage list Member, second voltage unit and K times of amplifying unit；

The first voltage unit, for producing first voltage, its first end ground connection；

The K times of amplifying unit, for the first voltage to be amplified into K times, the of its first end and the first voltage unit Two ends are connected, and the second end is connected with the first end of the second voltage unit, wherein, K is the constant more than zero；

The second voltage unit, for producing second voltage, its first end access current source circuit, the second end and described first The output end of reference voltage is used as after the three-terminal link of voltage cell.

2. Low Drift Temperature reference voltage circuit according to claim 1, it is characterised in that the first voltage unit includes NMOS tube MN, the second voltage unit includes PMOS MP, and the K times of amplifying unit includes resistance R1 and resistance R2, wherein：

The source electrode of the NMOS tube MN is grounded after being connected with the first end of the resistance R2, the grid of the NMOS tube MN with it is described It is connected after resistance R2 the second end connection with the first end of the resistance R1, the drain electrode of the NMOS tube MN and the PMOS MP Drain electrode and grid connection after as the reference voltage output end；

The source electrode of the PMOS MP accesses the current source circuit after being connected with the second end of the resistance R1.

3. Low Drift Temperature reference voltage circuit according to claim 1, it is characterised in that the first voltage unit includes NPN type triode QN, the second voltage unit includes PNP type triode QP, and the K times of amplifying unit includes resistance R1 and electricity R2 is hindered, wherein：

The emitter stage of the NPN type triode QN is grounded after being connected with the first end of the resistance R2, the NPN type triode QN Base stage be connected with the second end of the resistance R2 after be connected with the first end of the resistance R1, the NPN type triode QN's Colelctor electrode be connected with the colelctor electrode and base stage of the PNP type triode QP after as the reference voltage output end；

The emitter stage of the PNP type triode QP accesses the current source circuit after being connected with the second end of the resistance R1.

4. the Low Drift Temperature reference voltage circuit according to any one of claims 1 to 3, it is characterised in that the current source electricity Road includes current mirroring circuit.

5. Low Drift Temperature reference voltage circuit according to claim 4, it is characterised in that the current mirroring circuit includes PMOS Pipe MP1, PMOS MP2, PMOS MP3, NMOS tube MN1, NMOS tube MN2 and resistance Rs, wherein：

The PMOS MP1, the PMOS MP2 and the PMOS MP3 source electrode access same power supply, the PMOS Grid of MP2 and the PMOS MP3 grid with the PMOS MP1 is connected, and grid and the institute of the PMOS MP3 State PMOS MP2 drain electrode connection；

The drain electrode of the PMOS MP1 is connected with the drain and gate of the NMOS tube MN1, and the source electrode of the NMOS tube MN1 connects Ground；

The drain electrode of the PMOS MP2 is connected with the drain electrode of the NMOS tube MN2, the grid of the NMOS tube MN2 with it is described NMOS tube MN1 grid connection, and the source electrode of the NMOS tube MN2 be connected with the resistance Rs after ground connection；

The drain electrode of the PMOS MP3 is connected with the first end of the second voltage unit.

6. a kind of Low Drift Temperature reference voltage circuit, it is characterised in that the Low Drift Temperature reference voltage circuit includes first voltage list Member, second voltage unit and K times of amplifying unit；

The first voltage unit, for producing first voltage, its first end ground connection；

The K times of amplifying unit, for the first voltage to be amplified into K times, the of its first end and the first voltage unit Two ends are connected, and current source circuit is accessed after the three-terminal link of the second end and the first voltage unit, wherein, K is more than zero Constant；

The second voltage unit, for producing second voltage, its first end and the three-terminal link of the first voltage unit After access the current source circuit, the second end as reference voltage output end.

7. Low Drift Temperature reference voltage circuit according to claim 6, it is characterised in that the first voltage unit includes PMOS MP and metal-oxide-semiconductor M1, the second voltage unit includes NMOS tube MN and metal-oxide-semiconductor M2, and the K times of amplifying unit includes electricity R1 and resistance R2 is hindered, wherein：

The grid of the PMOS MP is connected with the first end of the resistance R1 and the first end of the resistance R2, the PMOS MP source electrode accesses current source circuit, drain electrode and the MOS of the PMOS MP after being connected with the second end of the resistance R1 Pipe M1 grid and drain electrode are connected, the source ground of the metal-oxide-semiconductor M1, the second end ground connection of the resistance R2；

The grid and the drain electrode access current source circuit of the NMOS tube MN, the source electrode of the NMOS tube MN is used as the benchmark The output end of voltage, and being connected with the drain electrode of the metal-oxide-semiconductor M2, the grid of the metal-oxide-semiconductor M2 and the metal-oxide-semiconductor M1 grid and Drain electrode connection, the source ground of the metal-oxide-semiconductor M2.

8. Low Drift Temperature reference voltage circuit according to claim 6, it is characterised in that the first voltage unit includes PNP type triode QP and triode Q1, second voltage unit includes NPN type triode QN and triode Q2, and described K times is amplified list Member includes resistance R1 and resistance R2, wherein：

The base stage of the PNP type triode QP is connected with the first end of the resistance R1 and the first end of the resistance R2, described PNP type triode QP emitter stage accesses current source circuit, the PNP type triode after being connected with the second end of the resistance R1 QP colelctor electrode is connected with the base stage and colelctor electrode of the triode Q1, the grounded emitter of the triode Q1, the resistance R2 the second end ground connection；

The base stage and colelctor electrode of the NPN type triode QN accesses the current source circuit, the transmitting of the NPN type triode QN Pole and is connected as the output end of the reference voltage with the colelctor electrode of the triode Q2, the base stage of the triode Q2 with Base stage and the colelctor electrode connection of the triode Q1, the grounded emitter of the triode Q2.

9. the Low Drift Temperature reference voltage circuit according to any one of claim 6 to 8, it is characterised in that the current source electricity Road includes current mirroring circuit.

10. Low Drift Temperature reference voltage circuit according to claim 9, it is characterised in that the current mirroring circuit includes PMOS MP1, PMOS MP2, PMOS MP3, NMOS tube MN1, NMOS tube MN2 and resistance Rs, wherein：

The PMOS MP1, the PMOS MP2 and the PMOS MP3 source electrode access same power supply, the PMOS Grid of MP2 and the PMOS MP3 grid with the PMOS MP1 is connected, and grid and the institute of the PMOS MP3 State PMOS MP2 drain electrode connection；

The drain electrode of the PMOS MP1 is connected with the drain and gate of the NMOS tube MN1, and the source electrode of the NMOS tube MN1 connects Ground；

The drain electrode of the PMOS MP2 is connected with the drain electrode of the NMOS tube MN2, the grid of the NMOS tube MN2 with it is described NMOS tube MN1 grid connection, and the source electrode of the NMOS tube MN2 be connected with the resistance Rs after ground connection；

The drain electrode of the PMOS MP3 is connected with the first end of the second voltage unit.