CN206250189U - 一种无基岛框架封装结构 - Google Patents

一种无基岛框架封装结构 Download PDF

Info

Publication number
CN206250189U
CN206250189U CN201621140849.XU CN201621140849U CN206250189U CN 206250189 U CN206250189 U CN 206250189U CN 201621140849 U CN201621140849 U CN 201621140849U CN 206250189 U CN206250189 U CN 206250189U
Authority
CN
China
Prior art keywords
island
framework
chip
free
free framework
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201621140849.XU
Other languages
English (en)
Inventor
殷炯
王强
龚臻
刘怡
章春燕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201621140849.XU priority Critical patent/CN206250189U/zh
Application granted granted Critical
Publication of CN206250189U publication Critical patent/CN206250189U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本实用新型涉及一种无基岛框架封装结构,它包括无基岛框架(1),所述无基岛框架(1)正面贴覆有固化膜(2),所述固化膜(2)上设置有芯片(3),所述芯片(3)与无基岛框架(1)通过电性连接部件(4)进行电性连接,所述无基岛框架(1)、固化膜(2)、电性连接部件(4)外均包封有塑封料(5),所述无基岛框架(1)背面露出于塑封料(5)。本实用新型一种无基岛框架封装结构,它在无基岛框架上贴固化膜固化后形成基岛作用的芯片支撑结构,能够有效解决芯片与管脚接触面积太小导致打线不稳晃动或打线时芯片抬起的问题,同时也能够避免预包封框架两侧铜面积比例差异大导致的框架翘曲问题。

Description

一种无基岛框架封装结构
技术领域
本实用新型涉及一种无基岛框架封装结构,属于半导体封装技术领域。
背景技术
目前通过蚀刻形成的引线框架无基岛产品,芯片装片时是架在管脚上的。实际上,当芯片架在管脚上,由于芯片与管脚接触面积太小,导致打线不稳晃动或打线时芯片受力一边抬起的异常现象。
无基岛预包封框架虽然可以通过预填塑封料达到支撑芯片的目的,但是无基岛预包封框架由于框架两侧铜面积比例差异大,会产生框架翘曲问题,并且装片胶会在塑封料上扩散,沾污到框架管脚上,影响产品良率及可靠性。
发明内容
本实用新型所要解决的技术问题是针对上述现有技术提供一种无基岛框架封装结构,它在无基岛框架上贴固化膜固化后形成基岛作用的芯片支撑结构,能够有效解决芯片与管脚接触面积太小导致打线不稳晃动或打线时芯片一侧抬起的问题,同时也能够避免预包封框架两侧铜面积比例差异大导致的框架翘曲问题。
本实用新型解决上述问题所采用的技术方案为:一种无基岛框架封装结构,它包括无基岛框架,所述无基岛框架正面贴覆有固化膜,所述固化膜上设置有芯片,所述芯片与无基岛框架通过电性连接部件进行电性连接,所述无基岛框架、固化膜、电性连接部件外均包封有塑封料,所述无基岛框架背面露出于塑封料。
与现有技术相比,本实用新型的优点在于:
1、在无基岛框架上贴固化膜固化后形成基岛作用的芯片支撑结构,能够加强框架的支撑能力,能够有效解决芯片与管脚接触太小导致打线不稳晃动或打线时芯片一侧抬起的问题,提高打线时芯片的稳定性与产品良率;
2、与预包封技术相比:(1)可以避免框架的翘曲问题;(2)可以避免芯片装片胶在塑封料上的扩散(装片胶在此种膜上扩散管控效果很好)。
附图说明
图1为本实用新型一种无基岛框架封装结构的示意图。
图2~图7为本实用新型一种无基岛框架封装工艺的各工序流程图。
其中:
无基岛框架1
固化膜2
芯片3
电性连接部件4
塑封料5。
具体实施方式
以下结合附图实施例对本实用新型作进一步详细描述。
如图1所示,本实施例中的一种无基岛框架封装结构,它包括无基岛框架1,所述无基岛框架1正面贴覆有固化膜2,所述固化膜2上设置有芯片3,所述芯片3与无基岛框架1通过电性连接部件4进行电性连接,所述无基岛框架1、固化膜2、电性连接部件4外均包封有塑封料5,所述无基岛框架1背面露出于塑封料5。
其工艺方法如下:
步骤一、参见图2,将固化膜设置在转换膜上,根据无基岛框架的尺寸加工成所需大小,固化膜可以是FOW膜或是FOD膜等;
上述固化膜的特性:此膜在固化前具有半流动性,通过转换贴膜、对位方法贴装在镂空框架上时不会从框架间隙流到框架背面沾污外形;当通过加热时,膜由半流动状态转变为固态,在此过程中也不会从框架间隙流到框架背面,此膜转化成固态后,在常温下或再次加热也不会恢复成半流动状态;
步骤二、参见图3,将转换膜设置有固化膜的一面贴在无基岛框架的内引脚上,使固化膜贴在无基岛框架的内引脚上;
步骤三、参见图4,将固化膜进行固化,固化膜完成固化之后去除转换膜;
步骤四、参见图5,在固化膜上通过装片胶进行正装芯片;
步骤五、参见图6,电性连接部件电性连接芯片和无基岛框架,电性连接部件是焊线;
步骤六、参见图7,包封,用塑封料包覆框架、固化膜、芯片、电性连接部件,并且无基岛框架背面露出于塑封料。
除上述实施例外,本实用新型还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本实用新型权利要求的保护范围之内。

Claims (1)

1.一种无基岛框架封装结构,其特征在于:它包括无基岛框架(1),所述无基岛框架(1)正面贴覆有固化膜(2),所述固化膜(2)上设置有芯片(3),所述芯片(3)与无基岛框架(1)通过电性连接部件(4)进行电性连接,所述无基岛框架(1)、固化膜(2)、电性连接部件(4)外均包封有塑封料(5),所述无基岛框架(1)背面露出于塑封料(5)。
CN201621140849.XU 2016-10-20 2016-10-20 一种无基岛框架封装结构 Active CN206250189U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201621140849.XU CN206250189U (zh) 2016-10-20 2016-10-20 一种无基岛框架封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201621140849.XU CN206250189U (zh) 2016-10-20 2016-10-20 一种无基岛框架封装结构

Publications (1)

Publication Number Publication Date
CN206250189U true CN206250189U (zh) 2017-06-13

Family

ID=58996149

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201621140849.XU Active CN206250189U (zh) 2016-10-20 2016-10-20 一种无基岛框架封装结构

Country Status (1)

Country Link
CN (1) CN206250189U (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106373935A (zh) * 2016-10-20 2017-02-01 江苏长电科技股份有限公司 一种无基岛框架封装工艺及其封装结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106373935A (zh) * 2016-10-20 2017-02-01 江苏长电科技股份有限公司 一种无基岛框架封装工艺及其封装结构
CN106373935B (zh) * 2016-10-20 2019-04-16 江苏长电科技股份有限公司 一种无基岛框架封装工艺及其封装结构

Similar Documents

Publication Publication Date Title
CN102324413B (zh) 有基岛预填塑封料先刻后镀引线框结构及其生产方法
CN102324415B (zh) 无基岛预填塑封料先刻后镀引线框结构及其生产方法
CN106784031A (zh) 一种新型光电传感器的封装件
CN104752386B (zh) 高可靠性sop封装引线框架及封装件生产方法
CN206250189U (zh) 一种无基岛框架封装结构
CN106373935B (zh) 一种无基岛框架封装工艺及其封装结构
CN102324414B (zh) 有基岛预填塑封料先镀后刻引线框结构及其生产方法
CN206163483U (zh) 包括薄膜体声波器件裸芯片在内的多芯片模组封装结构
CN104810462B (zh) 一种中大功率led驱动芯片的esop8引线框架
CN100587946C (zh) 窗口上下模流平衡的封装构造与封装方法
CN203674202U (zh) 一种高可靠性sop封装引线框架
CN202084532U (zh) To92型号封装盒及配套模具
CN104617052A (zh) 一种采用预置胶膜工艺封装的智能卡模块及其封装方法
CN204216033U (zh) 引线框架、半导体封装体
CN103107098B (zh) 方形扁平无引脚的封装方法及其封装结构
CN107808872B (zh) 一种腔体向下的球栅阵列塑料封装制备方法
CN208938954U (zh) 一种无基岛框架封装结构
CN204441277U (zh) 一种采用预置胶膜工艺封装的智能卡模块
CN202150453U (zh) 一种双扁平无载体无引线内引脚交错型ic芯片封装件
CN206116376U (zh) 一种to全包封封装结构
CN104600044A (zh) 一种微型智能卡及封装方法
CN104538378A (zh) 一种圆片级封装结构及其工艺方法
CN204668297U (zh) 一种矩阵列smbf引线框架
CN104465586B (zh) 一种圆片级封装结构及其工艺方法
CN104485287B (zh) 包含溢流槽的新型qfn框架的制备方法

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant