CN206249290U - A kind of server test device - Google Patents
A kind of server test device Download PDFInfo
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- CN206249290U CN206249290U CN201621328695.7U CN201621328695U CN206249290U CN 206249290 U CN206249290 U CN 206249290U CN 201621328695 U CN201621328695 U CN 201621328695U CN 206249290 U CN206249290 U CN 206249290U
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- 238000012360 testing method Methods 0.000 title claims abstract description 89
- 230000003993 interaction Effects 0.000 claims description 6
- 238000004891 communication Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 10
- 230000005611 electricity Effects 0.000 abstract description 3
- 238000011990 functional testing Methods 0.000 abstract description 3
- 230000002159 abnormal effect Effects 0.000 description 2
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- 238000010586 diagram Methods 0.000 description 1
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Abstract
The utility model provides a kind of server test device, high speed connector and plant-grid connection module are carried out physical connection by test board with server to be tested respectively, and unlatching 12V power supplys supply electricity to server to be measured and power, power-on switch, test board is powered, start test.The test node of server to be measured can be accessed by BMC management network ports, and treat testing service device each node and tested, so test board realizes treating the functional test of testing service device node, without be put into server to be tested in test cabinet again by whole test process, as long as server to be tested and test board are carried out into physical connection, test process is just realized, improve testing efficiency, ensure the degree of accuracy of test, reduce the risk of striker in test process.The electrifying timing sequence that fpga chip controls whole test board is employed, the reliability of system is improve, the operation power consumption of test system is reduced.
Description
Technical field
The utility model is related to server test field, more particularly to a kind of server test device.
Background technology
Server after the factory-assembled will to assembling after node carry out a series of test, it is necessary to will clothes during test
Business device is put into test cabinet, easily makes server to be measured that striker occur with test cabinet in placement process, causes clothes to be measured
Business device internal component damage, influence server is used.
The content of the invention
In order to overcome above-mentioned deficiency of the prior art, the purpose of this utility model to be, there is provided a kind of server test
Device, including：Test board；Test board includes：Multiple high speed connectors, SFP network interfaces, a PCIE slots, the 2nd PCIE
Slot, BMC management network ports, plant-grid connection module, with the power supply that plant-grid connection module is connected to control test board on/off
Switch, BMC managing chips, GPIOLED display lamps and be connecteds Header debugging boards with plant-grid connection module, for will access
Power convert into element manipulation voltage on test board voltage changing module；
SFP network interfaces, BMC management network ports, a PCIE slots are one group, are respectively connecting to the first high speed connector；
2nd PCIE slots are connected to the second high speed connector；
SFP network interfaces, BMC management network ports, GPIO LED display lamps and Header debugging boards respectively with BMC managing chips
Connection.
Preferably, plant-grid connection module includes：PSU interfaces and power patch panel；
Power patch panel is connected with PSU interfaces, and PSU interfaces are connected with voltage changing module.
Preferably, test board also includes：Fpga chip, TPS2363PFB controllers and two PCA95555 modules；
TPS2363PFB controllers are connected by a PCA95555 modules with a PCIE slots；
TPS2363PFB controllers are connected by the 2nd PCA95555 modules with the 2nd PCIE slots；
The first end of fpga chip is connected with a PCIE slots, the second end and a PCA95555 modules of fpga chip
Connection, the 3rd end of fpga chip is connected with the 2nd PCA95555 modules, and the 4th end and the 2nd PCIE slots of fpga chip connect
Connect；
First PCIE slots and the 2nd PCIE slots be × 16 PCIE slots.
Preferably, SFP network interfaces are provided with two 744410001 connectors, and two 744410001 connectors are respectively with
One high speed connector is connected；
BMC management network ports are provided with two 744410001 connectors, and two 744410001 connectors are respectively with first at a high speed
Connector is connected.
Preferably, test board also includes：Signal interconnect device；
Signal interconnect device includes：First PCIE interface boards, the 3rd high speed connector being connected with a PCIE interface boards,
2nd PCIE interface boards, respectively the 4th high speed connector being connected with the 2nd PCIE interface boards and the 3rd high speed connector of connection
With the 4th high speed connector, the 3rd high speed connector and the 4th high speed connector is set to enter the data interaction line of row data communication；
First PCIE interface boards are connected with a PCIE slots, the PCIE buses of the 2nd PCIE interface boards and testing service device
Connection；
Data interaction line is provided with the 5th high speed connector being connected with the 3rd high speed connector, and the 4th high speed connector connects
The FPC of the 6th high speed connector for connecing, the 5th high speed connector of connection and the 6th high speed connector.
Preferably, high speed connector model ERNI Vertical Male Connectors.
Preferably, 744410001 connectors are provided with RJ45 connector.
As can be seen from the above technical solutions, the utility model has advantages below：
High speed connector and plant-grid connection module are carried out physical connection by test board with server to be tested respectively, are opened
12V power supplys supply electricity to server to be measured and power, power-on switch, test board is powered, and start to treat testing service device and are surveyed
Examination.The test node of server to be measured can be accessed by BMC management network ports, and treats testing service device each node and be surveyed
Examination, if the functional exception of node shows abnormal signal, Header debugging boards by BMC managing chips by GPIOLED display lamps
Server exception node can be positioned.So test board realizes treating the functional test of testing service device node, whole
Individual test process is tested in cabinet without being again put into server to be tested, as long as server to be tested and test board are carried out into thing
Reason connection, just realizes test process, improves testing efficiency, it is ensured that the degree of accuracy of test, reduces the risk of striker in test process.
The electrifying timing sequence that fpga chip controls whole test board is employed, the reliability of system is improve, the operation of test system is reduced
Power consumption.
Brief description of the drawings
In order to illustrate more clearly of the technical solution of the utility model, the accompanying drawing to be used needed for description will be made below
Simply introduce, it should be apparent that, drawings in the following description are only some embodiments of the present utility model, for this area
For those of ordinary skill, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the overall schematic of server test device；
Fig. 2 is signal interconnect device schematic diagram.
Specific embodiment
It is specific below in conjunction with this to enable that the purpose of this utility model, feature, advantage are more obvious and understandable
Accompanying drawing in embodiment, is clearly and completely described, it is clear that disclosed below to the technical scheme in the utility model
Embodiment is only a part of embodiment of the utility model, and not all embodiment.Based on the embodiment in this patent, ability
All other embodiment that domain those of ordinary skill is obtained under the premise of creative work is not made, belongs to this patent guarantor
The scope of shield.
The utility model provides a kind of server test device, as shown in figure 1, including：Test board；Test board includes：
Multiple high speed connectors, SFP network interfaces 1, a PCIE slots 3, the 2nd PCIE slots 4, BMC management network ports 2, plant-grid connection
Module, with the power switch 6 that plant-grid connection module is connected to control test board on/off, BMC managing chips 7, GPIOLED
Display lamp 8, Header debugging boards 9 and is connected with plant-grid connection module, for the Power convert that will access into unit on test board
The voltage changing module 10 of part operating voltage；SFP network interfaces 1, BMC management network ports 2, a PCIE slots 3 are connected to for one group
One high speed connector 17；2nd PCIE slots 4 are connected to the second high speed connector 18；
SFP network interfaces 1, BMC management network ports 2, GPIO LED display lamps 8 and Header debugging boards 9 are managed with BMC respectively
Chip 7 is connected.GPIOLED display lamps 8 are connected with BMC managing chips 7, by BMC managing chips 7 to treat testing service device each
Individual node is processed, and is used for representing that whether normal server to be tested each node is by the light on and off of GPIOLED display lamps 8.
BMC management network ports are servomechanism remote side administration controller (Baseboard management controller).It is high
Fast connector model ERNI Vertical Male Connectors.
In the present embodiment, test board also includes：Fpga chip 20, TPS2363PFB controllers 11, two PCA95555 moulds
Block；TPS2363PFB controllers 11 are connected by a PCA95555 modules 12 with a PCIE slots 3；TPS2363PFB is controlled
Device 11 is connected 4 by the 2nd PCA95555 modules 13 with the 2nd PCIE slots；First PCIE slots 3 and the 2nd PCIE slots 4 are equal
It is × 16 PCIE slots.The first end of fpga chip 20 is connected with a PCIE slots, second end and first of fpga chip
PCA95555 modules are connected, and the 3rd end of fpga chip is connected with the 2nd PCA95555 modules, the 4th end of fpga chip and the
Two PCIE slots are connected.The electrifying timing sequence that fpga chip controls whole test board is employed, the reliability of system is improve, reduced
The operation power consumption of test system.
Plant-grid connection module includes：PSU interfaces 14, power patch panel 15；Power patch panel 15 is connected with PSU interfaces 14,
PSU interfaces 14 are connected with voltage changing module 10.PSU interfaces（Power supply unit, the supply unit of server）For power supply connects
Device is connect, two 12v electric power connection lines are connected with.
SFP network interfaces 1 are provided with two 744410001 connectors 16, and two 744410001 connectors 16 are respectively with first
High speed connector 17 is connected；BMC management network ports 2 also are provided with two 744410001 connectors 16, this two 744410001 connections
Device 16 is connected with the first high speed connector 17 respectively.744410001 connectors are provided with RJ45 connector.
TPS2363PFB is hot-swappable controller.PCA95555 modules have the long-range of interrupt output and configuration register
16 I2C and SMBus I/O expanders, I/O extended chips, IIC interfaces, expansible 16 road I/O.Such PCIE is inserted
The PCIE slots 4 of groove 3 and the 2nd for support hot plug × 16 PCIE slots.
High speed connector and plant-grid connection module are carried out physical connection by test board with server to be tested respectively, are opened
12V power supplys supply electricity to server to be measured and power, power-on switch, test board is powered, and start to treat testing service device and are surveyed
Examination.The test node of server to be measured can be accessed by BMC management network ports, and treats testing service device each node and be surveyed
Examination, if the functional exception of node shows abnormal signal, Header debugging boards by BMC managing chips by GPIOLED display lamps
Server exception node can be positioned.So test board realizes treating the functional test of testing service device node, whole
Individual test process is tested in cabinet without being again put into server to be tested, as long as server to be tested and test board are carried out into thing
Reason connection, just realizes test process, improves testing efficiency, it is ensured that the degree of accuracy of test, reduces the risk of striker in test process.
In the present embodiment, as shown in Fig. 2 test board also includes：Signal interconnect device；
Signal interconnect device includes：First PCIE interface boards 21, the 3rd high speed being connected with a PCIE interface boards 21 connects
Connect device 22, the 2nd PCIE interface boards 23 and are connected the 4th high speed connector 24 being connected with the 2nd PCIE interface boards 23 respectively
3rd high speed connector 22 and the 4th high speed connector 24, make the 3rd high speed connector 22 and the 4th high speed connector 24 enter line number
According to the data interaction line of communication；
First PCIE interface boards 21 are connected with a PCIE slots 3, the 2nd PCIE interface boards 23 and testing service device
PCIE buses are connected；So test board is connected with server to be tested by signal interconnect device, makes test board with clothes to be tested
Signal quality higher is obtained between business device, with data reliability higher and data fluency.
Data interaction line is provided with the 5th high speed connector 25 being connected with the 3rd high speed connector 22, and the 4th connects at a high speed
The FPC of the 6th high speed connector 26 of the connection of device 24, the 5th high speed connector 25 of connection and the 6th high speed connector 26
27。
Each embodiment is described by the way of progressive in this specification, and what each embodiment was stressed is and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.
Term " first " in specification and claims of the present utility model and above-mentioned accompanying drawing, " second ", " the 3rd "
" 4th " etc.（If there is）It is for distinguishing similar object, without for describing specific order or precedence.Should
The data that the understanding is so used can be exchanged in the appropriate case, so that embodiment of the present utility model described herein can
Implemented with the order in addition to those for illustrating herein or describing.Additionally, term " comprising " and " having " and they
Any deformation, it is intended that covering is non-exclusive to be included.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or new using this practicality
Type.Various modifications to these embodiments will be apparent for those skilled in the art, determine herein
The General Principle of justice can in other embodiments be realized in the case where spirit or scope of the present utility model are not departed from.Cause
This, the utility model is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein
The most wide scope consistent with features of novelty.
Claims (7)
1. a kind of server test device, it is characterised in that including：Test board；Test board includes：Multiple high speed connectors, SFP
Network interface, a PCIE slots, the 2nd PCIE slots, BMC management network ports, plant-grid connection module connects with plant-grid connection module
Connect the power switch for controlling test board on/off, BMC managing chips, GPIOLED display lamps, Header debugging boards and
Be connected with plant-grid connection module, for will access Power convert into element manipulation voltage on test board voltage changing module；
SFP network interfaces, BMC management network ports, a PCIE slots are one group, are respectively connecting to the first high speed connector；Second
PCIE slots are connected to the second high speed connector；
SFP network interfaces, BMC management network ports, GPIO LED display lamps and Header debugging boards connect with BMC managing chips respectively
Connect.
2. server test device according to claim 1, it is characterised in that
Plant-grid connection module includes：PSU interfaces and power patch panel；
Power patch panel is connected with PSU interfaces, and PSU interfaces are connected with voltage changing module.
3. server test device according to claim 1 and 2, it is characterised in that
Test board also includes：Fpga chip, TPS2363PFB controllers and two PCA95555 modules；
TPS2363PFB controllers are connected by a PCA95555 modules with a PCIE slots；
TPS2363PFB controllers are connected by the 2nd PCA95555 modules with the 2nd PCIE slots；
The first end of fpga chip is connected with a PCIE slots, and the second end and a PCA95555 modules of fpga chip connect
Connect, the 3rd end of fpga chip is connected with the 2nd PCA95555 modules, the 4th end of fpga chip is connected with the 2nd PCIE slots；
First PCIE slots and the 2nd PCIE slots be × 16 PCIE slots.
4. server test device according to claim 1 and 2, it is characterised in that
SFP network interfaces are provided with two 744410001 connectors, and two 744410001 connectors are connected at a high speed with first respectively
Device is connected；
BMC management network ports are provided with two 744410001 connectors, and two 744410001 connectors are connected at a high speed with first respectively
Device is connected.
5. server test device according to claim 1 and 2, it is characterised in that
Test board also includes：Signal interconnect device；
Signal interconnect device includes：First PCIE interface boards, the 3rd high speed connector being connected with a PCIE interface boards, second
PCIE interface boards, respectively the 4th high speed connector being connected with the 2nd PCIE interface boards and the 3rd high speed connector of connection and the
Four high speed connectors, make the 3rd high speed connector and the 4th high speed connector enter the data interaction line of row data communication；
First PCIE interface boards are connected with a PCIE slots, and the 2nd PCIE interface boards connect with the PCIE buses of testing service device
Connect；
Data interaction line is provided with the 5th high speed connector being connected with the 3rd high speed connector, the connection of the 4th high speed connector
The FPC of the 6th high speed connector, the 5th high speed connector of connection and the 6th high speed connector.
6. server test device according to claim 1, it is characterised in that
High speed connector model ERNI Vertical Male Connectors.
7. server test device according to claim 4, it is characterised in that
744410001 connectors are provided with RJ45 connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621328695.7U CN206249290U (en) | 2016-12-06 | 2016-12-06 | A kind of server test device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621328695.7U CN206249290U (en) | 2016-12-06 | 2016-12-06 | A kind of server test device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206249290U true CN206249290U (en) | 2017-06-13 |
Family
ID=59003614
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621328695.7U Expired - Fee Related CN206249290U (en) | 2016-12-06 | 2016-12-06 | A kind of server test device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107577216A (en) * | 2017-08-03 | 2018-01-12 | 郑州云海信息技术有限公司 | A kind of method that debugging signal is captured outside FPGA platform upper piece |
| CN109634397A (en) * | 2018-12-07 | 2019-04-16 | 郑州云海信息技术有限公司 | A kind of system and method for realizing intelligent network adapter or more Electricity Functional |
| CN111694340A (en) * | 2020-06-05 | 2020-09-22 | 浪潮电子信息产业股份有限公司 | Automatic test fixture and method for PSU BootLoader |
| CN111880974A (en) * | 2020-06-29 | 2020-11-03 | 苏州浪潮智能科技有限公司 | Device and method compatible with multi-type server test |
-
2016
- 2016-12-06 CN CN201621328695.7U patent/CN206249290U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107577216A (en) * | 2017-08-03 | 2018-01-12 | 郑州云海信息技术有限公司 | A kind of method that debugging signal is captured outside FPGA platform upper piece |
| CN109634397A (en) * | 2018-12-07 | 2019-04-16 | 郑州云海信息技术有限公司 | A kind of system and method for realizing intelligent network adapter or more Electricity Functional |
| CN111694340A (en) * | 2020-06-05 | 2020-09-22 | 浪潮电子信息产业股份有限公司 | Automatic test fixture and method for PSU BootLoader |
| CN111880974A (en) * | 2020-06-29 | 2020-11-03 | 苏州浪潮智能科技有限公司 | Device and method compatible with multi-type server test |
| CN111880974B (en) * | 2020-06-29 | 2022-10-18 | 苏州浪潮智能科技有限公司 | Device and method compatible with multi-type server test |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170613 Termination date: 20181206 |
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| CF01 | Termination of patent right due to non-payment of annual fee |