CN113885686A

CN113885686A - Power management device, edge computing device, and edge computing system

Info

Publication number: CN113885686A
Application number: CN202110970459.4A
Authority: CN
Inventors: 孙坚; 刘勇; 邓兵
Original assignee: Alibaba China Co Ltd
Current assignee: Alibaba China Co Ltd
Priority date: 2021-08-23
Filing date: 2021-08-23
Publication date: 2022-01-04
Anticipated expiration: 2041-08-23
Also published as: CN113885686B

Abstract

The embodiment of the present disclosure relates to a power management device, an edge computing device and an edge computing system, wherein the power management device includes: the power supply management system comprises at least one power supply management unit, a power supply management unit and a power supply management unit, wherein each power supply management unit comprises a mode switching switch, a power supply loading circuit, a power receiving power supply separating circuit, a power line and a network transmission line; the mode switching switch is used for selectively conducting the power supply loading circuit and the power line or conducting the power receiving power supply separation circuit and the power line according to the working mode; the power supply loading circuit is used for loading the direct current transmitted from the power line to the network transmission line; the power receiving and power separating circuit is used for separating direct current transmitted from a network transmission line to a power line, and the network transmission line is connected with the edge computing equipment. Therefore, the power supply and receiving functions can be separated from the edge computing equipment by utilizing the power supply management equipment, the independent deployment and the flexible adaptation can be realized, and the problems of over-design, poor configuration flexibility and high cost can be solved.

Description

Power management device, edge computing device, and edge computing system

Technical Field

The present disclosure relates to the field of edge computing technologies, and in particular, to a power management device, an edge computing device, and an edge computing system.

Background

The edge calculation, also called distributed calculation, fog calculation or multilateral calculation, has the main advantage that the integration, analysis and calculation feedback of mass equipment data can be completed at the data acquisition end or the system edge end. The edge computing can save communication bandwidth, reduce network delay, reduce data traffic, improve system security and confidentiality, rely less on storage and computing resources, and improve reliability and control of edge devices. The edge calculation may be performed in an edge calculation device. Illustratively, edge computing devices include intelligent sensors, programmable logic controllers, edge intelligent routers, and Information Communication Technology (ICT) convergence gateways, among other devices that may implement data processing locally.

Active Ethernet (POE) refers to a technology that can provide dc Power for edge computing devices while transmitting data signals to IP-based terminals (such as IP phones, wireless lan access points AP or network cameras, etc.) without any modification to the existing Ethernet cat.5 wiring infrastructure.

In the prior art, the edge computing Device has different POE requirements in the deployment process, and there is a POE deployment scenario as non-POE deployment, Power Sourcing Equipment (PSE), and Powered Device (PD) according to the deployment scenario, and the integrated PSE or PD function inside the edge computing Device may cause over-design on the system side, poor configuration flexibility of the PSE and the PD, and extra cost.

Disclosure of Invention

To solve the technical problem or at least partially solve the technical problem, embodiments of the present disclosure provide a power management device, an edge computing device, and an edge computing system.

In a first aspect, an embodiment of the present disclosure provides a power management apparatus, including at least one power management unit, where each power management unit includes a mode switch, a power supply loading circuit, a power receiving power splitting circuit, a power line, and a network transmission line;

the mode switch is used for selectively conducting the power supply loading circuit and the power line or conducting the power receiving power supply separation circuit and the power line according to a working mode;

the power supply loading circuit is used for loading the direct current transmitted from the power line onto the network transmission line;

the power receiving power supply separation circuit is used for separating the direct current transmitted from the network transmission line to the power supply line;

the network transmission line is connected to an edge computing device.

In a second aspect, an embodiment of the present disclosure further provides an edge computing device, where the edge computing device is connected to a power management device, the edge computing device includes a core board and a substrate, where the core board is provided with an edge computing function chip, the substrate is provided with a signal transmission interface, and the edge computing function chip on the core board is connected to the signal transmission interface on the substrate through at least one connector;

the signal transmission interface comprises a network signal interface, and the network signal interface is connected with a network transmission line.

In a third aspect, an embodiment of the present disclosure further provides an edge computing system, including: any of the power management devices provided by the embodiments of the present disclosure, and any of the edge computing devices provided by the embodiments of the present disclosure.

Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has at least the following advantages: in the disclosed embodiment, the power management apparatus includes at least one power management unit, each power management unit including a mode switch, a power supply loading circuit, a power receiving power separating circuit, a power line, and a network transmission line; the mode switching switch can selectively conduct the power supply loading circuit and the power line according to the working mode, the power supply loading circuit is used for loading direct current transmitted from the power line onto a network transmission line, at the moment, the network transmission line can be used for transmitting the direct current, and edge computing equipment configured with the power management equipment can be used as PSE at the moment and can supply power to post-stage equipment connected with the PSE; or, the mode switch can selectively connect the power receiving power separating circuit and the power line according to the operating mode, the power receiving power separating circuit is used for separating the direct current transmitted from the network transmission line to the power line, and at this time, the direct current is separated from the network transmission line and transmitted to the power receiving equipment through the power line, so that power can be supplied to the power receiving equipment. Therefore, by arranging the power management equipment, the coupling and the separation of direct current and a network transmission line can be realized, the power supply and the power receiving functions can be stripped from the edge computing equipment on the system side, independent deployment and flexible configuration are realized, the PSE or PD function is not required to be integrated inside the edge computing equipment, the over-design on the system side is avoided, and the problems of poor configuration flexibility and extra cost of the PSE and the PD are improved.

Drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numbers refer to the same or similar elements. It should be understood that the drawings are schematic and that elements and features are not necessarily drawn to scale.

Fig. 1 is a schematic structural diagram of a power management device according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another power management device provided in the embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of another power management device provided in the embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another power management device provided in the embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a cascade of four power management units according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a single power management unit according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of an edge computing device according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a core board according to an embodiment of the disclosure;

fig. 9 is a schematic structural diagram of another core board according to an embodiment of the present disclosure;

fig. 10 is a schematic diagram illustrating a corresponding connection relationship between a core board and a substrate according to an embodiment of the disclosure;

fig. 11 is a schematic structural diagram of a connector according to an embodiment of the disclosure;

fig. 12 is a schematic diagram illustrating a terminal arrangement of a connector according to an embodiment of the disclosure;

fig. 13 is a schematic cross-sectional view taken along a line a1-a2 in the core board shown in fig. 9;

fig. 14 is a schematic partial plan view of another core board according to an embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.

It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order, and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.

The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description.

It should be noted that the terms "first", "second", and the like in the present disclosure are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence relationship of the functions performed by the devices, modules or units.

It is noted that references to "a", "an", and "the" modifications in this disclosure are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that "one or more" may be used unless the context clearly dictates otherwise.

Before explaining the power management device, the edge computing device, and the edge computing system provided by the embodiments of the present disclosure, terms that may be referred to in the embodiments of the present disclosure are explained.

POE: power Over Ethernet, active Ethernet, refers to a technology that can provide dc Power for some IP-based terminals while transmitting data signals (i.e., network signals) for such devices under the existing Ethernet infrastructure.

PSE: the Power Sourcing Equipment comprises Power Sourcing Equipment and Equipment for supplying Power to other terminal Equipment.

PD: a Power Device, a Power receiving Device, and a Device receiving Power from another terminal Device.

ECM: edge Computing Module, the core plate for provide different Computing power, support SoC operation core, connect the base plate through the connector.

EBB: edge Computing basepad, base plate, be used for connecting the core plate.

The power management device provided by the disclosure can be configured in a system network, for example, can be configured on the side of an edge computing device, and realizes power supply/power receiving. The power management device comprises at least one power management unit, wherein each power management unit comprises a mode switching switch, a power supply loading circuit, a power receiving power supply separation circuit, a power line and a network transmission line; the mode switching switch can selectively conduct the power supply loading circuit and the power line according to the working mode, the power supply loading circuit is used for loading direct current transmitted from the power line onto a network transmission line, at the moment, the network transmission line can be used for transmitting the direct current, and edge computing equipment configured with the power management equipment can be used as PSE at the moment and can supply power to post-stage equipment connected with the PSE; or, the mode switch can selectively connect the power receiving power separating circuit and the power line according to the operating mode, the power receiving power separating circuit is used for separating the direct current transmitted from the network transmission line to the power line, at this time, the direct current is separated from the network transmission line, the direct current can be transmitted to the power receiving equipment through the power line, and then the power supply of the power receiving equipment connected with the power line can be realized. Therefore, through the arrangement of the power management equipment connected with the edge computing equipment through the network transmission line, the coupling and the separation of direct current and the network transmission line can be realized, the power supply and the power receiving functions can be stripped from the edge computing equipment on the system side, the independent deployment and the flexible configuration are realized, the PSE or PD functions are not required to be integrated inside the edge computing equipment, the over-design on the system side is avoided, and the problems that the configuration flexibility of the PSE and the PD is poor and extra cost is paid are solved. Furthermore, the requirement of high-power supply/power receiving can be met by cascading a plurality of power supply management units.

As shown in fig. 1, a power management device 10 provided by the embodiment of the present disclosure may include: at least one power management unit 20, each power management unit 20 including a mode switch 21, a power supply loading circuit 22, a power receiving power separating circuit 23, a power line 24, and a network transmission line 25;

a mode switch 21 for selectively connecting the power supply loading circuit 22 and the power line 24 or connecting the power receiving power separating circuit 23 and the power line 24 according to the operation mode;

the power supply loading circuit 22 is used for loading the direct current transmitted from the power line 24 onto the network transmission line 25;

the power receiving power supply splitting circuit 23 is configured to split the dc power transmitted from the network transmission line 25 to the power supply line 24;

the network transmission line 25 is connected to the edge computing device.

In the embodiment of the present disclosure, the mode switch 21 can select a circuit to be conducted to the power line 24 according to the operation mode. Specifically, when the operation mode is the power supply mode, that is, the terminal device of the power management device is configured as the power supply device, the mode switch 21 selectively connects the power supply loading circuit 22 and the power line 24, and the power supply loading circuit 22 loads the direct current transmitted from the power line 24 onto the network transmission line 25, so as to supply power to the subsequent device by using the network transmission line 25. When the operation mode is the power receiving mode, that is, when the terminal device of the power management device is configured as the power receiving device, the mode switch 21 selectively turns on the power receiving power separating circuit 23 and the power line 24, the power receiving power separating circuit 23 separates the direct current transmitted from the network transmission line 25 to the power line 24, and the terminal device can be electrically connected to the power line 24 to receive power.

Therefore, through the mode switch 21 in the power management unit 20, the coupling and separation of the direct current and the network transmission line can be realized, the power supply and power receiving functions can be stripped from the system side (referring to a system for transmitting network signals, which can be called as a network system), and the system is independently deployed and flexibly configured, so that the PSE or PD functions do not need to be integrated inside the edge computing device, the over-design of the system side is avoided, and the problems of poor configuration flexibility and extra cost of the PSE and the PD are improved.

It can be appreciated that when the direct current is applied to the network transmission line, the network transmission line may be used to transmit only the direct current, or the network transmission line may be used to transmit both the direct current and the network signal; that is, the network signal and the direct current can be transmitted by using the same network transmission line, and can also be transmitted by using different network transmission lines; correspondingly, a signal wire power supply mode can be adopted, and an idle wire power supply mode can also be adopted. Illustratively, corresponding to the signal line power mode, the PSE transmits direct current while transmitting data to the PD using the pairs (1, 2, 3, 6) of the 3/5 twisted pairs for transmitting data; corresponding to the idle mode, the PSE transmits dc power to the PD using the pairs (4, 5, 7, 8) of the 3/5 twisted pairs that are not used for data transmission, which may be set based on network signals and transmission requirements of the dc power, and is not limited herein.

It can be understood that fig. 1 only exemplarily shows that the power management device 10 includes one power management unit 20, but does not constitute a limitation of the power management device 10 provided by the embodiment of the present disclosure. In other embodiments, the number of the power management units 20 may also be two, three or more, which is not limited herein and is exemplified hereinafter. Applying DC power from power line 24 to network transmission line 25

The power management apparatus 10 provided by the embodiment of the present disclosure can selectively turn on the power line 24 and the power supply loading circuit 22 or turn on the power line 24 and the power receiving power splitting circuit 23 according to the operation mode by setting the power management apparatus to include at least one power management unit 20, and the mode switching switch 21 in the power management unit 20; meanwhile, the power supply loading circuit 22 can load the direct current transmitted from the power line 24 onto the network transmission line 25, and the power receiving separation circuit 23 can separate the direct current transmitted from the network transmission line 25 onto the power line 24, can integrate the PSE and the PD, and can be used as a power receiving device or a power supply device, and only needs to switch by using the mode switch 21; meanwhile, the PSE and PD can be designed to be separated from the network system, and the mode selector switch 21 switches the circuit to be connected to the power line 24 in response to the operating mode, so that the power management device 10 can be independently deployed without being limited to the network system, and can be flexibly adapted to the power supply and power receiving requirements of the network system according to the POE function requirements and the deployment environment.

Based on this, for the scenario that the demand of each different edge computing device for POE is different in the edge computing device deployment process, for example, there is a POE deployment scenario that is non-POE deployment, power supply device, powered device, the PSE and PD functions can be configured and implemented by the power management device 10, rather than integrating the PSE and PD functions inside the edge computing device, which avoids over-design of the network system, and further avoids paying extra cost. That is, the POE function can be stripped from the network system and independently implemented by the power management device 10, and the power management device 10 integrates PSE and PD designs, so as to be suitable for various different scenarios.

Therefore, the embodiment of the present disclosure provides an integrated solution for POE power supply and powered devices, integrates power supply and power receiving in the same power management device 10, and can be deployed in combination with serial products of edge computing devices. For example, the power management device 10 is suitable for a scenario in which the terminal device does not have a POE function or is not determined to be used as a power supply device or a powered device, but its associated device depends on POE deployment, and flexible adaptation is performed according to power supply and power receiving requirements.

In an alternative embodiment of the present disclosure, as shown in fig. 2, the power supply loading circuit 22 includes:

a boosting sub-circuit 221 for boosting the direct current of the first voltage transmitted on the power line 24 into a direct current of a second voltage, the value of the second voltage being greater than the value of the first voltage;

a loading sub-circuit 222 for loading the dc power of the second voltage onto the network transmission line 25.

In the embodiment of the present disclosure, the voltage boost sub-circuit 221 can make the output voltage higher than the input voltage. Specifically, the input voltage is a first voltage transmitted on the power line 24, and the output voltage is a second voltage; the first voltage is converted into a second voltage after being boosted by the boosting sub-circuit 221; the value of the second voltage is greater than the value of the first voltage.

Illustratively, the boost sub-circuit 221 is capable of boosting 12V dc to 48V dc; correspondingly, and the loading sub-circuit 222 is used to load 48 vdc onto the network transmission line 25.

It can be understood that the above description is only exemplified by the first voltage being 12V and the second voltage being 48V, that is, the boost sub-circuit 221 may boost the output voltage to 4 times of the input voltage, but does not constitute a limitation on the embodiment of the present disclosure. In other embodiments, the boosting capability of the boosting sub-circuit 221 may be set based on the power supply requirement and the first voltage transmitted on the power line 24, and is not limited herein.

For example, the boost sub-circuit 221 may employ a switching dc boost circuit such as a boost circuit or other dc boost circuits, which are not described or limited herein.

Similarly, the loading sub-circuit 222 may adopt any loading circuit capable of loading the dc power to the network transmission line 25, which is not described or limited herein.

In the embodiment of the present disclosure, by providing that the power supply loading circuit 22 includes the voltage boost sub-circuit 221 and the loading sub-circuit 222, the voltage boost sub-circuit is configured to boost the direct current of the first voltage transmitted on the power line 24 into the direct current of the second voltage, and the loading sub-circuit is configured to load the direct current of the second voltage onto the network transmission line 25, on the basis that the direct current can be loaded onto the network transmission line 25 by the power supply loading circuit 22, the direct current transmitted on the power line 24 can be boosted based on the power supply requirement of the power supply device, that is, based on the power consumption requirement of the power consumption device connected thereto, so that the direct current loaded onto the network transmission line 25 is the direct current with the second voltage, and the second voltage is greater than the first voltage, thereby being beneficial to meeting the power consumption requirement of the power consumption device with a large power consumption.

In an alternative embodiment of the present disclosure, as shown in fig. 3, the power receiving power source separation circuit 23 includes:

a splitting sub-circuit 231 for splitting the direct current of the third voltage from the network transmission line 25;

and a voltage reduction sub-circuit 232, configured to reduce the dc power of the third voltage into dc power of a fourth voltage, where the value of the fourth voltage is smaller than the value of the third voltage.

In the disclosed embodiment, the dc current is a dc current signal with a fixed voltage value, and the data signal is usually an analog signal or a digital signal, which is a regular, programmed, electrical signal with information. On the basis of this, the direct current can be distinguished from the data signal, for which the separation sub-circuit 231 is designed, the direct current of the third voltage can be separated from the network transmission line 25.

In the disclosed embodiment, the buck sub-circuit 232 enables the output voltage to be lower than the input voltage. Specifically, the input voltage is a third voltage, the output voltage is a fourth voltage, the dc power of the third voltage is converted into the fourth voltage after passing through the voltage-reducing sub-circuit 232, and the value of the fourth voltage is smaller than that of the third voltage.

Illustratively, the voltage step-down sub-circuit 232 is capable of stepping down the dc power of the third voltage of the other value, which is split off by the splitting sub-circuit 231 from the power transmission line 25, to 12V dc power and supplying the terminal device, such as the edge computing device, via the power line 24.

It can be understood that the above description is only exemplified by the fourth voltage being 12V, but does not limit the embodiments of the present disclosure. In other embodiments, the voltage reduction capability of the voltage reduction sub-circuit 232 may be set based on the power demand and the third voltage of the dc power split from the network transmission line 24, and is not limited herein.

For example, the voltage-reducing sub-circuit 232 may adopt a switching dc voltage-reducing circuit or other dc voltage-reducing circuits, which are not described or limited herein.

Similarly, the separating sub-circuit 231 may be any separating circuit capable of separating the dc power from the network transmission line 25, which is not described or limited herein.

In the embodiment of the present disclosure, the power receiving power supply separation circuit 23 includes a separation sub-circuit 231 and a voltage reduction sub-circuit 232; the splitting sub-circuit 231 is used to split the direct current of the third voltage from the network transmission line 25; the voltage-reducing sub-circuit 232 is configured to reduce the dc power of the third voltage to a dc power of a fourth voltage, where the value of the fourth voltage is smaller than the value of the third voltage, and on the basis that the received power supply separation circuit 23 can be used to separate the dc power from the network transmission line 25, the dc power obtained by separation can be reduced based on the power consumption requirement of the power receiving device, so that the voltage of the dc power is reduced from the third voltage to the fourth voltage, which is beneficial to meeting the power consumption requirement of a terminal device with smaller power consumption, such as an edge computing device.

In an alternative embodiment of the present disclosure, as shown in fig. 4 or fig. 5, the number of the power management units 20 is at least two, the power lines 24 of at least two power management units 20 are electrically connected to serve as a common power output terminal, and each power management unit 20 further includes:

a load balancing circuit 26 provided in series with the power reception power source separation circuit 23;

and, the load balancing circuit 26 between different power management units 20 is electrically connected to balance the load between at least two power management units 20.

In the embodiment of the present disclosure, the power lines 24 of at least two power management units 20 are electrically connected in a sequential plugging manner, and the connection ends of the power lines 24 are shown in fig. 5. Wherein, the power line 24 may adopt a dc power cable, the connection ends may include a male head 241 and a female head 242, when the connection ends are sequentially plugged, the male head 241 is sequentially inserted into the female head 242, and the male head 241 which is not visible from the outside after plugging is represented by a dotted line in fig. 5; the female connectors 242 implement cascade connection between the power management units 20, and the male connector 241 supplies power to the powered device. The male connector 241 may also be referred to as a DC output terminal, i.e., a DC Jack output; the female header 242 may also be referred to as a DC input terminal, i.e., a DC Jack input, and the male header 241 and the female header 242 constitute a set of DC Jack terminals. Wherein, DC jack represents a direct current jack or a direct current jack.

In the embodiment of the present disclosure, the load balancing circuit 26 is disposed in the power management unit 20, and is disposed in series with the powered power splitting circuit 23, and is configured to access the dc power separated by the powered power splitting circuit 23 from the network transmission line 25; and the load balancing circuit 26 between different power management units 20 is electrically connected to balance the load between the power management units 20, so that the common power output end can output stable direct current meeting the power consumption requirement. For example, in fig. 4, the load balancing circuit 26 needs to balance two paths of direct current in parallel; in fig. 6, the load balancing circuit 26 needs to balance four parallel direct currents, for example, adjust output currents corresponding to different direct currents.

Illustratively, the load balancing circuit 26 may include a power converter, a regulating amplifier and a PWM controller connected in a cyclic order, the non-inverting input terminals of the regulating amplifiers of the load balancing circuit 26 between different power management units 20 are connected and connected to the shared bus; the adjusting amplifier is used for adjusting the current amplification factor, the PWM controller is used for controlling the duty ratio of a voltage signal, the power converter is used for realizing the conversion of voltage, current and corresponding power, and more accurate load balance is realized based on parameters transmitted on the shared bus; wherein direct current is input by the power converter and finally output by the power converter after load balancing.

It is understood that the load balancing circuit 26 may also adopt other circuit structures capable of achieving load balancing, which are not described or limited herein.

In the embodiment of the present disclosure, by setting the number of the power management units 20 to be at least two, the power lines 24 of at least two power management units 20 are electrically connected to serve as a common power output end, and each power management unit 20 further includes: a load balancing circuit 26 provided in series with the power reception power source separation circuit 23; moreover, the load balancing circuits 26 between different power management units 20 are electrically connected to balance the load between at least two power management units 20; while the power supply and receiving functions can be integrated by the power management apparatus 10, two or more power management units 20 can be provided according to different power supply/use requirements, and load balancing between different power management units 20 is implemented by using the load balancing circuit 26 in the power management unit 20, so that a common power output terminal of at least two power management units 20 can output stable direct current that meets the power use requirements.

It can be understood that fig. 4 only exemplarily shows that the number of the power management units 20 is two, and fig. 6 only exemplarily shows that the number of the power management units 20 is four. In other embodiments, the number of power management units 20 may also be three, five, or more; the load balancing circuits between different power management units 20 are electrically connected in sequence to correspondingly achieve balancing between three or more power management units 20.

In an alternative embodiment of the present disclosure, as shown in fig. 5 or fig. 6, each power management unit 20 is enclosed in a casing 200, the casing 200 is provided with a first opening 201 for the network transmission line 25 to pass through, a second opening 202 for the power line 24 to pass through, and a third opening 203 for the cascading probe to pass through, and the cascading probe is used to electrically connect the load balancing circuits 26 between different power management units 20.

In the embodiment of the present disclosure, the housing 200 can enclose the power management unit 20, so as to facilitate the overall structure of the power management device 10 to be more stable. In fig. 5 and 6, the dotted lines inside the case 200 indicate the external non-portable circuits and connection lines built in the case 200.

In the embodiment of the present disclosure, a first opening 201, a second opening 202 and a third opening 203 are provided on the housing 200; first openings 201 are provided at opposite sides of the housing 200 for allowing the network transmission line 25 to be accessed and accessed; the second opening 202 may be disposed on the same side of the housing 200 as one of the first openings 201, and the second opening 202 is used for passing the power cord 24; the third openings 203 are disposed at two adjacent sides of the housing 200, the two adjacent sides can be used for connecting two opposite sides where the first opening 201 is located, and the third openings 203 are used for the cascading probes to pass through, so as to facilitate the connection between different power management units 20.

It is understood that the third openings 203 are only exemplarily shown in fig. 6 to include two rows of four openings, i.e. 8 openings in total. In other embodiments, the number and arrangement of the third openings 203 may also be set based on the requirement of the power management apparatus 10, and is not limited herein.

In the embodiment of the present disclosure, when the mode switch 21 is implemented by a hardware structure, it may be disposed on the other side of the housing 200, and is connected to the power line 24 inside the housing 200, and selectively connected to the power loading circuit 22 or the power separating circuit 23, so as to correspondingly connect the power line 24 and the power loading circuit 22, or connect the power line 24 and the power separating circuit 23. The power supply loading circuit 22 and the power receiving separating circuit 23 are both connected to the network transmission line 25, the power supply loading circuit 22 can load the dc power onto the network transmission line 25, and the power receiving separating circuit 23 can separate the dc power transmitted from the network transmission line 25 onto the power line 24, so that the power management unit 20 can couple or separate the dc power to or from the network transmission line 25.

Illustratively, as shown in fig. 5 or fig. 6, the network transmission line 25 is further connected to a network output 252 for accessing or outputting data signals.

Illustratively, taking the orientation shown in fig. 5 and fig. 6 as an example, the power management device is configured into a network system, when the power management device works as a PSE device, a terminal device of the network system, such as an edge computing device, can be connected to the first opening 201 on the right side of the power management device through a network signal transmission line 25, and 12V dc is connected to the power management device through a connection terminal (including a male connector 241 and a female connector 242) and a power line 24. With reference to fig. 2, the 12V dc is boosted to 48V dc by the boost sub-circuit 221, and the loading sub-circuit 222 is loaded onto the network transmission line 25, and is output to the external PD device by the network signal transmission line 25 electrically connected to the first opening 201 on the right side, where the external PD device may be, for example, a POE camera, a POE door, a POE curtain, a POE charging device, or a POE lighting device. At this time, the power receiving source separating circuit 23, the load balancing circuit 26, and the cascade probe are all in the non-operating state.

When the power management device is used as a PD power separation device, a terminal device of a network system, for example, an edge computing device, may connect to the first opening 201 on the left side of the power management device, and at this time, the first opening 201 on the right side may connect to a POE power network of a switch, that is, connect to a switch with a POE function; the switch POE power network can be connected to the power management device via a network transmission line 25, wherein the network signal transmission line 25 carries dc power. With reference to fig. 3, the dc signal of the dc on the network transmission line can be separated by the separation sub-circuit 231 and converted into 12V dc by the voltage reduction sub-circuit 232, and the 12V dc can be transmitted to the male connector 241 of the connection end via the power line 24 and further connected to the edge computing device, so as to implement power receiving of the edge computing device. At this time, the power supply source loading circuit 22 is in the non-operating state; the cascade probe is also in a non-working state; when the power consumption of the power-receiving edge computing equipment is larger, the cascade probe is in a working state, and cascade of different power management units is realized.

Specifically, when the power management device is cascaded as a PD power separation device, as shown in fig. 6, four power management units are combined into one power management device through a cascaded probe, 4 groups of DC Jack terminals are also connected through a male-female connection terminal, four groups of POE power networks are correspondingly connected to the four first openings 201 on the right side, respectively, power conversion of 48V to 12V is provided through a power receiving power separation circuit and a load balancing circuit, and 12V DC output voltage is output to an edge computing device through the cascaded probe as load balancing.

In the embodiment of the present disclosure, the power supply capability of the 4-way POE power network can be provided by cascading four power management units. Illustratively, the 8023.at standard can support a power supply capacity of up to 102W, which can meet the power supply requirements of higher power edge computing devices or other terminal devices.

In other embodiments, when the power consumption of the edge computing device is higher, a larger number of power management unit cascades may be further adopted in the power management device, which is neither described nor limited herein. Therefore, the power management equipment can be suitable for power supply/power receiving scenes which cannot be met by POE standards, and flexible adaptation under different power utilization scenes can be realized.

In an alternative embodiment of the present disclosure, as shown in fig. 5 or 6, a network transmission line 25 connected to the edge computing device is used to transmit network signals and dc power; or a network transmission line 25 connected to the edge computing device for transmitting network signals.

In the disclosed embodiment, the edge computing device may have power supply/receiving functions integrated therein, and the corresponding network transmission line 25 may transmit both network signals and dc power. Illustratively, at this point, the dc power and network signals are coupled or decoupled internally within the edge computing device; optionally, a separation circuit for separating the dc power and the network signal is arranged inside the edge computing device, and a circuit structure of the separation circuit may be the same as that of the power receiving power separation circuit in the power management device, or another circuit structure known to those skilled in the art is adopted, which is not limited herein; optionally, the edge computing device is internally provided with a loading circuit for coupling the dc power and the network signal, and the circuit structure of the loading circuit may be the same as that of the power supply loading circuit in the power management device, or other circuit structures known to those skilled in the art may be adopted, which is not limited herein.

Alternatively, when the power receiving function is integrated in the edge computing device and the network transmission line 25 only transmits the network signal, the power management device 10 may be used to load the local dc power onto the network signal transmission line 25, and then connect the network transmission line 25 to the edge computing device. In this manner, the power management device 10 can be configured to meet the requirement that the edge computing device simultaneously receives network signals and direct current power through only one signal transmission port.

Alternatively, when the power receiving function is not integrated inside the edge computing device, but the network transmission line 25 transmits the network signal and the direct current at the same time, the power management device 10 may be used to separate the network signal and the power signal, transmit the network signal to the edge computing device through the network transmission line 25 connected to the edge computing device, and supply power to the edge computing device through another power line connected to the edge computing device, in which case, the corresponding edge computing device has two transmission ports for receiving the network signal and the direct current, respectively.

Alternatively, when the power supply function is not integrated in the edge computing device, but the network transmission line 25 transmits the network signal and the dc power simultaneously, the power management device 10 may be used to electrically couple the dc power to the network transmission line 25, and then, the network signal and the dc power may be transmitted synchronously.

In the embodiment of the present disclosure, by separating or coupling the network signal and the direct current by using the power management device, the PSE and the PD can be integrated, and the PSE and the PD can be used as a powered device and a power supply device, and only the mode switch 21 in the power management device 10 is used to switch the working mode; meanwhile, the PSE and PD can be designed to be separated from the network system, and the mode selector switch 21 switches the circuit to be connected to the power line 24 in response to the operating mode, so that the power management device 10 can be independently deployed without being limited to the network system, and can be flexibly adapted to the power supply and power receiving requirements of the network system according to the POE function requirements and the deployment environment.

The embodiment of the disclosure further provides edge computing equipment, which includes a signal transmission interface by setting a substrate, wherein an edge computing function chip on a core board is connected with the signal transmission interface on the substrate through at least one connector, so that the core board connected with the substrate can be replaced, and under an edge computing scene, the edge computing equipment can meet diverse requirements of various service lines on computing power of a CPU (central processing unit), AI computing power, low-delay network interconnection, industrial interfaces and the like, and provide solutions for meeting requirements of computing power elastic upgrade and the like. That is, the edge computing device provided by the embodiment of the present disclosure is transversely compatible with various solutions by setting a peelable connection between the core board and the substrate, so as to meet diversified demands of business on computing power and configuration, and optimize cost; and the demand of calculation capacity improvement can be met longitudinally, and the upgrading iteration of the solution is facilitated.

As shown in fig. 7, the edge computing apparatus provided by the embodiment of the present disclosure includes a core board 40 and a substrate 30, wherein an edge computing function chip 41 is disposed on the core board 40, a signal transmission interface 300 is disposed on the substrate 30, and the edge computing function chip 41 on the core board 40 is connected to the signal transmission interface 300 on the substrate 30 through at least one connector 42; the signal transmission interface 300 includes a network signal interface, which is connected to a network transmission line to realize the connection between the edge computing device and the power management device.

In the embodiment of the present disclosure, the edge calculation function chip 41 can implement an edge calculation function, such as a billing function, an image recognition function, an illumination function, a temperature control function, or other functions in an edge scene, which is not limited herein.

Illustratively, the edge computing function Chip 41 may include at least one of systems on Chip (SoC) such as intel Keembay, Cambricon NPU, Rockchip RK series, highpass, Xilinx, flathead, and X86 CPU. Accordingly, the core board 40 may compatibly support implementing a variety of different edge computation functions.

In the embodiment of the present disclosure, at least one connector 42 is further disposed on the core board 40 provided with the edge computing function chip 41, so as to implement connection with the signal transmission interface 300 of the substrate 30. Thus, rather than modularly designing the core board 40 in the edge computing device, the modular core board 40 enables releasable connection to the substrate 30 through standardized terminals (also referred to as "interfaces") in the connectors 42.

Because the required computation power is different in different edge computation scenarios, the requirements for the edge computation function chip 41 on the core board 40 are greatly different. In this regard, the connector 42 on the core board 40 and the signal transmission interface 300 on the substrate 30 are connected in a pluggable manner, so that the core board 40 meeting the computing requirements can be connected with the substrate 30, and the computing requirements under different edge computing scenes can be met.

In the embodiment of the present disclosure, the substrate 30 is directly connected to an external device, such as at least one of a camera, an audio capture device and other data capture devices, in addition to the core board 40, and may be set based on a scene suitable for the edge computing device, which is not limited herein.

In an alternative embodiment of the present disclosure, the at least one connector 42 may include a main connector 421, as shown in fig. 7, the main connector 421 is fixed to an edge of the core board 40; further, at least one connector 42 may further include an auxiliary connector 422, as shown in fig. 8, the auxiliary connector 422 is fixed to the edge of the core board 40; also, the auxiliary connector 422 and the main connector 421 may be fixed to two different edges of the core board 40.

In other embodiments, the at least one connector 42 may also include only the auxiliary connector 422, and the auxiliary connector 422 is secured to an edge of the core board 40.

In the embodiment of the present disclosure, only the main connector 421 may be provided at the edge of the core board 40, and the number and functions of the terminals thereof may be provided, as will be described later in detail; when the terminals of the main connector 421 are not enough, the auxiliary connector 422 may be further added. For example, a terminal corresponding to a function of primary interest may be provided in the main connector 421, and a terminal corresponding to another extended function or an auxiliary function may be provided in the auxiliary connector 422. Alternatively, the main connector 421 and the auxiliary connector 422 can be used for different subjects, such as for the state of the subject, identification of related module information, health status, connection status, and the like.

In an alternative embodiment of the present disclosure, as shown in fig. 10, the core function of the core board 40 is to support an SOC operation core, and the built-in main functions may include:

1) a display output function, correspondingly, a universal man-machine interface can be provided;

2) network functions, such as providing 2-way network connectivity;

3) a Peripheral Component Interconnect express (PCIe) bus, such as a PCIe 3.03 × 4 channel bus, may support connection of components such as a 5G network, storage, and AI acceleration;

4) universal Serial Bus (USB) functionality, such as providing a Universal human machine interface;

5) other IO functions, correspondingly, provide audio input and output interfaces;

6) the control bus interface supports Controller Area Network (CAN), RS232 and RS485 functions.

In an alternative embodiment of the present disclosure, as shown in fig. 10 and 11, each of the signal transmission interfaces may be provided corresponding to each of the terminals in the connector 42; as shown in fig. 11, the connector 42 includes at least one of a USB signal terminal, a CAN bus signal terminal, a High Definition Multimedia Interface (HDMI) Interface signal terminal, a Camera Serial Interface (CSI) signal terminal, a Joint Test Action Group (JTAG) signal terminal, an ethernet signal terminal, an audio signal terminal, an Artificial Intelligence (AI) module signal terminal, a memory signal terminal (i.e., a memory card signal terminal), a mobile communication signal terminal, a Serial Peripheral Interface (SPI) signal terminal, a Serial communication bus signal terminal, and a power supply terminal.

Correspondingly, the interface of the signal transmission interface may include at least one of a USB signal interface, a CAN bus signal interface, an HDMI interface signal interface, a CSI signal interface, a JTAG signal interface, an ethernet signal interface, an audio signal interface, an AI module signal interface, a memory card signal interface, a mobile communication signal interface, an SPI signal interface, a serial communication bus signal interface, and a power supply interface. Referring to fig. 9 and 11, the connector 42 may be a main connector 421 or an auxiliary connector 422.

In the embodiment of the present disclosure, with reference to fig. 10, the USB signal interface may include a USB3.0 signal interface and a USB2.0 signal interface for transmitting a universal serial signal; the CAN bus signal interface CAN be referred to as a CAN interface for short, and also CAN comprise a CAN interface 2 used for transmitting CAN bus signals; the HDMI signal interface can be abbreviated as an HDMI interface and is used for transmitting HDMI signals; the CSI signal interface is used for transmitting CSI signals, the JTAG signal interface is used for transmitting JTAG signals, the Ethernet signal interface can comprise Gigabit Ethernet (GE) network interface 1 and GE network interface 2 and is used for transmitting Ethernet signals, and the audio signal interface can also be called an audio input/output interface and is used for transmitting audio signals; the AI module signal interface comprises a first slot of an M.2AI module and a second slot of the M.2AI module, the memory signal interface can be a slot of a Micro SD card, the mobile communication signal interface is used for transmitting mobile communication signals, the SPI signal interface is used for transmitting SPI signals, the serial communication bus signal interface can comprise an RS485 interface and an RS232 interface, and the power supply interface can be a direct current interface.

Therefore, the core board 40 and the substrate 30 may be interconnected by using an interconnection interface of a standardized design, and the substrate 30 supports power access, video input/output, audio input/output, network access, USB access, a 4G/5G module (e.g., an m.2 interface), a Global Navigation Satellite System (GNSS) (e.g., a beidou System is designed on the substrate), a network-processor (NPU) accelerator card (e.g., Dual m.2), and the like, and may compatibly support Single m.2 × 2), a Solid State Disk (SSD) or Solid State Drive (SSD) storage memory (e.g., m.2), and other functions related to edge calculation such as a debug interface (i.e., JTAG).

For example, the signal terminals of the main connector 421 and the signals led out therefrom are described in table 1.

TABLE 1 terminal signal meter of main connector

For example, the signal terminals of the auxiliary connector 422 and the signals derived therefrom are illustrated in table 2.

TABLE 2 auxiliary connector terminal signal table

In an alternative embodiment of the present disclosure, the core board may support two sizes, and specifically, only the main connector is provided, i.e., the core board with a single connector has a size of 76mmx50 mm; setting a main connector and an auxiliary connector at the same time, namely, the size of a core plate with a double connector is 76mmx110 mm; the core plate may have a thickness of 1.05mm and a weight of 300 g.

In an alternative embodiment of the present disclosure, the core board supports two high speed connectors for connecting signals to the substrate, which may be Molex Mirror Mezz series 2063060537, with a 5mm high mating height, as shown in Table 3.

TABLE 3 high speed connector Specifications

Item	Description of the invention
		Model number	2063060537
Number of pins	169
		Rate of speed	56GNRZ/112GPAM4
Single pinCurrent capacity	1A
		Weight (D)	TBD g

In an alternative embodiment of the present disclosure, as shown in fig. 12, each pin (i.e., terminal) in the connector 42 is shown at 420, the connector 42 includes a total of 169 defined terminals 420 and is arranged in 5 rows, the number of terminals 420 in the middle row is 37, and the number of terminals 420 in each row is 33 (i.e., 37-4) in the remaining 4 rows, such that there are 169 terminals, i.e., 37 × 5-4 × 4 ═ 169.

Based on this arrangement, the pin definition of the main connector is exemplarily shown in table 4.

TABLE 4 Pin definition of the Main connector

The definition of the pin shown in table 4 can cover the edge service interface requirement, and can realize the automatic identification and in-place detection functions; in particular, the pin design may employ a combination of primary and secondary connector modes, with the primary connector pins meeting the capability of stand-alone use.

According to the sequence of "meaning of signal name | | signal, function description | | | signal flow direction (I/O/IO) | channel voltage (with Pwr Rail) | ECM pull-down and whether processing condition | | load (Carrier) needs other processing | | | remark", the definition of each pin in table 4 is described as follows:

the P3V3 power supply 3.3V I3.3V NA does not;

the P5V power supply 5V of the ECM board is I5V NA No;

P3V3_ STBY ECM board 3.3Vstandby supplies power I3.3V NA none;

the GND | high-speed signal is grounded | I |/| NA | not;

USB2_ #0_ DN | Micro USB2 port 0, data negative pole | | I/O | |3.3V | | NA | | | is allocated to the external MicroUSB OTG port;

the USB2_ #0_ DP | Micro USB2 port 0, the data positive pole | | I/O | |3.3V | | | NA | | is distributed to the external MicroUSB OTG port;

the USB2_ #2_ DN | USB2 port 2 is reserved with a data negative pole I/O |3.3V | NA | and if the support plate is directly connected with an external USB port, a protective device needs to be added according to the port requirement;

the USB2_ #2_ DP | | USB2 port 2, the data positive pole | | I/O | |3.3V | | | NA | | reserve, if the support plate is directly connected to the external USB port, need to increase the protective device according to the port requirement;

the USB2_ #3_ DN | USB2 port 3 is reserved with the data negative pole | I/O |3.3V | NA | and if the support plate is directly connected with an external USB port, a protective device needs to be added according to the port requirement;

the USB2_ #3_ DP | | USB2 port 3, the data positive pole | | I/O | | |3.3V | | | NA | | | reserve, if the support plate is directly connected to the external USB port, need to increase the protective device according to the port requirement;

the USB3_ #3_ RX _ DN | USB3 port 3 is characterized in that a SuperSpeed receiving negative pole I | AC coupled | NA | AC coupling capacitor | is reserved, and if the carrier plate is directly connected with an external USB port, a protection device needs to be added according to the port requirement;

a CAN0_ H | CAN0 controller sends a sending end | O |3.3V | NA | to a carrier plate CAN transceiver, the controller and the transceiver suggest a reserved end to match, and the rear end CANH of the transceiver and CANL match at 120 ohms;

the CAN0_ L | CAN0 controller receives end | I |3.3V | NA | to the carrier plate CAN transceiver, the controller and the transceiver suggest a reserved terminal for matching, and the rear end CANH of the transceiver is 120 omega matched with CANL;

the ECM _ WATCHDOG | | | WATCHDOG feeding signal | | | O | | |3.3V | | | NA | | | is reserved;

USB2_ #0_ VBUS | Micro-USB VBUS voltage detecting | | | I | |5V | | | NA | | | none;

the cathode of the HDMI _ CLK _ DN I HDMI CLK signal differential signal is I O I1.8V I L I NA I L;

the HDMI _ CLK _ DP | positive pole of the HDMI CLK signal differential signal is | O |1.8V | reserved end is matched with | NA | but not;

the HDMI _ DATA1_ DP | HDMI signal differential signal 1 is provided with a negative pole | O |1.8V | which is connected with a reserved end matching | NA | but not;

the HDMI _ DATA1_ DN | I is a positive pole of the HDMI signal differential signal 1, O | I1.8V | I is reserved and connected with matching | NA | I;

the HDMI _ DATA2_ DP | HDMI signal differential signal 2 has a negative pole | O |1.8V | which is reserved to be terminated and matched with | NA | |;

the HDMI _ DATA2_ DN | I HDMI signal differential signal 2 positive pole | O |1.8V | I is reserved to be connected and matched with | NA | I;

the HDMI _ DATA0_ DN | I HDMI signal differential signal 0 positive pole | O |1.8V | I is reserved to be terminated and matched with | NA | I;

MDI0+ _1| | | MDI1 differential pair 0 negative pole, can consult 10/100/1000M | | I/O | |3.3V | | | NA | | | connect isolation transformer | | | give support plate kilomega net mouth 1;

MDI0- _1| | MDI1 differential pair 0 anode, can consult 10/100/1000M | | I/O | |3.3V | | | NA | | | and connect isolation transformer | | | to support plate kilomega net port 1;

MDI1+ _1| | | MDI1 differential pair 1 cathode, can consult 10/100/1000M | | I/O | |3.3V | | | NA | | | and connect isolation transformer | | | to support plate kilomega network port 1;

MDI1- _1| | | MDI1 differential pair 1 positive pole, can consult 10/100/1000M | | I/O | |3.3V | | | NA | | | connect isolation transformer | | | give support plate kilomega net mouth 1;

MDI2+ _1| | | MDI1 differential pair 2 cathode, can consult 10/100/1000M | | I/O | |3.3V | | | NA | | | connect isolation transformer | | | give support plate kilomega net port 1;

MDI2- _1| | MDI1 differential pair 2 anode, can consult 10/100/1000M | | I/O | |3.3V | | | NA | | | and connect isolation transformer | | | to support plate kilomega net port 1;

MDI3+ _1| | | MDI1 differential pair 3 negative pole, can consult 10/100/1000M | | I/O | |3.3V | | | NA | | | connect isolation transformer | | | give support plate kilomega net mouth 1;

MDI 3-1I MDI1 differential pair 3 anode, can negotiate 10/100/1000M I/O3.3V NA I and connect isolation transformer to carrier plate gigabit net port 1;

the USB3_ #2_ RX _ DN | USB3 port 2 is characterized in that a SuperSpeed receiving negative pole | I | AC coupled | NA | AC coupling capacitor | is reserved, and if the carrier plate is directly connected with an external USB port, a protection device needs to be added according to the port requirement;

the GND | high-speed signal is grounded | I |/| NA | not;

the M.2_5G _ CLK _100M _ DN | PCIe device gives the M.25G slot with reference to a 100M clock differential negative pole | O | PCIE | NA | I | which is a clock;

the M.2_5G _ CLK _100M _ DP | PCIe device gives the M.25G slot with reference to a 100M clock differential positive pole | O | PCIE | | NA | | NA | | this clock;

the HDMI _ DDC _ SDA | | HDMI IIC data | | | O | | |1.8V | | | reserved end is matched with | | NA | | nothing;

HDMI _ DDC _ SCL | HDMI IIC clock | O |1.8V | is reserved and terminated with matching | NA | |;

HDMI _ CBL _ HPD | | HDMI hot plug detection | | | I | | |1.8V | | | reserved termination matches | | NA | | | nothing;

the MCU _ UART _ TX | MCU UART serial port transmits | O |3.3V | NA | nothing;

the MCU _ UART _ RX | MCU UART serial port receives | I |3.3V | NA | does not exist;

the PERST _ M.2_5G _ PCIE _ N | PCIe slave device reset signal | | | O | |3.3V | | | NA | | low level is effective, and the carrier plate is pulled upward to be distributed to a 5G module slot position of the carrier plate acceleration card;

the PERST _2M.2_ PCIE0_ N | PCIe slave device reset signal | | | O | |3.3V | | | NA | | low level is effective, and the carrier plate is pulled upward to be distributed to the 2M.2MAIN slot position of the carrier plate accelerator card;

the ECM _ RESETTBTN _ N | | | system reset button signal | | | I | |3.3V | | | NA | | |4.7K is pulled up to 3V3stby | | | nothing;

the ECM _ POWERBTIN _ N | system switch button signal | I |3.3V | NA |4.7K is pulled up to 3V3stby |;

distributing an M.2_5G _ RESET # | | PCIe slave device RESET signal O3.3V NA to a 5G module slot position of the carrier plate accelerator card;

the ECM _ ALERT _ N | whole board healthy green light is controlled to be | O |3.3V | NA | MOS controlled, and the high level is lighted up | | is not;

the ECM _ HEALTH _ N | whole board fault red light control | O |3.3V | NA | MOS control, and high level lighting | is absent;

the PERST _ M.2_ SSD _ PCIE _ N | PCIe slave device reset signal O |3.3V | NA | is effective at a low level, and the carrier plate is pulled upward to be allocated to the carrier plate acceleration card M.2SSD slot;

w _ DISABLE1# |5G module flight mode control | | O | |3.3V/1.8V | | | ECM pull-up | | | NA | |5G module flight mode control;

w _ DISABLE2# |5G module flight mode control | | O | |3.3V/1.8V | | | ECM pull-up | | | NA | |5G module flight mode control;

the TPM _ SPI0_ MIS0| | SPI0 mainly receives and sends | | I | |3.3V | | | NA | | | to reserve for TPM function, and ends are matched according to actual link simulation reservation;

an emergency event | | | I | |3.3V | | | NA | | | of the TPM _ IRQ # | TCPM is pulled up | | | support plate to be reserved for the TPM function;

TPM _ SPI0_ CLK | SPI0 clock | O |3.3V | NA | | is reserved for TPM function, and termination matching is reserved according to actual link simulation;

TPM _ SPI0_ MOSI | SPI0 is mainly used for transmitting and receiving |0| 3.3V | NA | to be reserved for TPM functions, and termination matching is reserved according to actual link simulation;

2M.2_ PCIE _ RXN3 PCIe lane3 receives a differential signal cathode I AC coupled NA AC coupled capacitor to be distributed to a 2M.2MAIN slot of the carrier plate acceleration card;

2M.2_ PCIE _ RXP3 PCIe lane3 receives a differential signal positive pole I AC coupled NA AC coupled to be distributed to a 2M.2MAIN slot of the carrier board acceleration card;

2M.2_ PCIE _ RXN2 PCIe lane2 receives a differential signal cathode I AC coupled NA AC coupled capacitor to be distributed to a 2M.2MAIN slot of the carrier plate acceleration card;

2M.2_ PCIE _ RXP2 PCIe lane2 receives a differential signal positive pole I AC coupled NA AC coupled to be distributed to a 2M.2MAIN slot of the carrier board acceleration card;

2M.2_ PCIE _ RXN1 PCIe lane1 receives a differential signal cathode I AC coupled NA AC coupled capacitor to be distributed to a 2M.2MAIN slot of the carrier plate acceleration card;

2M.2_ PCIE _ RXP1 PCIe lane1 receives a differential signal positive pole I AC coupled NA AC coupled to be distributed to a 2M.2MAIN slot of the carrier board acceleration card;

2M.2_ PCIE _ RXN0 PCIe lane0 receives a differential signal cathode I AC coupled NA AC coupled capacitor to be distributed to a 2M.2MAIN slot of the carrier plate acceleration card;

2M.2_ PCIE _ RXP0 PCIe lane0 receives a differential signal positive pole I AC coupled NA AC coupled to be distributed to a 2M.2MAIN slot of the carrier board acceleration card;

2m.2_ CLK0_100M _ DN | PCIe device references 100M clock differential negative pole | O | | PCIe | | NA | | | NA | | this clock to the 2m.2main slot;

2M.2_ PCIE _ TXN3 PCIe lane3 sends a differential signal negative pole O AC coupled capacitance NA to be distributed to a 2M.2MAIN slot of the carrier plate acceleration card;

2M.2_ PCIE _ TXP3 PCIe lane3 sends a differential signal positive pole O AC coupled capacitance NA to be distributed to a 2M.2MAIN slot of the carrier plate accelerator card;

2M.2_ PCIE _ TXN2 PCIe lane2 sends a differential signal negative pole O AC coupled capacitance NA to be distributed to a 2M.2MAIN slot of the carrier plate acceleration card;

2M.2_ PCIE _ TXP2 PCIe lane2 sends a differential signal positive pole O AC coupled capacitance NA to be distributed to a 2M.2MAIN slot of the carrier plate accelerator card;

2M.2_ PCIE _ TXN1 PCIe lane1 sends a differential signal negative pole O AC coupled capacitance NA to be distributed to a 2M.2MAIN slot of the carrier plate acceleration card;

2M.2_ PCIE _ TXP1 PCIe lane1 sends a differential signal positive pole O AC coupled capacitance NA to be distributed to a 2M.2MAIN slot of the carrier plate accelerator card;

2M.2_ PCIE _ TXN0 PCIe lane0 sends a differential signal negative pole O AC coupled capacitance NA to be distributed to a 2M.2MAIN slot of the carrier plate acceleration card;

2M.2_ PCIE _ TXP0 PCIe lane0 sends a differential signal positive pole O AC coupled capacitance NA to be distributed to a 2M.2MAIN slot of the carrier plate accelerator card;

the M.2_5G _ PCIE _ RXP0 PCIe lane0 receives a differential signal positive pole I AC coupled NA AC coupled capacitor I distributed to a 5G module slot of the carrier board accelerator card;

the ECM _ PG | | ECM board power state is used for lighting a bottom board power lamp and controlling the power to be in time sequence with power, wherein the power is not provided with | | | O | |3.3V | | NA | | |;

the M.2_ SSD _ PCIE _ RXP3 PCIe lane3 receives a differential signal positive pole I AC coupled NA AC coupled to the slot of the carrier board accelerator card M.2SSD;

the M.2_ SSD _ PCIE _ RXP2 PCIe lane2 receives a differential signal positive pole I AC coupled NA AC coupled to the slot of the carrier board accelerator card M.2SSD;

the M.2_ SSD _ PCIE _ RXP1 PCIe lane1 receives a differential signal positive pole I AC coupled NA AC coupled to the slot of the carrier board accelerator card M.2SSD;

the M.2_ SSD _ PCIE _ RXP0 PCIe lane0 receives a differential signal positive pole I AC coupled NA AC coupled to the slot of the carrier board accelerator card M.2SSD;

the m.2_ SSD _ CLK _100M _ DN | | | PCIe device clocks the m.2ssd slot with reference to the 100M clock differential negative O PCIe NA | | |;

the m.2_ SSD _ CLK _100M _ DP | | | PCIe device clocks the m.2ssd slot with reference to the 100M clock differential positive O PCIe NA | | |;

m.2_5G _ PCIE _ TXN0 PCIe lane0 sends a differential signal negative pole O AC coupled NA AC coupled capacitor to be distributed to a 5G module slot of the carrier board accelerator card;

m.2_5G _ PCIE _ TXP0 PCIe lane0 sends a differential signal positive pole O AC coupled NA AC coupled capacitance to be distributed to a 5G module slot of the carrier board accelerator card;

the WAKE _ ON _ WAN # |5G module WAKEs up a host signal | | | I | |3.3V/1.8V | | | ECM to pull up an | | | NA | | |5G module for a WAKE-up signal of the host, and a 5G module port OC;

the VCCRTC _3P3| real-time clock comprises an ECM board RTC power supply | | | I | |3.3V | | | NA | | | RTC battery interface, when an RTC chip is arranged on the ECM board, the interface provides a battery power supply for the RTC, a diode needs to be connected to the ECM to prevent current from flowing back into a battery, and when the RTC chip is arranged on a bottom plate, the I2C1 interface is directly used.

In the description herein, the double vertical line "|" is used to separate two adjacent descriptions without other meanings.

Thus, in an alternative embodiment of the present disclosure, in conjunction with fig. 12, the main connector includes 5 columns of signal terminals in the order of a first column (i.e., column a) signal terminals, a second column (i.e., column B) signal terminals, a third column (i.e., column C) signal terminals, a fourth column (i.e., column D) signal terminals, and a fifth column (i.e., column E) signal terminals; the first column of signal terminals comprise a power supply terminal, a first USB signal terminal and a first CAN bus signal terminal; the second column of signal terminals comprises a first HDMI signal terminal, a first Ethernet signal terminal and a second USB signal terminal; the third column signal terminal comprises a first mobile communication signal terminal, a second HDMI interface signal terminal, a first memory signal terminal and a first SPI signal terminal; the fourth column of signal terminals includes a first AI module signal terminal and a second mobile communication signal terminal; the fifth column of signal terminals includes a second memory signal terminal and a third mobile communication signal terminal.

By the arrangement, signal interference among different types of signal terminals can be avoided, and the stability of signal transmission is improved; meanwhile, the arrangement regularity of the signal terminals is strong, and the signal terminals in adjacent rows are staggered, so that the arrangement space of the main connector is saved, the processing is facilitated, and the stability of the overall structure is improved.

In a similar arrangement, in an alternative embodiment of the present disclosure, in combination with fig. 12, the 5 columns of signal terminals of the auxiliary connector are the sixth column (i.e., column a), the seventh column (i.e., column B), the eighth column (i.e., column C), the ninth column (i.e., column D) and the tenth column (i.e., column E) signal terminals, respectively; wherein the sixth column of signal terminals includes a CSI signal terminal and a third USB signal terminal; the seventh column of signal terminals comprises a JTAG signal terminal, a fourth USB signal terminal and a second Ethernet signal terminal; the eighth column of signal terminals comprises a fourth mobile communication signal terminal, a third HDMI interface signal terminal and a second SPI signal terminal; the ninth column of signal terminals comprises audio signal terminals, serial communication bus signal terminals and memory card signal terminals; the tenth column of signal terminals includes a second AI module signal terminal and a second CAN bus signal terminal.

That is, in an alternative embodiment of the present disclosure, the pin definition of the auxiliary connector may also be implemented based on the pin arrangement shown in fig. 12.

Exemplary, the pin definitions of the auxiliary connector are shown in table 5.

TABLE 5 Pin definition of auxiliary connector

According to the sequence of "meaning of signal name | | signal, function description | | | signal flow direction (I/O/IO) | channel voltage (represented by Pwr Rail) | ECM pull-down and whether processing condition | | load (Carrier) needs other processing | | | remark", the definition of each pin in table 5 is described as follows:

the GND | high-speed signal is grounded | I |/| NA | not;

the CSI _ LANE3+ I camera inputs the difference pair 3 positive pole I1.8V NA to the FPC connector of the carrier plate for connecting the camera;

the CSI _ LANE 3-I camera inputs the difference pair 3 negative electrode I1.8V NA for the FPC connector of the carrier plate for connecting the camera;

the CSI _ LANE2+ I camera inputs the differential pair 2 with positive pole I1.8V NA to the FPC connector of the carrier plate for connecting the camera;

the CSI _ LANE 2-I camera inputs the difference pair 2 with the negative electrode I1.8V NA for the FPC connector of the carrier plate for connecting the camera;

the CSI _ LANE1+ I camera inputs the 1 positive pole I1.8V NA to the carrier plate to be used for connecting with the FPC connector of the camera;

the CSI _ LANE 1-I camera inputs the 1 negative pole I1.8V NA to the differential pair to be used for connecting the FPC connector of the camera by the carrier plate;

the CSI _ LANE0+ I camera inputs the differential pair 0 positive electrode I1.8V NA for the FPC connector of the carrier plate for connecting the camera;

the CSI _ LANE 0-I camera inputs the difference pair 0 cathode I1.8V NA to the FPC connector of the carrier plate for connecting the camera;

the CSI _ CLK plus the positive pole of the differential clock pair of the camera is used for providing the FPC connector for the carrier plate to connect the camera, wherein the positive pole of the differential clock pair of the camera is O1.8V NA;

the CSI _ CLK-I camera differential clock pair has a negative electrode of O I1.8V NA I to the FPC connector of the carrier plate for connecting the camera;

the CSI _ RST | camera is reset | O |1.8V | NA | to provide the FPC connector for the carrier plate to connect with the camera;

the CSI _ MCLK | | system clock outputs | | | O | | |1.8V | | NA | | | | NA | | | to the FPC connector used for connecting the camera of the carrier plate;

the CSI _ I2C _ SCL I CSI I2C clock outputs O I3.3V I Carrier to pull up and reserve the Carrier to pull up I to the FPC connector used for connecting the camera;

the USB3_ #5_ TX _ DN | USB3 port 5 is characterized in that SuperSpeed sends a negative pole | O | AC coupled | AC coupling capacitance | NA | reserved and is allocated to a slot of a 5G module of the carrier board accelerator card, and a protective device is required to be added according to the port requirement;

UART _ FT231_ TXD Micro-USB to UART TX interface O3.3V NA does not exist;

UART _ FT231_ RXD | | Micro-USB to UART RX interface | | | I | |3.3V | | | NA | | NA | | | none;

JTAG _ TDI | JTAG data is input into a | | I | |3.3V | | NA | | support plate to be pulled up | | | for the support plate to convert the USB for debug;

JTAG _ TDO | JTAG data output | | O | |3.3V | | NA | | support plate pull-up | | | for support plate conversion USB, used for debug;

the JTAG _ TCK | JTAG clock outputs | O |3.3V | NA | the support plate is pulled down | to the support plate conversion USB for debug;

in the JTAG _ TMS | JTAG mode, selecting | O |3.3V | NA | support plate to pull up | to convert the USB for debug;

the JTAG _ TRST | JTAG resetting input | | I | |3.3V | | NA | | support plate is pulled up | | | to the support plate conversion USB for debug;

the JTAG _ SRST _ N | JTAG system resets and inputs | | | I | |3.3V | | NA | | | the support plate to pull up | | | for the USB of the conversion of the support plate, used for debug;

the USB3_ #4_ RX _ DN | USB3 port 4 is characterized in that a SuperSpeed receiving negative pole I | AC coupled | NA | AC coupling capacitor | is reserved, and if the carrier plate is directly connected with an external USB port, a protection device needs to be added according to the requirement of the port;

the USB2_ #4_ DN | USB2 port 4 is reserved with a data negative pole I/O |3.3V | NA | and if the support plate is directly connected with an external USB port, a protection device needs to be added according to the port requirement;

the USB2_ #4_ DP | | USB2 port 4, the data positive pole | | I/O | |3.3V | | | NA | | reserve, if the support plate is directly connected to the external USB port, need to increase the protective device according to the port requirement;

MDI0+ _2| | | MDI2 differential pair 0 negative pole, can consult 10/100/1000M | | I/O | |3.3V | | | NA | | | connect isolation transformer | | | give support plate kilomega network port 2;

MDI 0-2I MDI2 differential pair 0 anode, can negotiate 10/100/1000M I/O3.3V NA I and connect isolation transformer to carrier plate gigabit net port 2;

the negative electrode of the MDI1+ _2| | MDI2 differential pair 1 can negotiate 10/100/1000M | | I/O | |3.3V | | NA | | to connect the isolation transformer | | | to the carrier plate gigabit net port 2;

MDI 1-2I MDI2 differential pair 1 anode, can negotiate 10/100/1000M I/O3.3V NA I and connect isolation transformer to carrier plate gigabit net port 2;

MDI2+ _2| | | MDI2 differential pair 2 cathode, can consult 10/100/1000M | | I/O | |3.3V | | | NA | | | connect isolation transformer | | | give support plate kilomega network port 2;

MDI 2-2I MDI2 differential pair 2 anode, can negotiate 10/100/1000M I/O3.3V NA I and connect isolation transformer to carrier plate gigabit net port 2;

MDI3+ _2| | | MDI2 differential pair 3 negative pole, can consult 10/100/1000M | | I/O | |3.3V | | | NA | | | connect isolation transformer | | | give support plate kilomega network port 2;

MDI 3-2I MDI2 differential pair 3 anode, can negotiate 10/100/1000M I/O I3.3V NA I and connect isolation transformer to carrier plate kilomega network port 2;

the USB2_ #5_ DN | USB2 port 5 is reserved with a data negative pole I/O |3.3V | NA | and is allocated to a slot position of a 5G module of the carrier plate accelerator card, and a protective device is required to be added according to the port requirement;

the USB2_ #5_ DP | | USB2 port 5, the positive pole | | I/O | |3.3V | | | NA | | of data is reserved, is allocated to the acceleration card 5G module slot position of the support plate, need to increase the protective device according to the port requirement;

FT232_ RESET # | RS232 RESET signal | | O | | |3.3V | | NA | | | none;

LAN _ SW1_100M _ LED _ N | | net gape 1, light signal | | O | |3.3V | | NA | | | gives the carrier plate giga net gape light signal;

LAN _ SW1_ ACTIVE _ LED _ N | | net gape 1, light signal | | O | |3.3V | | NA | | | gives the carrier plate giga net gape light signal;

the FAN _ ALERT # | FAN controls an ALERT signal | | | I | |3.3V | | | NA | | | reserved;

FAN _ THERM # | FAN controls THERM signal | | I | |3.3V | | NA | | NA | | | reserve;

LAN _ SW1_1000M _ LED _ N | | net gape 1, light signal | | O | |3.3V | | NA | | | gives the carrier plate giga net gape light signal;

LAN _ SW2_100M _ LED _ N | | net gape 2, light signal | | O | |3.3V | | NA | | | gives the carrier plate giga net gape light signal;

LAN _ SW2_ ACTIVE _ LED _ N | | net gape 2, light signal | | O | |3.3V | | NA | | | NA | | gives the carrier plate giga net gape light signal;

LAN _ SW2_1000M _ LED _ N | | net gape 2, light signal | | O | |3.3V | | NA | | | gives the carrier plate giga net gape light signal;

a GPS _ ANTOFF | | GPS antenna control number | | | O | | |3.3V | | NA | | | is reserved;

a GPS _ RESETn | GPS reset signal | O |3.3V | NA | is reserved;

a GPS _ WAKEUP | | | GPS wake-up signal | | | I | | |3.3V | | | NA | | | | is reserved;

GPS _ PPS | | GPS Time Plus signal | | I | | |3.3V | | NA | | | is reserved;

GPS _ UART _ TX | GPS UART TX interface | O |3.3V | NA | is none;

GPS _ UART _ RX | GPS UART RX interface | | I | | |3.3V | | NA | | | none;

w _ DPR | | M.25G Module DPR signal | | O | | |3.3V | | | NA | | is reserved;

HDMI _ CEC | HDMI CEC controls | I |1.8V | reserved end matching | | | NA | | nothing;

adding a protective device according to the port requirement by the Audio _ HPH _ L | left channel O | Analog | NA | of the earphone;

adding a protection device according to the port requirement by the Audio _ HPH _ R | right channel O | Analog | NA | of the earphone;

inserting and detecting the I1.8V NA by the Audio _ HPH _ DET earphone, and adding a protective device according to the port requirement;

the MIC _ BIAS | microphone is additionally provided with a protective device according to the port requirement by referring to | I | Analog | NA | I;

the MIC _ IN _ P | microphone inputs 1.8V | NA | according to the requirements of ports, and a protection device is added;

the MIC _ IN _ M | microphone inputs 1.8V | NA | according to the requirements of ports, and a protection device is added;

inserting and detecting an Audio _ MIC _ DET | microphone, and adding a protective device according to the port requirement, wherein the Audio _ MIC _ DET | microphone is inserted and detected, and the I |1.8V | NA | I;

QTM1_ THERM | | mmWAVE antenna temperature detection resistance | | | | I |/| NA | | | | does not exist;

QTM2_ THERM | | mmWAVE antenna temperature detection resistance | | | | I |/| NA | | | | does not exist;

QTM3_ THERM | | mmWAVE antenna temperature detection resistance | | | | I |/| NA | | | | does not exist;

RS485_ UART _ RX | | RS485 UART TX interface | | O | |3.3V | | | NA | | none;

RS485_ UART _ TX | | RS485 UART RX interface | | | I | |3.3V | | | NA | | none;

RS485_ RTSA _ N | | | RS232 UART RTS interface | | | O | |3.3V | | | NA | | | nothing;

RS232_ UART _ TX | | RS232 UART TX interface | | O | |3.3V | | NA | | | none;

RS232_ UART _ RX | | RS232 UART RX interface | | I | |3.3V | | | NA | | | none;

the SDCARD _ ESD _ D0| | SDIO data 0| | | I/O | |3.3V/1.8V | | | NA | | carrier plate is pulled upwards to reserve | | to the MicroSD interface of the carrier plate;

the SDCARD _ ESD _ D1| | SDIO data 1| | | I/O | |3.3V/1.8V | | | NA | | carrier plate is pulled upwards to reserve | | to the MicroSD interface of the carrier plate;

the SDCARD _ ESD _ D2| | SDIO data 2| | | I/O | |3.3V/1.8V | | | NA | | carrier plate is pulled upwards to reserve | | to the MicroSD interface of the carrier plate;

the SDCARD _ ESD _ D3| | SDIO data 3| | | I/O | |3.3V/1.8V | | | NA | | carrier plate is pulled upwards to reserve | | to the MicroSD interface of the carrier plate;

the SDCARD _ ESD _ CLK | | SDIO clock | | | O | | |3.3V/1.8V | | | NA | | | support plate is pulled upward | | | to the MicroSD interface of the support plate;

the SDCARD _ ESD _ CMD | SDIO command | O |3.3V/1.8V | NA | is pulled up to the MicroSD interface of the carrier plate;

the SDCARD _ ESD _ CD _ N | SD card is pulled up to a MicroSD interface of the carrier plate by an I |3.3V/1.8V | NA | I | carrier plate when the position of the SDCARD _ ESD _ CD _ N | SD card is detected;

the SDCAD _ V2P9| | SD power supply | | | O | | |3.3V/1.8V | | | NA | | | gives the MicroSD interface of the carrier plate;

m.2_ SSD _ I2C _ ALERT # | PCIe, SMBUS ALERT signal | | I | |1.8V | | NA | | | NA | | is distributed to the slot position of the carrier board accelerator card M.2SSD;

2M.2_ I2C _ Main _ ALERT # | PCIe, SMBUS ALERT signal | | I | | |1.8V | | NA | | | is distributed to the slot position of the carrier plate acceleration card 2 M.2MAIN;

2M.2_ I2C _2nd _ ALERT # | PCIe, SMBUS ALERT signal | | I | | |1.8V | | NA | | | is distributed to the 2M.2second slot of the carrier plate accelerator card;

audio _ HPH _ REF _ L | Audio Codec signal reference ground-left channel | | | I |/| NA | | electrically conductive path

The Audio Codec signal reference is grounded;

audio _ HPH _ REF _ R | Audio Codec signal reference ground-left channel | | | I |/| NA | | electrically conductive path

The Audio Codec signal reference is grounded;

2M.2_ PCIE _ RXN7 PCIe lane7 receives a differential signal cathode I AC coupled NA AC coupled capacitance to be distributed to a 2M.2Second slot of the carrier plate acceleration card;

2M.2_ PCIE _ RXP7 PCIe lane7 receives a differential signal positive pole I AC couppled NA AC coupling capacitance to be distributed to a 2M.2Second slot of the carrier plate acceleration card;

2M.2_ PCIE _ RXN6 PCIe lane6 receives a differential signal cathode I AC coupled NA AC coupled capacitance to be distributed to a 2M.2Second slot of the carrier plate acceleration card;

2M.2_ PCIE _ RXP6 PCIe lane6 receives a differential signal positive pole I AC couppled NA AC coupling capacitance to be distributed to a 2M.2Second slot of the carrier plate acceleration card;

2M.2_ PCIE _ RXN5 PCIe lane5 receives a differential signal cathode I AC coupled NA AC coupled capacitance to be distributed to a 2M.2Second slot of the carrier plate acceleration card;

2M.2_ PCIE _ RXP5 PCIe lane5 receives a differential signal positive pole I AC couppled NA AC coupling capacitance to be distributed to a 2M.2Second slot of the carrier plate acceleration card;

2M.2_ PCIE _ RXN4 PCIe lane4 receives a differential signal cathode I AC coupled NA AC coupled capacitance to be distributed to a 2M.2Second slot of the carrier plate acceleration card;

2M.2_ PCIE _ RXP4 PCIe lane4 receives a differential signal positive pole I AC couppled NA AC coupling capacitance to be distributed to a 2M.2Second slot of the carrier plate acceleration card;

2m.2_ CLK1_100M _ DN | PCIe device references 100M clock differential negative pole | O | | PCIe | | NA | | | NA | | this clock gives 2m.2second slot;

2M.2_ PCIE _ TXN7 PCIe lane7 sends a differential signal negative pole O AC coupled capacitance NA to be distributed to a 2M.2Second slot of the carrier plate acceleration card;

2M.2_ PCIE _ TXP7 PCIe lane7 sends a differential signal positive pole O AC coupled capacitance NA to be distributed to a 2M.2Second slot of the carrier plate accelerator card;

2M.2_ PCIE _ TXN6 PCIe lane6 sends a differential signal negative pole O AC coupled capacitance NA to be distributed to a 2M.2Second slot of the carrier plate acceleration card;

2M.2_ PCIE _ TXP6 PCIe lane6 sends a differential signal positive pole O AC coupled capacitance NA to be distributed to a 2M.2Second slot of the carrier plate accelerator card;

2M.2_ PCIE _ TXN5 PCIe lane5 sends a differential signal negative pole O AC coupled capacitance NA to be distributed to a 2M.2Second slot of the carrier plate acceleration card;

2M.2_ PCIE _ TXP5 PCIe lane5 sends a differential signal positive pole O AC coupled capacitance NA to be distributed to a 2M.2Second slot of the carrier plate accelerator card;

2M.2_ PCIE _ TXN4 PCIe lane4 sends a differential signal negative pole O AC coupled capacitance NA to be distributed to a 2M.2Second slot of the carrier plate acceleration card;

2M.2_ PCIE _ TXP4 PCIe lane4 sends a differential signal positive pole O AC coupled capacitance NA to be distributed to a 2M.2Second slot of the carrier plate accelerator card;

a CAN1_ H | CAN1 controller sends a sending end | O |3.3V | NA | to a carrier plate CAN transceiver, the controller and the transceiver suggest a reserved end to match, and the rear end CANH of the transceiver and CANL match at 120 ohms;

the CAN1_ L | CAN1 controller receives end | I |3.3V | NA | to the carrier plate CAN transceiver, the controller and the transceiver suggest a reserved terminal for matching, and the rear end CANH of the transceiver is 120 omega matched with CANL;

the CLKRREQ _2M.2_ PCIE1_ N | PCIe device requires a signal of | I |3.3V | ECM to pull up | I | carrier plate to be distributed to a carrier plate acceleration card 2M.2SECOND slot by referring to a 100M clock;

In the description of the pin definitions in table 4 and table 5, the ECM, i.e., the core board, and the carrier board, i.e., the carrier board of the ECM refer to the substrate above.

In an alternative embodiment of the present disclosure, when a dual connector configuration is used, in an achievable configuration specification of the edge computing device, the edge computing function chip may use a high-pass QSM8250 processor, and the memory specification of the processor may use LPDDR 512 GB, 64bit, 2750 MHz; the edge computing device is also compatible with video processing functions, graphics processing functions and security processing functions; illustratively, an Adreno VPU 665-fifth generation UHD video processing unit may be employed to implement video processing functionality, an Adreno GPU 650 may be employed to implement graphics processing functionality in conjunction with OpenGL and OpenCL techniques, and a processor security engine may be employed to implement security processing functionality in conjunction with a mobile payment security processing unit, biometric (e.g., fingerprint, iris, voice, facial, etc.) recognition, and the like.

Illustratively, in the edge computing device, an AI acceleration module may be optionally provided. Correspondingly, 1 dual-wide m.2ai module slot may be provided, or 2 single-wide m.2ai module slots may be provided, to support artificial intelligence and machine learning. Illustratively, the AI acceleration module may be supported by the substrate system.

Illustratively, in the edge computing device, 256GB onboard UFS may be provided for storage functions, which may be used to store OS and application software; 1 Micro SD card slot can be provided to automatically expand the Micro SD card, the maximum support SD3.0 rate SDR104, the maximum capacity can be 2TB, and the Micro SD card can be supported by a substrate system; and 1 M.2SSD slot can be arranged, can support 2280-specification PCIE interfaces and can be supported by a substrate system.

For example, in the edge computing device, 2 wired network interfaces may be provided for the wired network, such as a gigabit ethernet interface and an optical interface (i.e., an optical-electrical multiplexing alternative), which are supported by the substrate system.

For example, in the edge computing device, a wireless network interface may be configured for a wireless network to support m.25g communication module installation and support 5G mobile communication.

For example, in the edge computing device, 4 SMA antenna interfaces may be further provided, 1 SIM card slot may be further provided, and a 5G millimeter wave antenna module may be further optionally configured, where the module needs to be installed in a substrate system; a display interface can be arranged to support the HDMI to pass through the substrate system interface; audio interfaces, such as 1 audio input interface and 1 audio output interface, can also be arranged, the plane of the interface is circular, and the diameter can be 3.5 mm; an acoustic interface can also be arranged and can be supported by the substrate system; USB interfaces can be arranged, for example, 2 USB2.0 interfaces (panels) and 1 USB2.0 interface (internal for expanding USB dongle), and the interface form can be Type-A; alarm interfaces, such as 1 RS232 and 1 RS485, can also be arranged for connecting an external cradle head, an access control system and other systems; 4 alarm outputs can also be provided for connecting external alarm output devices, such as a smoke sensing system; 4 alarm inputs may also be provided for connection to external alarm input devices, such as an access control system.

In other embodiments, the edge processing apparatus may also adopt other specification structures, which are not described or limited herein.

In an optional embodiment of the present disclosure, the core board 40 or the edge computing device as a whole may implement power supply/receiving based on the power management device of any one of the above embodiments.

In an alternative embodiment of the present disclosure, as shown in fig. 13 and 14, an opening area 400 is formed on the core board 40, and the opening area 400 is disposed corresponding to the edge calculation function chip 41.

In the embodiment of the present disclosure, by setting the opening area 400 at the position corresponding to the edge calculation function chip 41, the edge calculation function chip 41 can also quickly dissipate heat toward one side of the core board 41 by using the opening area 400, so as to achieve the effect of dissipating heat from both sides and improving the heat dissipation efficiency.

Further, the opening area 400 is also used for the heat dissipation and conduction column to pass through, and the heat dissipation and conduction column passes through the opening area 400 and contacts one side of the edge calculation function chip 41 facing the core board 41, such as the surface of the memory chip, so as to achieve double-sided heat dissipation and achieve good heat dissipation.

In an optional embodiment of the present disclosure, components such as the edge computing function chip 41 on the core board 40 may adopt an industrial-grade specification design, and the storage temperature range may be: -40 ℃ to +85 ℃, and the working temperature standard range is as follows: -25 ℃ to +65 ℃, and the wide temperature range is: -40 ℃ to +65 ℃; the storage humidity and the working humidity are both: 5% RH-95% RH, no condensation; the protection grade is IP40, and the heat dissipation mode is fanless natural heat dissipation; and the high/low temperature resistant, dustproof, anti-seismic, strong electromagnetic interference resistant and other performances are achieved, and the high/low temperature resistant, dustproof, anti-seismic and strong electromagnetic interference resistant device can adapt to severe working environments.

In an optional embodiment of the present disclosure, the core board may support temperature monitoring of the temperature sensor, and two temperature monitoring points may be disposed around the upper edge calculation function chip 41 of the core board, so as to realize temperature monitoring based on the principle that the resistance value of the thermistor changes in response to a change in temperature.

Further, the overall power consumption of the edge computing device must meet the requirements of different SoC computing platforms and various functional chips, and the heat dissipation must meet the threshold operating temperature range requirement.

For example, taking a system-on-chip QSM8250 platform as an example, the chip power consumption may include:

QSM8250 is adopted to realize SoC function, corresponding power consumption can be 12.5Watt, and UFS flash memory is included, for example, power consumption of 125GB memory chip; an LT9611UXC video conversion chip is adopted to realize a display function, for example, the mipi of a mobile phone is converted into the HDMI so as to adapt to the display of a liquid crystal screen, and the corresponding power consumption can be 0.013 Watt; the LAN7800 is adopted to realize the LAN card function, and the corresponding power consumption can be 1.7 Watt; the HUBUSB hub function is realized by adopting a USB5807CT-I/KD, and the corresponding power consumption can be 0.508Watt or 1.226 Watt; the PCIe switch function is realized by adopting ASM2812I, and the corresponding power consumption can be 1.405Watt or 2.163 Watt; the WCD-9385 is adopted as an audio codec, and corresponding power consumption comes from SoC; MCP25625 as a CAN controller with corresponding power consumption of 0.35 Watt; the XR33202 is used as an RS485 serial communication interface chip, and the corresponding power consumption can be 0.003 Watt; the MAX3221 is used as an RS232 serial communication interface chip, and the corresponding power consumption can be 0.003 Watt.

It can be understood that each of the above power consumptions is related to an operating factor such as an operating state and an operating environment of the corresponding functional component, and is not described in detail herein.

It can be understood that the corresponding part of the interface of the chip from the connector to the substrate, UFS and memory is only within the SOM. That is, these functional chips may be provided on the substrate or the core board as needed, and the terminals of the main connector are adaptively adjusted based on the signal transmission relationship between the substrate and the core board.

In an alternative embodiment of the present disclosure, the core board may incorporate a power supply from the main high speed connector to supply power to the entire core board, which has to consume less than 30W.

Illustratively, the power supply pin supplies power as follows:

the pin P3V3 is a 3.3V power supply input, corresponds to a 3.3V voltage source, has 8 pins and can support power consumption of 26.4 Watt; the pin P5V is a 5V power supply input, corresponds to a 5V voltage source, has 2 pins and can support power consumption of 10 Watt; the pin P3V3_ STBY is a 3.3V STBY power supply input, corresponds to a 3.3V STBY voltage source, has 2 pins and can support power consumption of 6.6 Watt; the pin VCCRTC _3P3 is a 3V RTC power supply input, corresponds to a 3.3V RTC voltage source, has 1 pin number and can support power consumption of 3.3 Watt; pin GND, power ground, and 67 pins in number.

Illustratively, in conjunction with the electrical characteristics of the edge computing device, the absolute minimum rating (referred to as "minimum"), maximum rating (referred to as "maximum") of each set of voltages, and the proposed operating range for each set of voltages based thereon, are as follows (shown in "pin name | | | minimum | | | maximum | | | proposed range", voltage in V):

P3V3||-0.5||3.6||3.135～3.465；

P5V||-0.3||6||4.75～5.25；

P3V3_STBY||-0.5||3.6||3.135～3.465；

VCCRTC_3P3||-0.3||3.3||2.79～3.21；

GND||0||0||0～0。

the edge computing equipment provided by the embodiment of the disclosure adopts a modular design, can be independently evolved, has expansibility and compatibility, and is beneficial to ensuring that the edge computing equipment and a system comprising the equipment have compatibility of various solutions and system upgrading iteration requirements after future computing power is improved; meanwhile, the core board adopts two structural size forms, and more elastic configurations are provided for the EBB + ECM overall solution; the interface definition fully considers the functional requirements of the edge computing industry on the universal interface, and can meet the requirements under various different edge computing scenes; finally, aiming at the heat dissipation of the double-sided chip module, the double-sided heat dissipation is realized by arranging the opening area, and the heat dissipation efficiency is improved.

The embodiment of the present disclosure further provides an edge computing system, where the edge computing system may include the power management device in any of the above embodiments, or include the edge computing device in any of the above embodiments, and has a corresponding technical effect.

In the embodiment of the present disclosure, the edge computing device is disposed in the edge computing system, and other terminal devices may not have a power supply function, so in an edge computing system, some devices may support a POE function, and some devices may not support the POE function, and power on or power off is required, that is, the power management device may couple or separate the dc power and the network transmission line, and the dc power obtained after separation may be used by other electrical devices, and during use, the dc power needs to be reprocessed, such as boosting, reducing voltage, and balancing. The electricity consuming device may be, for example, an edge computing device or a data acquisition device, and is not limited herein.

Meanwhile, in the edge computing equipment, the connection that can peel off between the core board and the base plate, the core board that possesses different computing power can combine different base plates, form multiple different edge computing equipment, realize that the edge computing platform that accords with optional configuration elasticity is nimble, satisfy the demand of multiple different edge computing scenes.

The foregoing description is only exemplary of the preferred embodiments of the disclosure and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the disclosure herein is not limited to the particular combination of features described above, but also encompasses other embodiments in which any combination of the features described above or their equivalents does not depart from the spirit of the disclosure. For example, the above features and (but not limited to) the features disclosed in this disclosure having similar functions are replaced with each other to form the technical solution.

Further, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A power management device is characterized by comprising at least one power management unit, wherein each power management unit comprises a mode switching switch, a power supply loading circuit, a power receiving power supply separating circuit, a power line and a network transmission line;

the network transmission line is connected to an edge computing device.

2. The power management device of claim 1, wherein the power supply loading circuit comprises:

the boost sub-circuit is used for boosting the direct current of the first voltage transmitted on the power line into the direct current of a second voltage, and the value of the second voltage is greater than that of the first voltage;

and the loading sub-circuit is used for loading the direct current of the second voltage onto the network transmission line.

3. The power management device according to claim 2, wherein the power receiving power source separation circuit includes:

a splitting sub-circuit for splitting the direct current of the third voltage from the network transmission line;

and the voltage reduction sub-circuit is used for reducing the direct current of the third voltage into direct current of a fourth voltage, and the value of the fourth voltage is smaller than that of the third voltage.

4. The power management device of claim 1, wherein the number of the power management units is at least two, power lines of the at least two power management units are electrically connected as a common power output, each of the power management units further comprising:

a load balancing circuit connected in series with the power receiving power supply separation circuit;

and the load balancing circuits among different power management units are electrically connected so as to balance the load among the at least two power management units.

5. The power management device according to claim 4, wherein each power management unit is packaged in a housing, the housing is provided with a first opening for a network transmission line to pass through, a second opening for a power line to pass through, and a third opening for a cascading probe to pass through, and the cascading probe is used for electrically connecting the load balancing circuits between different power management units.

6. The power management device of claim 1, wherein the network transmission line coupled to the edge computing device is configured to transmit network signals and direct current; or

The network transmission line connected to the edge computing device is used to transmit network signals.

7. The power management device according to claim 1, wherein the edge computing device connected to the network transmission line comprises a core board and a substrate, the core board is provided with an edge computing function chip, the substrate is provided with a signal transmission interface, and the edge computing function chip on the core board is connected to the signal transmission interface on the substrate through at least one connector.

8. The edge computing equipment is characterized by comprising a core board and a substrate, wherein an edge computing function chip is arranged on the core board, a signal transmission interface is arranged on the substrate, and the edge computing function chip on the core board is connected with the signal transmission interface on the substrate through at least one connector;

the signal transmission interface is connected with the power management equipment through a network transmission line.

9. The edge computing device of claim 8, wherein the at least one connector comprises a master connector secured to an edge of the core board.

10. The edge computing device of claim 9, wherein the main connector comprises a first column of signal terminals, a second column of signal terminals, a third column of signal terminals, a fourth column of signal terminals, and a fifth column of signal terminals;

the first column of signal terminals comprises a power supply terminal, a first USB signal terminal and a first CAN bus signal terminal;

the second column of signal terminals comprises a first HDMI signal terminal, a first Ethernet signal terminal and a second USB signal terminal;

the third column signal terminals comprise a first mobile communication signal terminal, a second HDMI interface signal terminal, a first memory signal terminal and a first SPI signal terminal;

the fourth column of signal terminals includes a first AI module signal terminal and a second mobile communication signal terminal;

the fifth column of signal terminals includes a second memory signal terminal and a third mobile communications signal terminal.

11. The edge computing device of claim 8, wherein the at least one connector comprises a secondary connector secured to an edge of the core board.

12. The edge computing device of claim 11, wherein the auxiliary connector comprises a sixth column of signal terminals, a seventh column of signal terminals, an eighth column of signal terminals, a ninth column of signal terminals, and a tenth column of signal terminals;

the sixth column of signal terminals comprises CSI signal terminals and a third USB signal terminal;

the seventh column of signal terminals comprises a JTAG signal terminal, a fourth USB signal terminal and a second Ethernet signal terminal;

the eighth column of signal terminals comprises a fourth mobile communication signal terminal, a third HDMI interface signal terminal and a second SPI signal terminal;

the ninth column of signal terminals comprises audio signal terminals, serial communication bus signal terminals and memory card signal terminals;

the tenth column of signal terminals includes a second AI module signal terminal and a second CAN bus signal terminal.

13. The edge computing device of claim 8, wherein the core board has an opening area formed thereon, the opening area being disposed in correspondence with the edge computing functional chip.

14. The edge computing device of claim 8, wherein the power management device coupled to the network transmission line comprises at least one power management unit, each of the power management units comprising a mode switch, a power supply loading circuit, a power supply splitting circuit, a power line, and a network transmission line;

the power receiving power supply separation circuit is used for separating the direct current transmitted from the network transmission line to the power supply line.

15. An edge computing system comprising a power management device as claimed in any one of claims 1 to 7 and an edge computing device as claimed in any one of claims 8 to 14.