CN206211846U - DC buck voltage-stablizer and its pulse frequency modulated control circuit - Google Patents
DC buck voltage-stablizer and its pulse frequency modulated control circuit Download PDFInfo
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Abstract
This disclosure relates to DC buck voltage-stablizer and its PFM control circuit, belong to electronic circuit field, power consumption can be reduced.The circuit includes：Triangular-wave generator, enables when signal is enabled in triangular-wave generator and produces triangular wave；Sampling unit, the sample peak point current of inductive element and the output voltage of DC buck voltage-stablizer；PFM control units, inductive element is controlled to be in charged state when first condition meets, when peak point current is more than pre-set peak value current threshold, control inductive element is in freewheeling state, and wherein first condition is that both in following three have met and remaining one is from being unsatisfactory for being changed into meeting：Peak point current is less than pre-set peak value current threshold, output voltage less than predetermined reference voltage and a triangular wave charging-discharging cycle completion；Synchronization unit, makes triangular-wave generator enable the timing synchronization that moment starts with inductive element charging that signal starts to enable.
Description
Technical field
The embodiment of the present disclosure is related to electronic circuit field, in particular it relates to a kind of DC buck voltage-stablizer and its pulse
Frequency modulation(PFM) controls circuit.
Background technology
As on-chip system and mobile phone modules are to the demand of High-current output, DC buck voltage-stablizer needs to exist
All there is efficiency higher in the case of underloading and heavy duty.
In order to improve efficiency in underloading, the more commonly used underloading control model is jump modulation (Pulse Skip between pulse
Modulation, PSM) control model.The control principle of PSM current-mode control patterns is as shown in figure 1, the schematic diagram is directed to
The upper pipe of the buck of DC buck voltage-stablizer is PMOS, down tube is NMOS.Its operation principle is as follows：
The work loop of pulsewidth modulation (Pulse Width Modulation, PWM) pattern is：The output voltage of buck
Vout is by obtaining feedback voltage V FB after the feedback network being made up of C1, R1 and R2；Feedback voltage V FB is input to computing and puts
Big device EA, the reference signal Vref with buck output voltages are compared, compare the output voltage modulated signal VC for obtaining and pass through
It is compared with oblique wave sampled signal Vramp after the compensation network be made up of C2, C3 and R3, the output letter of comparator PWMCMP is again
The power switch pipe of buck is driven by driver.
The work loop of PSM patterns is：Control loop before VC signals is identical with PWM mode.When load current drop
When low, VC signals are decreased.When VC signals are less than VrefPSM signals, by the way that after comparator PSMCMP, PSM controls will be produced
Signal processed.As PSM=1, buck is operated in PFM patterns, and otherwise buck is operated in PWM mode.In PFM states, buck will
With PWM frequency open several times, when buck output voltage be higher than threshold voltage after, buck by shutdown switch, in discharge condition.
Load current is bigger, and the number of times of unlatching is more, conversely, the number of times opened is then fewer.
Such scheme the disadvantage is that, PSM control models are actually the discontinuous operating mode of PWM mode.In PSM patterns
When, the modules needed for PWM work are in enabled state, therefore can not substantially optimization efficiency.Secondly, PSM underloading moulds
The switching frequency each time of formula is identical with PWM mode, and the number of times of unlatching is simply changed according to load change.Therefore, line
Ripple will be different according to load change and the change of opening times.Output voltage ripple will produce shake, produce subharmonic point
Amount.
Utility model content
The purpose of the embodiment of the present disclosure is to provide a kind of DC buck voltage-stablizer and its pulse frequency modulated control circuit,
Can solve the problem that above mentioned problem of the prior art.
To achieve these goals, the embodiment of the present disclosure provides a kind of pulse frequency for DC buck voltage-stablizer and adjusts
System control circuit, the DC buck voltage-stablizer includes being provided to load the inductive element of electric current, and the circuit includes：
Triangular-wave generator, triangular wave is produced for being enabled when signal is enabled in triangular-wave generator；
Sampling unit, for the peak point current to the inductive element and the output voltage of the DC buck voltage-stablizer
Sampled；
Pulse frequency modulated control unit, for controlling the inductive element to be in charging shape when first condition meets
State, controls the inductive element to be in freewheeling state, wherein described when the peak point current is more than pre-set peak value current threshold
First condition is that both in following three have met and remaining one is from being unsatisfactory for being changed into meeting：The peak point current is less than
The pre-set peak value current threshold, the output voltage are less than predetermined reference voltage and a triangular wave charging-discharging cycle completion；
Synchronization unit, the moment for making the triangular-wave generator enable signal start to enable fills with the inductive element
Establish the timing synchronization of beginning by cable.
According to the another aspect of the embodiment of the present disclosure, there is provided a kind of DC buck voltage-stablizer, the DC buck voltage stabilizing
Device includes that above-mentioned pulse frequency modulated controls circuit.
Above-mentioned technical proposal is by when DC buck voltage-stablizer is in light condition, making the triangle of triangular-wave generator
Wave producer enables signal and starts the timing synchronization that the inductive element charging of the moment and DC buck voltage-stablizer for enabling starts,
And limit the purpose that the peak point current of inductive element reaches PFM controls during underloading no more than pre-set peak value current threshold.By
In the peak inrush current for limiting inductive element charging, therefore according to input and output voltage and inductance value, can draw in PFM shapes
The ripple value of maximum switching frequency (i.e. PWM working frequencies) under state.Again by the cut-off current and current ripples size of peak point current,
The load current threshold from PFM pattern switching to PWM mode can be drawn.And because the switching frequency of output current can be with load electricity
Cleanliness increases, and then ripple can linearly diminish, and order harmonic components will not be produced under whole PFM patterns.Further, since PFM
Control circuit simple structure, and under PFM control models do not need PWM loops work always, therefore rise reduce direct current
The power consumption of buck regulator, improves efficiency.And the triangular-wave generator of triangular-wave generator is enabled signal and start to enable
Moment and inductive element charge the timing synchronization for starting, then can solve the problem that some load patch occur due to triangle period of wave
With current charge-discharge electricity the cycle be it is non-integral multiple caused by output voltage fall or upper punching problem.
Other feature and advantage of the embodiment of the present disclosure will be described in detail in subsequent specific embodiment part.
Brief description of the drawings
Accompanying drawing is the embodiment of the present disclosure to be further understood for providing, and constitutes a part for specification, with
The specific embodiment in face is used to explain the embodiment of the present disclosure together, but does not constitute the limitation to the embodiment of the present disclosure.Attached
In figure：
Fig. 1 is the principle schematic of existing PSM control models；
Fig. 2 is the buck structural representations in DC buck voltage-stablizer；
Fig. 3 is to control showing for circuit according to the pulse frequency modulated for DC buck voltage-stablizer of the embodiment of the present disclosure
Meaning block diagram；
Fig. 4 is the illustrative circuitry of the triangular-wave generator that circuit is controlled according to the pulse frequency modulated of the embodiment of the present disclosure
Figure；
Fig. 5 is showing for the pulse frequency modulated control unit according to the pulse frequency modulated of embodiment of the present disclosure control circuit
Meaning circuit diagram；
Fig. 6 is the schematic circuit diagram of the synchronization unit that circuit is controlled according to the pulse frequency modulated of the embodiment of the present disclosure；
Fig. 7 is to control the pulse frequency modulated pattern of circuit to pass in and out control according to the pulse frequency modulated of the embodiment of the present disclosure
The schematic circuit diagram of unit；
Fig. 8 shows the simulation result of the lower PFM control models of 100mA loads；
Fig. 9 shows the simulation result of PFM control models in load change procedure；
Figure 10 is the pulse frequency modulated controlling party for DC buck voltage-stablizer according to a kind of embodiment of the disclosure
The flow chart of method.
Specific embodiment
The specific embodiment of the embodiment of the present disclosure is described in detail below in conjunction with accompanying drawing.It should be appreciated that this
The described specific embodiment in place is merely to illustrate and explains the embodiment of the present disclosure, is not limited to the embodiment of the present disclosure.
The embodiment of the present disclosure provides a kind of pulse frequency modulated for DC buck voltage-stablizer and controls circuit, the direct current
Buck regulator includes being provided to load the inductive element of electric current.Fig. 2 shows what the DC buck voltage-stablizer was driven
The schematic circuit diagram of buck power switch pipes and its passive control element.As shown in Fig. 2 the PFM control letters obtained under PFM patterns
Number by after driver 20 control buck in upper pipe M11 and down tube M12 break-make.When M11 conductings, M12 disconnect, perception unit
Part L charges, so as to be the load supplying being made up of capacitor C and resistor R；When M11 disconnections, M12 are turned on, inductive element L
In freewheeling state.In addition, the pwm control signal obtained under PWM mode is also by the upper pipe controlled after driver 20 in buck
The break-make of M11 and down tube M12.
It will be apparent to a skilled person that Fig. 2 is only example.In fact, straight described in the embodiment of the present disclosure
Stream buck regulator and its pulse frequency modulated control circuit are applied to any kind of buck structures of driving.
The pulse frequency modulated control for DC buck voltage-stablizer according to the embodiment of the present disclosure described in detail below
Circuit.As shown in figure 3, the circuit can include：
Triangular-wave generator 301, triangular wave is produced for being enabled when signal is enabled in triangular-wave generator；
Sampling unit 302, for the output of the peak point current to the inductive element and the DC buck voltage-stablizer
Voltage is sampled；
Pulse frequency modulated control unit 303, charges for controlling the inductive element to be in when first condition meets
State, controls the inductive element to be in freewheeling state, wherein institute when the peak point current is more than pre-set peak value current threshold
It is that both in following three have met and remaining one is from being unsatisfactory for being changed into meeting to state first condition：The peak point current is small
In the pre-set peak value current threshold, the output voltage is less than predetermined reference voltage and a triangular wave charging-discharging cycle is complete
Into；
Synchronization unit 304, the moment of enable and the perception unit are started for making the triangular-wave generator enable signal
The timing synchronization that part charging starts.
Above-mentioned technical proposal is by when DC buck voltage-stablizer is in light condition, making triangular-wave generator 301
Triangular-wave generator enables inductive element L (shown in Fig. 2) chargings that signal starts the moment and DC buck voltage-stablizer for enabling
The timing synchronization of beginning, and limit the peak point current of inductive element L no more than pre-set peak value current threshold and reach during underloading
The purpose of pulse frequency modulated (Pulse Frequency Modulation, PFM) control.Charged due to limiting inductive element
Peak inrush current, therefore according to input and output voltage and inductance value, can show that maximum switching frequency is (i.e. under PFM states
PWM working frequencies) ripple value.Again by the cut-off current and current ripples size of peak point current, can draw from PFM pattern switchings
To the load current threshold of PWM mode.And because the switching frequency of output current can linearly increase with load current, then ripple
Can linearly diminish, order harmonic components will not be produced under whole PFM patterns.Further, since the simple structure of PFM control circuit,
And do not need PWM loops to work always under PFM control models, therefore the power consumption for reducing DC buck voltage-stablizer is acted,
Improve efficiency.And the triangular-wave generator of triangular-wave generator 301 is enabled moment and inductive element L that signal starts to enable
Charge the timing synchronization for starting, then can solve the problem that in the appearance of some load patch due to triangle period of wave and current charge-discharge electricity cycle
For non-integral multiple caused output voltage fall or upper punching problem.
In a kind of possible implementation method, when DC buck voltage-stablizer is in heavy condition, it is operated in PWM moulds
In formula, now triangular-wave generator enables signal and is constantly in enabled state, therefore triangular-wave generator 301 being capable of the company of generation
Continuous triangular wave.Produced triangular signal can be compared to obtain tying the buck for example shown in Fig. 2 with reference signal
The pwm control signal that structure is controlled.And when DC buck voltage-stablizer is in light condition, the triangular-wave generator makes
Energy signal starts the timing synchronization that the moment for enabling and inductive element L chargings start, and this causes that triangular-wave generator 301 is produced
The interrupted triangular wave of life.
In a kind of possible implementation method, the circuit structure of triangular-wave generator 301 can be with as shown in figure 4, can wrap
Include：
Connected by the first semiconductor switch S11, the 3rd semiconductor switch S13 and capacitor C1 the charge circuit for being formed, institute
The voltage at capacitor C1 two ends is stated as the output voltage vtri of the triangular-wave generator 301, the 3rd semiconductor switch
The break-make of S13 enables signal PFM_ch_ctl and controls by the triangular-wave generator；
Connected by the second semiconductor switch S12, the 3rd semiconductor switch S13 and capacitor C1 electric discharge for being formed
Loop；
The output voltage vtri and triangular wave high voltage threshold vh of the triangular-wave generator 301 are used as the second comparator
The input signal of CMP2, the output voltage vtri and triangular wave low voltage threshold vl of the triangular-wave generator 301 are used as first
The input signal of comparator CMP1, the output signal vl_th1 of the first comparator CMP1 and the second comparator CMP2's
Output signal vh_th1 as rest-set flip-flop RS1 input signal, the Q output signals vcharge of the rest-set flip-flop RS1 is used for
It is in the conduction state when controlling the first semiconductor switch S11 different with the second semiconductor switch S12.
By the triangle generator circuit structure shown in Fig. 4, when DC buck voltage-stablizer works in a PWM mode
When, triangular-wave generator enables signal PFM_ch_ctl can control the 3rd semiconductor switch S13 to be constantly in conducting state (example
Such as, if the 3rd semiconductor switch S13 is NMOS tube, triangular-wave generator enables signal PFM_ch_ctl and is equal to 1, namely always
It is high level), to ensure the closure of charging and discharging circuit, so as to carry out continuous discharge and recharge to capacitor C1, produce continuous
Triangular signal vtri.And preferably, the size of current of the charge circuit and the discharge loop is equal, namely charge
Electric current Ich is equal in magnitude with discharge current Idisch.In addition, triangular wave high voltage threshold vh and triangular wave low voltage threshold vl
Purpose is to limit the peak-to-peak value of produced triangular wave.
In addition, the discharge and recharge frequency of triangular-wave generator 301 is controlled by the Q output signals vcharge of rest-set flip-flop RS1
System.Wherein, if the conduction type of the first semiconductor switch S11 and the second semiconductor switch S12 is identical, can for example use
Vcharge signals control the second semiconductor switch S12, control the first half to lead with the inversion signal vchargeB of vcharge
Body switchs S11.And if the conduction type of the first semiconductor switch S11 and the second semiconductor switch S12 is different, then can be such as
The second semiconductor switch S12 and the first semiconductor switch S11 is controlled with vcharge signals simultaneously.
In a kind of possible implementation method, the circuit structure of the pulse frequency modulated control unit 303 can be such as Fig. 5
It is shown, can include：
The peak point current Isample of the inductive element L and pre-set peak value current threshold PFM_lim is used as the 4th comparator
The input signal of CMP4, the output voltage VFB of the DC buck voltage-stablizer and predetermined reference voltage Vref is used as
The input signal of three comparator CMP3, power supply signal VDD as the first d type flip flop D1 input signal, the rest-set flip-flop RS1
Q output signals vcharge inversion signal vchargeB as the first d type flip flop D1 clock signal；
The output signal S1 of the 4th comparator CMP4, the Q output signals S2 of the first d type flip flop D1 and described
The output signal S3 phases of three comparator CMP3 with afterwards, the place of the device M1 by rising edge signal to be changed into rising pulses signal
With pulse frequency modulated enable signal PFM_EN phases with the output signal of Xiang Yuhou is triggered as the 2nd D after reason and anti-phase treatment
The clear terminal input signal of device D2, the pulse frequency modulated is enabled when signal PFM_EN is enabled makes the DC buck voltage stabilizing
Device into pulse frequency modulated pattern, do not enable when the DC buck voltage-stablizer is entered PWM mode；
The Q output signals PFM of the second d type flip flop D2 is changed into rising pulses by anti-phase treatment, by rising edge signal
Signal PFM_EN phases and the letter of Xiang Yuhou are enabled after treatment, the anti-phase treatment of the device M2 of signal with the pulse frequency modulated
Number as the first d type flip flop D1 clear terminal input signal；
The output signal S1 of the 4th comparator CMP4 believes by anti-phase treatment, by rising edge signal change rising pulses
Number device M3 treatment, anti-phase treatment after enable signal PFM_EN phases and, the signal of Xiang Yuhou with the pulse frequency modulated
Used as the clock signal of the second d type flip flop D2, the power supply signal VDD is the input signal of the second d type flip flop D2.
By the circuit structure of the pulse frequency modulated control unit 303 shown in Fig. 5, the Q of the second d type flip flop D2 is defeated
Go out the on off state of the upper down tube of buck when signal PFM determines that DC buck voltage-stablizer is in PFM control models.With Fig. 2
As a example by shown buck structures, as PFM=1, disconnected corresponding to upper pipe M11, down tube M12 is turned on, i.e. inductive element L is in continuous
Stream mode；Conversely, during PFM=0, being disconnected corresponding to upper pipe M11 conductings, down tube M12, then inductive element L is in charged state.
During non-PFM patterns (namely pwm pattern), i.e. PFM_EN=0, the second d type flip flop D2 are in cleared condition all the time.By above-mentioned
Description understands so that inductive element L is in freewheeling state, it is necessary to the output signal S1 for meeting the 4th comparator is experienced by 1 to 0
Process, i.e. Isample current sampling signals become greater than PFM_lim by less than PFM_lim, and such S1 signals are by phase inverter
And will produce a rising edge signal, now the second d type flip flop D2 at the clock signal CK ends of the second d type flip flop D2 after module M3
Clear terminal input signal be 1, therefore will cause PFM=1.
Want to make inductive element L to be in charged state, then need to allow the clear terminal input signal of the second d type flip flop D2 be
Zero.Meet this condition needs satisfaction：The output signal S1 of the 4th comparator, the output signal S2 and the 3rd of the first d type flip flop
In the output signal S3 of comparator, it is 1 to have two output signals, and another output signal is then changed into 1 from 0.So, three it is defeated
Go out signal by a rising edge signal after logical AND gate, will be produced；Again by M1 modules, rising edge signal is converted into rise
Pulse signal；After eventually passing phase inverter, negative pulse input signal is produced in the clear terminal RN of the second d type flip flop D2.Wherein, S1
=1, show PFM_lim>Isample；S2=1, shows that triangular-wave generator 301 has completed a charging-discharging cycle；S3=1,
Show VFB<Vref.
Therefore, the clear terminal RN in the second d type flip flop D2 produces negative pulse to there are three kinds of combinations：
(1) S1=1, S2=1, S3 are changed into 1 from 0.This corresponds to the peak value sampling electric current of the upper PMOS of buck structures
Isample is less than pre-set peak value current threshold PFM_lim, and a triangular wave charging-discharging cycle has been completed, and now occurs in that straight
The output voltage VFB for flowing buck regulator is less than predetermined reference voltage Vref, therefore now inductive element L will be charged；
(2) S1=1, S3=1, S2 are changed into 1 from 0.This corresponds to the peak value sampling electric current of the upper PMOS of buck structures
Isample is less than pre-set peak value current threshold PFM_lim, and the output voltage VFB of DC buck voltage-stablizer is less than preset reference
Voltage Vref, a triangular wave charging-discharging cycle is just completed, i.e. the inversion signal of the Q output signals of rest-set flip-flop RS1
VchargeB is changed into 1 from 0；
(3) S2=1, S3=1, S1 are changed into 1 from 0.This has been completed corresponding to a triangular wave charging-discharging cycle, direct current drop
Peak value sampling electric currents of the output voltage VFB of die mould voltage-stablizer less than the upper PMOS of predetermined reference voltage Vref, buck structure
Isample will cause PFM=1 after more than PFM_lim, and now Isample will decline, after its value is less than PFM_lim, the
The output signal S1 of four comparators will be changed into 1 from 0.
Fig. 6 shows the exemplary circuit figure of synchronization unit 304.Wherein, the synchronization unit 304 can be touched including the 3rd D
Hair device D3, wherein：
The power supply signal VDD as the 3d flip-flop D3 input signal；
The inversion signal vchargeB of the Q output signals vcharge of the rest-set flip-flop RS1 is triggered as the 3rd D
The clock signal of device D3；
The Q output signals PFM of the second d type flip flop D2 is changed into rising pulses by anti-phase treatment, by rising edge signal
Signal PFM_EN phases and the letter of Xiang Yuhou are enabled after treatment, the anti-phase treatment of the device M4 of signal with the pulse frequency modulated
Number as the 3d flip-flop D3 clear terminal input signal；
The QN output signals of the 3d flip-flop D3 enable signal PFM_ch_ctl as the triangular-wave generator.
By the circuit diagram of the synchronization unit 304 shown in Fig. 6, it can be seen that being operated in DC buck voltage-stablizer
During pwm pattern, PFM_EN=0, therefore PFM_ch_ctl=1, now the 3rd semiconductor in triangular-wave generator 301 open
Close S13 in the conduction state all the time so that triangular-wave generator 301 can produce continuous triangular wave, so as to not interfere with just
Normal triangular wave discharge and recharge.When DC buck voltage-stablizer is operated in PFM control models, when PFM is by step-down high, i.e. buck
The upper PMOS turn-on instant of structure, PFM signals by M4 modules produce positive pulse signal, the signal by after phase inverter with
PFM_EN signals phase is input into undersuing with the clear terminal RN in 3d flip-flop D3, therefore 3d flip-flop D3 is clear
Zero so that PFM_ch_ctl=1.Now triangular-wave generator 301 is started to charge up.When vchargeB signals produce a positive pulse
During signal, show that triangular wave charging-discharging cycle is completed, now will be switched off triangular wave charge path, be i.e. now PFM_ch_ctl
=0.Therefore, by the circuit diagram of the synchronization unit 304 shown in Fig. 6, it is possible to achieve triangular-wave generator enables signal
PFM_ch_ctl starts the timing synchronization that moment starts with inductive element L chargings for enabling, and can solve the problem that in some loads
Section occur due to triangle period of wave and current charge-discharge electricity the cycle be it is non-integral multiple caused by output voltage fall or upper punching
Problem.
In a kind of possible implementation method, the pulse frequency modulated control circuit can also include pulse frequency modulated
Pattern passes in and out control unit, and now the sampling unit 302 can be also used for the average electric current under the PWM mode
Sampled.
Fig. 7 shows that pulse frequency modulated pattern passes in and out the circuit diagram of control unit, and it can compare including the 5th
Device CMP5, the 6th comparator CMP6, phase inverter INV1 and with door AND1, wherein, the average electric current that sampling unit 302 is sampled
The equal threshold voltage V that Isense is converted toIsenseWith default average voltage threshold Vth_PFMAs the 5th comparator CMP5's
Input signal, the output voltage VFB of the DC buck voltage-stablizer and the default electricity lower than the predetermined reference voltage Vref
Pressure value VFB_lev1 as the 6th comparator CMP6 input signal, the output signal of the 6th comparator CMP6 passes through
After phase inverter INV1 is anti-phase with the output signal of the 5th comparator CMP5 with door AND1 at obtain the pulse frequency
Rate modulation enables signal PFM_EN.
By the circuit diagram shown in Fig. 7, Vth_PFMIt is the threshold voltage into PFM control models, VFB_lev1 is one
The individual value more lower slightly than predetermined reference voltage Vref.Work as VIsenseLess than Vth_PFMWhen, the output signal of the 5th comparator CMP5 is 1,
And VFB_lev1 is less than VFB, therefore PFM_EN=1 in stable state, so that DC buck voltage-stablizer is into PFM controls
Pattern.When VFB is less than VFB_lev1, the output signal of the 6th comparator CMP6 is 1, therefore PFM_EN=0, namely when load
When electric current is more than peak value current limliting corresponding electric current average, due to the restriction of maximum switching frequency, now inductive element L can not be exported
Enough energy can decline to load, therefore VFB, so as to jump out PFM control models.In addition, presetting equal threshold voltage by setting
Threshold value Vth_PFMSize, the electric current average of its corresponding entrance PFM pattern is less than electric current average when jumping out PFM patterns, this
Retarding window ensure that will not repeatedly be switched under a certain load condition between PFM patterns and PWM mode.
Fig. 8 shows the simulation result of the lower PFM control models of 100mA loads.In simulation result, vtri represents that triangular wave is sent out
Raw device output signal, IL represents that the electric current of inductive element L, PFM control buck power switch pipe break-makes under representing PFM control models
Signal, PFM_ch_ctl represent triangular-wave generator enable signal.From simulation result as can be seen that in light condition,
Vtri signals are synchronous with quarter holding at the beginning of IL signals.In this example, the peak point current of IL is limited in 2A or so, therefore upper pipe
M11 after peak current threshold 2A is reached, will be switched off pipe M11, conducting down tube M12 every time, inductive element L is in afterflow shape
State.After a triangular wave charging-discharging cycle terminates, vtri signals will all the time be in low level threshold value, and until next time, perception is first
Part charges and starts, and triangular-wave generator will start next charge cycle.
Fig. 9 shows the simulation result of PFM control models in load change procedure, wherein load from 20mA changing to 2A.
In Fig. 9, vtri is the output signal of triangular-wave generator, and IL is the electric current of inductive element L, and Vout is DC decompression
The output voltage of type voltage-stablizer, Iload is load current, and PFM_EN is PFM pattern enables signals.PFM_EN=1, shows direct current
Buck regulator is operated in PFM control models.It can be seen that during loading from small change greatly, IL perception unit
The open frequency of part electric current rises, and the open frequency of vtri also rises therewith, and both keep synchronous.When load current becomes big
When, open frequency accelerates, and causes ripple to diminish.At the t1 moment that double-head arrow is indicated, because load current Iload is limited more than peak value
Corresponding average electric current output is flowed, therefore output voltage Vout begins to decline, after it is less than preset value, PFM_EN=0 is jumped out
PFM control models, into pwm pattern.From simulation result as can be seen that at the t1 moment, switching frequency be PWM frequently
Rate, the i.e. peak frequency of PFM mode of operations.Be can visually see from figure, ripple value now is equal to the line under PWM mode
Wave number.On the premise of peak current level and electric current peak-to-peak value is known, you can draw its average electric current.This electric current be from
PFM patterns jump back out to the threshold point of PWM mode.
The embodiment of the present disclosure also provides a kind of DC buck voltage-stablizer, and the DC buck voltage-stablizer includes being described above
For DC buck voltage-stablizer pulse frequency modulated control circuit.
The power management module that the DC buck voltage-stablizer mentioned in the embodiment of the present disclosure can be used in chip for cell phone.
The embodiment of the present disclosure also provides a kind of pulse frequency modulated control method for DC buck voltage-stablizer, and this is straight
Stream buck regulator includes being provided to load the inductive element of electric current, and as shown in Figure 10, the method may comprise steps of：
In step S1001, the output electricity of peak point current and the DC buck voltage-stablizer to the inductive element
Pressure is sampled；
In step S1002, the inductive element is controlled to be in charged state when first condition meets, wherein described straight
The triangular-wave generator enable signal for flowing the triangular-wave generator of buck regulator starts the moment for enabling and the perception unit
The timing synchronization that part charging starts, the triangular-wave generator is used to enable generation when signal is enabled in the triangular-wave generator
Triangular wave；Wherein, the first condition is that both in following three have met and remaining one is from being unsatisfactory for being changed into meeting：
The peak point current is less than predetermined reference voltage and a triangular wave less than the pre-set peak value current threshold, the output voltage
Charging-discharging cycle is completed.
In the step s 1003, controlled at the inductive element when the peak point current is more than pre-set peak value current threshold
In freewheeling state.
Above-mentioned technical proposal is by when DC buck voltage-stablizer is in light condition, making the triangle of triangular-wave generator
Wave producer enables signal and starts the timing synchronization that the inductive element charging of the moment and DC buck voltage-stablizer for enabling starts,
And limit the purpose that the peak point current of inductive element reaches PFM controls during underloading no more than pre-set peak value current threshold.By
In the peak inrush current for limiting inductive element charging, therefore according to input and output voltage and inductance value, can draw in PFM shapes
The ripple value of maximum switching frequency (i.e. PWM working frequencies) under state.Again by the cut-off current and current ripples size of peak point current,
The load current threshold from PFM pattern switching to PWM mode can be drawn.And because the switching frequency of output current can be with load electricity
Cleanliness increases, and then ripple can linearly diminish, and order harmonic components will not be produced under whole PFM patterns.Further, since PFM
Control circuit simple structure, and under PFM control models do not need PWM loops work always, therefore rise reduce direct current
The power consumption of buck regulator, improves efficiency.And the triangular-wave generator of triangular-wave generator is enabled signal and start to enable
Moment and inductive element charge the timing synchronization for starting, then can solve the problem that some load patch occur due to triangle period of wave
With current charge-discharge electricity the cycle be it is non-integral multiple caused by output voltage fall or upper punching problem.
In a kind of possible implementation method, the triangular-wave generator includes：
Connected by the first semiconductor switch, the 3rd semiconductor switch and capacitor the charge circuit for being formed, the capacitor
The voltage at two ends as the triangular-wave generator output voltage, the break-make of the 3rd semiconductor switch is by the triangular wave
Generator enables signal control；
Connected by the second semiconductor switch, the 3rd semiconductor switch and the capacitor discharge loop for being formed；
The output voltage of the triangular-wave generator and triangular wave high voltage threshold as the second comparator input signal,
The output voltage of the triangular-wave generator and triangular wave low voltage threshold as first comparator input signal, described first
The output signal of comparator and second comparator as rest-set flip-flop input signal, the rest-set flip-flop Q output letter
Number for control first semiconductor switch different with second semiconductor switch when it is in the conduction state.
In a kind of possible implementation method, the size of current of the charge circuit and the discharge loop is equal.
It is described to control the inductive element to be in charging shape when first condition meets in a kind of possible implementation method
State and the step for controlling the inductive element to be in freewheeling state when the peak point current is more than pre-set peak value current threshold
Suddenly realized by pulse frequency modulated control unit, the pulse frequency modulated control unit includes：
The peak point current and the pre-set peak value current threshold as the 4th comparator input signal, the direct current drop
The output voltage of die mould voltage-stablizer and the predetermined reference voltage as the 3rd comparator input signal, power supply signal is used as
The input signal of one d type flip flop, the inversion signal of the Q output signals of the rest-set flip-flop as first d type flip flop when
Clock signal；
The output signal of the 4th comparator, the Q output signals of first d type flip flop and the 3rd comparator
Output signal phase with afterwards, by after treatment and anti-phase treatment that rising edge signal is changed into rising pulses signal with pulse frequency
Modulation enables the output signal of signal phase and, Xiang Yuhou as the clear terminal input signal of the second d type flip flop, the pulse frequency
Modulation enable make when signal is enabled the DC buck voltage-stablizer into pulse frequency modulated pattern, do not enable when make it is described straight
Stream buck regulator enters PWM mode；
The Q output signals of second d type flip flop are changed into rising pulses signal by anti-phase treatment, by rising edge signal
With pulse frequency modulated enable signal phase with the signal of Xiang Yuhou is used as first d type flip flop after treatment, anti-phase treatment
Clear terminal input signal；
The output signal of the 4th comparator changes the place of rising pulses signal by anti-phase treatment, by rising edge signal
With pulse frequency modulated enable signal phase with the signal of Xiang Yuhou is used as second d type flip flop after reason, anti-phase treatment
Clock signal, the power supply signal is the input signal of second d type flip flop.
In a kind of possible implementation method, the triangular wave of the triangular-wave generator of the DC buck voltage-stablizer occurs
Device is enabled the step of signal starts the timing synchronization that moment starts with inductive element charging for enabling by synchronization unit reality
Existing, the synchronization unit includes：
3d flip-flop；
The power supply signal as the 3d flip-flop input signal；
The inversion signal of the Q output signals of the rest-set flip-flop as the 3d flip-flop clock signal；
The Q output signals of second d type flip flop are changed into rising pulses signal by anti-phase treatment, by rising edge signal
With pulse frequency modulated enable signal phase with the signal of Xiang Yuhou is used as the 3d flip-flop after treatment, anti-phase treatment
Clear terminal input signal；
The QN output signals of the 3d flip-flop enable signal as the triangular-wave generator.
In a kind of possible implementation method, the method also includes：
Average electric current under the PWM mode is sampled；
According to comparative result of the average electric current with default average current threshold and the DC buck voltage stabilizing that sample
The output voltage of device controls turnover pulse frequency to adjust with the comparative result of the preset voltage value lower than the predetermined reference voltage
Molding formula.
In a kind of possible implementation method, the ratio of the average electric current that the foundation is sampled and default average current threshold
The ratio of the output voltage of relatively result and the DC buck voltage-stablizer and the preset voltage value lower than the predetermined reference voltage
Relatively result come control turnover pulse frequency modulated pattern the step of, can by pulse frequency modulated pattern pass in and out control unit come
Realize,
Pulse frequency modulated pattern turnover control unit include the 5th comparator, the 6th comparator, phase inverter and with
Door, wherein, the average electric current that samples and default average current threshold as the 5th comparator input signal, it is described straight
The output voltage and the preset voltage value lower than the predetermined reference voltage of buck regulator are flowed as the 6th comparator
Input signal, after the output signal of the 6th comparator is anti-phase with the output signal of the 5th comparator with obtain institute
State pulse frequency modulated and enable signal.
According to the such as triangular-wave generator, pulse frequency modulated control unit being related in the method for the embodiment of the present disclosure,
The concrete principle of synchronization unit and pulse frequency modulated pattern turnover control unit is described according to the embodiment of the present disclosure
It has been described in detail in circuit, here is omitted.
Describe the preferred embodiment of the embodiment of the present disclosure in detail above in association with accompanying drawing, but, the embodiment of the present disclosure is simultaneously
The detail in above-mentioned implementation method is not limited to, in the range of the technology design of the embodiment of the present disclosure, can be to disclosure reality
The technical scheme for applying example carries out various simple variants, and these simple variants belong to the protection domain of the embodiment of the present disclosure.
It is further to note that each particular technique feature described in above-mentioned specific embodiment, in not lance
In the case of shield, can be combined by any suitable means.In order to avoid unnecessary repetition, the embodiment of the present disclosure pair
Various possible combinations are no longer separately illustrated.
Additionally, can also be combined between a variety of implementation methods of the embodiment of the present disclosure, as long as it is not
The thought of the embodiment of the present disclosure is run counter to, it should equally be considered as embodiment of the present disclosure disclosure of that.
Claims (8)
1. a kind of pulse frequency modulated for DC buck voltage-stablizer controls circuit, the DC buck voltage-stablizer include to
Load provides the inductive element of electric current, it is characterised in that the circuit includes：
Triangular-wave generator, triangular wave is produced for being enabled when signal is enabled in triangular-wave generator；
Sampling unit, the output voltage for the peak point current to the inductive element and the DC buck voltage-stablizer is carried out
Sampling；
Pulse frequency modulated control unit, for controlling the inductive element to be in charged state when first condition meets,
The peak point current controls the inductive element to be in freewheeling state when being more than pre-set peak value current threshold, wherein described first
Part is that both in following three have met and remaining one is from being unsatisfactory for being changed into meeting：The peak point current is less than described pre-
If peak current threshold, the output voltage are less than predetermined reference voltage and a triangular wave charging-discharging cycle completion；
Synchronization unit, for enabling the triangular-wave generator, signal starts the moment of enable and inductive element charging is opened
The timing synchronization of beginning.
2. circuit according to claim 1, it is characterised in that the triangular-wave generator includes：
Connected by the first semiconductor switch, the 3rd semiconductor switch and capacitor the charge circuit for being formed, the capacitor two ends
Voltage as the triangular-wave generator output voltage, the break-make of the 3rd semiconductor switch occurs by the triangular wave
Device enables signal control；
Connected by the second semiconductor switch, the 3rd semiconductor switch and the capacitor discharge loop for being formed；
The output voltage of the triangular-wave generator and triangular wave high voltage threshold as the second comparator input signal, it is described
The output voltage of triangular-wave generator and triangular wave low voltage threshold as first comparator input signal, described first compares
The output signal of device and second comparator as rest-set flip-flop input signal, the Q output signals of the rest-set flip-flop use
It is in the conduction state when controlling first semiconductor switch different with second semiconductor switch.
3. circuit according to claim 2, it is characterised in that the size of current of the charge circuit and the discharge loop
It is equal.
4. circuit according to claim 2, it is characterised in that first semiconductor switch and second semiconductor are opened
The conduction type of pass is identical or different.
5. circuit according to claim 2, it is characterised in that the pulse frequency modulated control unit includes：
The peak point current and the pre-set peak value current threshold as the 4th comparator input signal, the DC buck
The output voltage of voltage-stablizer and the predetermined reference voltage as the 3rd comparator input signal, power supply signal is used as a D
The input signal of trigger, the inversion signal of the Q output signals of the rest-set flip-flop is believed as the clock of first d type flip flop
Number；
The output of the output signal, the Q output signals of first d type flip flop and the 3rd comparator of the 4th comparator
Signal phase with afterwards, by after treatment and anti-phase treatment that rising edge signal is changed into rising pulses signal with pulse frequency modulated
The output signal of signal phase and, Xiang Yuhou is enabled as the clear terminal input signal of the second d type flip flop, the pulse frequency modulated
Enable make when signal is enabled the DC buck voltage-stablizer into pulse frequency modulated pattern, do not enable when the direct current drops
Die mould voltage-stablizer enters PWM mode；
The Q output signals of second d type flip flop are changed into the place of rising pulses signal by anti-phase treatment, by rising edge signal
With pulse frequency modulated enable signal phase with the signal of Xiang Yuhou is used as first d type flip flop after reason, anti-phase treatment
Clear terminal input signal；
The output signal of the 4th comparator by anti-phase treatment, by rising edge signal change rising pulses signal treatment,
Enabled with the pulse frequency modulated after anti-phase treatment the signal of signal phase and, Xiang Yuhou as second d type flip flop when
Clock signal, the power supply signal is the input signal of second d type flip flop.
6. circuit according to claim 5, it is characterised in that the synchronization unit includes：
3d flip-flop；
The power supply signal as the 3d flip-flop input signal；
The inversion signal of the Q output signals of the rest-set flip-flop as the 3d flip-flop clock signal；
The Q output signals of second d type flip flop are changed into the place of rising pulses signal by anti-phase treatment, by rising edge signal
With pulse frequency modulated enable signal phase with the signal of Xiang Yuhou is used as the 3d flip-flop after reason, anti-phase treatment
Clear terminal input signal；
The QN output signals of the 3d flip-flop enable signal as the triangular-wave generator.
7. the circuit according to claim 5 or 6, it is characterised in that the pulse frequency modulated control circuit also includes arteries and veins
Frequency modulation pattern turnover control unit is rushed, wherein：
The sampling unit is additionally operable to sample the average electric current under the PWM mode；
Pulse frequency modulated pattern turnover control unit include the 5th comparator, the 6th comparator, phase inverter and with door, its
In, the average electric current that samples and default average current threshold as the 5th comparator input signal, the direct current drop
The output voltage of die mould voltage-stablizer and the preset voltage value lower than the predetermined reference voltage are used as the defeated of the 6th comparator
Enter signal, after the output signal of the 6th comparator is anti-phase with the output signal of the 5th comparator with obtain the arteries and veins
Rush frequency modulation(PFM) and enable signal.
8. a kind of DC buck voltage-stablizer, it is characterised in that the DC buck voltage-stablizer includes appointing in claim 1 to 7
Circuit described in one claim.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106533172A (en) * | 2016-12-08 | 2017-03-22 | 北京松果电子有限公司 | DC step-down voltage regulator and pulse frequency modulation control circuit and method thereof |
| CN110391735A (en) * | 2018-04-16 | 2019-10-29 | 恩智浦有限公司 | PWM mode step-up switching regulator with programmable pulse frequency-hopping mode |
| TWI719511B (en) * | 2019-06-24 | 2021-02-21 | 國立中山大學 | Psm/pwm dual-mode buck converter |
| CN115360910A (en) * | 2022-07-06 | 2022-11-18 | 电子科技大学 | Pulse type energy power management and sensing circuit without external power supply |
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2016
- 2016-12-08 CN CN201621343234.7U patent/CN206211846U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106533172A (en) * | 2016-12-08 | 2017-03-22 | 北京松果电子有限公司 | DC step-down voltage regulator and pulse frequency modulation control circuit and method thereof |
| CN106533172B (en) * | 2016-12-08 | 2023-11-14 | 北京小米松果电子有限公司 | DC voltage-reducing voltage stabilizer and pulse frequency modulation control circuit and method thereof |
| CN110391735A (en) * | 2018-04-16 | 2019-10-29 | 恩智浦有限公司 | PWM mode step-up switching regulator with programmable pulse frequency-hopping mode |
| CN110391735B (en) * | 2018-04-16 | 2023-10-17 | 恩智浦有限公司 | PWM mode boost switching regulator with programmable pulse hopping mode |
| TWI719511B (en) * | 2019-06-24 | 2021-02-21 | 國立中山大學 | Psm/pwm dual-mode buck converter |
| CN115360910A (en) * | 2022-07-06 | 2022-11-18 | 电子科技大学 | Pulse type energy power management and sensing circuit without external power supply |
| CN115360910B (en) * | 2022-07-06 | 2024-06-04 | 电子科技大学 | Pulse type energy power source management and sensing circuit without external power supply |
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Address after: 100085 unit C, building C, lin66, Zhufang Road, Qinghe, Haidian District, Beijing Patentee after: Beijing Xiaomi pinecone Electronic Co., Ltd Address before: 100085 Beijing city Haidian District Qinghe Shun Yip things Park Building 3 unit A Patentee before: BEIJING PINECONE ELECTRONICS Co.,Ltd. |