CN206195819U - Spatial information network link controlgear - Google Patents

Abstract

The utility model discloses a spatial information network link controlgear, include and carry out total the control unit of regulating and control to the data message, be connected with first interface board and second interface board on total the control unit respectively, total the control unit includes the network switching unit, be connected with physical layer chip, part interconnection bridging chip, flash memory ware, memory, connector and RS232 interface on the network switching unit. This device was applicable to between the star and communicate in star ground a plurality of working frequency band and multiple communication mode, in microwave communication, laser communication. The dynamic framing of key breakthrough technique, the application of link protocol in the space communication environment has effectively been solved based on the professional scheduling technique of data priority. The device is novel in design, circuit structure simply can be by communications field wide application.

Description

A kind of Information Network link controlling device

Technical field

The utility model is related to technical field of electronic communication, more particularly to a kind of Information Network link controlling device.

Background technology

Build the Information Network with communication capacity between star, can reduce communication system to ground infrastructure according to Lai Xing, meets the communication service demand of the whole world or zone user, further effectively alleviates the congestion condition in ground network, ensures Effective transmission of information and reliable delivery.But, nodal distance that Information Network has is remote, link error code is high, business kind The features such as class is more, high requirement is proposed to technologies such as link establishment, frame length design, service integrations.Network of the prior art Link controlling device do not take into full account satellite communication on transmission line in data volume is big and data type more than problem, deposit It is not sufficiently stable in link connection, and the cooperation of electronic unit is also not accurate enough, can cause data outage and loss of data Phenomenon.

Utility model content

The utility model discloses a kind of Information Network link controlling device, including data message is regulated and controled Master control unit, is connected to first interface plate and second interface plate on the master control unit；

The master control unit includes network exchange unit, and physical chip, portion are connected with the network exchange unit Part interconnection bridging chip, flash memories, memory, connector and RS232 interfaces；

The network exchange unit interconnects bridging chip and is connected again with cpci bus by network exchange unit and part With first interface plate data communication；The network exchange unit is connected by connector with second interface plate；Described first connects Oralia includes the first transceiver interface, Ethernet interface and network interface, and the second interface plate includes the second transceiver interface.

The network exchange unit uses fpga chip, its model XC7K325T.

The physical chip uses network PHY chip its model 88E1116R, part interconnection bridging chip to use PCI The bridging chip of its model of bridge joint mode PCI9056.

By adopting the above-described technical solution, a kind of Information Network link controlling device that the utility model is provided, Suitable between star and star the ground multiple working frequency range and communication that communicate, such as in microwave communication, laser communication.Emphasis is dashed forward Broken dynamic frame forming tech, the traffic scheduling technology based on data priority efficiently solve link protocol in space communication environment In application.The device is novel in design, circuit structure simply can be by communications field extensive use.

Brief description of the drawings

In order to illustrate more clearly of the embodiment of the present application or technical scheme of the prior art, below will be to embodiment or existing The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this Some embodiments described in application, for those of ordinary skill in the art, on the premise of not paying creative work, Other accompanying drawings can also be obtained according to these accompanying drawings.

Fig. 1 is structural representation of the present utility model；

Fig. 2 is FPGA overall logic annexation schematic diagrames in the utility model；

Fig. 3 is the protocol interface module schematic diagram of optical fiber 802.3 of FPGA in the utility model；

Fig. 4 is the 802.3 protocol interface module schematic diagrames of the RJ45 of FPGA in the utility model；

Fig. 5 is the protocol interface module schematic diagram of optical fiber 802.3 of FPGA in the utility model；

Fig. 6 is the 802.3 protocol interface module schematic diagrames of the RJ45 of FPGA in the utility model.

Specific embodiment

To make the technical solution of the utility model and advantage clearer, with reference to attached in the utility model embodiment Figure, clearly complete description is carried out to the technical scheme in the utility model embodiment：

A kind of Information Network link controlling device as shown in figs 1 to 6, it is main to include adjusting data message The master control unit of control, is connected to first interface plate and second interface plate on the master control unit.Master control unit exists Suitable first interface plate or second interface plate are selected with external world's electricity according to the characteristics of data when entering row data communication with outside Row data communication is entered on road.For example when data volume then selects second interface plate for gigabit type；If data volume is 10,000,000,000 number Carry out data transmission according to the interface then from first interface plate.

The master control unit includes network exchange unit 1, and physical chip is connected with the network exchange unit 1 11st, part interconnection bridging chip 12, flash memories 13, memory 14, connector 15 and RS232 interfaces 16；The network exchange list Unit 1 interconnects bridging chip 12 and is connected again logical with first interface plate data with cpci bus by physical chip 11 and part Letter；The network exchange unit 1 is connected by connector 15 with second interface plate；The first interface plate includes the first transmitting-receiving Interface, Ethernet interface and network interface, the second interface plate include the second transceiver interface.

Further, the network exchange unit 1 uses fpga chip, its model XC7K325T.Net based on FPGA Network crosspoint uses standard 3U cpci bus standards, takes two groove positions of 3U CPCI cabinets, and network number is carried out using FPGA Processed according to exchange, it is adaptable to high-performance, the signal processing system of big data quantity.The upper plug-in 256M × 64bit DDR3 storages of FPGA Device, for data buffer storage, the upper plug-in 1Gbit flash storages of FPGA, for program Solidification and user data, board front panel 8 road optical fiber are drawn, 4 road optical fiber (1,2,3,4) are 802.3 agreements, and 4 road optical fiber (A, B, C, D) are SNP agreements, board front panel Drawing serial ports is used to control to manage, and it is 802.3 agreements to draw 2 road optical fiber (6,7) by back card/back board, and 4 tunnels are drawn by back card/back board RJ45 network interfaces, agreement is 802.3 agreements, and two-way WiFi signal is drawn by back card/back board, and agreement is 802.11 agreements, and FPGA passes through Bridging chip connects cpci bus, it is possible to achieve the communication with CPCI main frames.

The Series FPGAs of Xilinx 7 are made up of three sections of brand-new FPGA product lines, and can meet should from high-volume cost-sensitive Low cost, miniaturization, super high-end connection bandwidth, logical capacity and signal handling capacity to very-high performance application etc. be Row system requirements.Used as programmable chip, 7 family devices are the solid foundation of target design platform, make designer from exploitation The incipient stage in cycle can be just concentrated on system innovation energy.The Series FPGAs of Xilinx 7 use the state-of-the-art property high of industry Energy, low-power consumption (HPL) 28nm dielectric layer/metal to-metal brake (HKMG) technologies high, shift systematic function onto unprecedented new peak Degree, I/O bandwidth is up to 2.4Tb/s, logic unit up to 2,000,000, and DSP performances reach 4.7TMACS, and power consumption with respect to former generation 50% is reduced for device, become substitution ASSP and ASIC may be programmed solution completely.The system uses Xilinx Company KintexTM-7 Series FPGA chip XC7K325T, it is main to complete high rate bioreactor function.Encapsulate selection is FFG900。

That wherein memory 14 is selected is DDR3, and what DDR3 was selected is the 256M*16bit chips of Hynix, 4 compositions 256M*64bit, the altogether memory space of 2G bytes.DDR3 controllers are completed by fpga logic, and controller uses the height of K7FPGA Performance BANK, it is possible to achieve the speed of 800MHz clocks.The theoretical bandwidth of whole DDR3 storages reaches 12.8GB/S (800MHz* Throughput rate 2*8B).

Flash memories 13 select Flash chip, are the 1Gbit NORFlash of Micron, highway width 16bit, support synchronous Access, it is possible to achieve the high speed data transfer with FPGA, be mainly used in the configuration data storage of FPGA, it is also possible to deposit number of users According to.

Part interconnection bridging chip 12 connects the bridging chip of its model of mode PCI9056 using PCI Bridge.The chip can be with Pci bus to the protocol conversion of local bus are realized, completes to extend the function of pci interface to FPGA.Support 32 data in PCI ends Width, the pci bus for supporting 33MHz or 66MHz, theoretical bandwidth is 66M*32bit=266MB/S, it is possible to achieve highest 166 The data transfer of megabyte per second.

Physical chip uses network PHY chip its model 88E1116R, and the device is the physical layer device of kilomega network, It is RGMII interfaces to be connected with the MAC in FPGA, externally supports the Ethernet of 1000BASE-T.External interface supports 10/100/ Tri- kinds of speed of 1000BASE-T, compatible 802.3.

That the power supply of the wherein power supply of the master control unit is selected is the micromodule power supply LTM4620A of Linear.The module It is doubleway output, the electric current output of maximum 13A is supported per road.System uses two power modules, is FPGA, DDR3, PCI Bridge joint, optic module etc. are powered.

The external gigabit network interface of first interface plate has optical Gigabit net and twisted-pair feeder gigabit network interface, and optical Gigabit net connects Mouth has selected two more common kilomega network module, is the FTLF8524P2 series and FTLF1424P2 series of finisar. FTLF8524P2 series is 850mm wavelength multi-mode optical modules, can support 1.063/2.125/4.25Gb/S Fiber Channel Agreement, it is also possible to support the 1000Base-X Ethernet protocols of 1.25G；FTLF8524P2 series is 1310mm wavelength single-mode optical modes Block, can support 1.063/2.125/4.25Gb/S Fiber Channel agreements, it is also possible to support the 1000Base-X of 1.25G with Too fidonetFido.

Overall logic annexation in FPGA is as shown in Fig. 2 be mainly used to realize the data of 802.3 agreements and SNP agreements Exchange and control.The data transmit-receive of 802.3 agreements is responsible in the management of 802.3 protocol interfaces, and SNP associations are responsible in the management of SNP protocol interfaces The data transmit-receive of view；Middle data exchange management module is responsible for for the protocol data on both sides entering row format conversion, according to management The switching path of the configuration of port carries out data exchange；Data buffer management module enters row buffering to network data, realizes network Error retransmitting function.

(1) protocol interface module of optical fiber 802.3

The protocol interface module of optical fiber 802.3 is realized that inside story logic realization MAC, high-speed transceiver realizes PHY, outward by FPGA Portion's link optic module realizes 1000BASE-SX data interconnection, and structure is as shown in Figure 3.Data flow is that optic module realizes photoelectricity Conversion, the serial signal of 1.5Gbps is given the high-speed transceiver module in FPGA；High-speed transceiver module realizes the work(of PHY Can, the serial signal of 1.5Gbps unstring to wait is processed, and is connected with MAC by internal gmii interface；MAC is connect by GMII Mouth connects the data of PHY, is processed, with the data that the output of fifo interface form is received, while supporting reverse link communication.

(2) 802.3 protocol interface modules of RJ45

802.3 protocol interface modules of RJ45 are realized that inside story logic realization MAC, PHY use external chip reality by FPGA It is existing, the data interconnection of 10/100/1000BASE-T is realized by transformer and RJ45 interfaces, structure is as shown in Figure 4.Data flow It is that electric signal is changed by transformer isolation, four groups of differential signals is given the PHY chip of outside, PHY chip is to differential signal Received and processed, be connected with the MAC of FPGA by RGMII interfaces；MAC in FPGA connects the number of PHY by RGMII interfaces According to, processed, export the data for receiving in fifo interface form；It is same to support reverse link communication.

(3) SNP protocol interface modules

The bottom layer treatment of SNP agreements is identical with 802.3 agreements of optical fiber interface.SNP protocol interface modules by FPGA realize, Inside story logic realization SNP dominates head, and high-speed transceiver realizes PHY, and external linkage optic module realizes that 1000BASE-SX data are mutual Connection, structure is as shown in Figure 5.

(4) 802.11 protocol interface modules of Wifi

WiFi interfaces realize protocol section by outside Wifi modules, are connected with the processor in FPGA by SPI mouthfuls, by Processor completes area protocol and data processing work, and data are delivered into Switching Module by FIFO, as shown in Figure 6.

(5) DDR storages control management

DDR storages part is realized caching network data, is retransmitted with the error with data, and each sendaisle has solid Fixed buffering area, all of packet is deposited according to the mode of FIFO, is transmitted in order, after confirmation sends successfully, is sent Next packet.

(6) data exchange management

Data exchange administrative section includes data exchange path clustering and Data Format Transform.Data exchange path clustering, Control information is received by serial ports by processor, data exchange path is determined, data exchange is realized by internal logic.Agreement turns Mold changing block only occurs in the interface of SNP agreements, when receiving or sending SNP protocol data bags, carries out protocol conversion.

The above, only the utility model preferably specific embodiment, but protection domain of the present utility model is not Be confined to this, any one skilled in the art in the technical scope that the utility model is disclosed, according to this practicality New technical scheme and its utility model design are subject to equivalent or change, should all cover in protection model of the present utility model Within enclosing.

Claims (3)

1. a kind of Information Network link controlling device, it is characterised in that：Including the master control regulated and controled to data message Unit, is connected to first interface plate and second interface plate on the master control unit；

The master control unit includes network exchange unit (1), and physical chip is connected with the network exchange unit (1) (11), part interconnects bridging chip (12), flash memories (13), memory (14), connector (15) and RS232 interfaces (16)；

The network exchange unit (1) interconnects bridging chip (12) and is connected with cpci bus by physical chip (11) and part Connect again with first interface plate data communication；The network exchange unit (1) is connected by connector (15) with second interface plate； The first interface plate includes the first transceiver interface, Ethernet interface and network interface, and the second interface plate includes that the second transmitting-receiving connects Mouthful.

2. a kind of Information Network link controlling device according to claim 1, is further characterized in that：The network is handed over Change unit (1) and use fpga chip, its model XC7K325T.

3. a kind of Information Network link controlling device according to claim 1, is further characterized in that：The physical layer Chip uses network PHY chip its model 88E1116R, part to interconnect bridging chip (12) and connect mode its model using PCI Bridge It is the bridging chip of PCI9056.