CN206116403U - Optimize super knot semiconductor device of switching characteristic - Google Patents
Optimize super knot semiconductor device of switching characteristic Download PDFInfo
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- CN206116403U CN206116403U CN201620945153.8U CN201620945153U CN206116403U CN 206116403 U CN206116403 U CN 206116403U CN 201620945153 U CN201620945153 U CN 201620945153U CN 206116403 U CN206116403 U CN 206116403U
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Abstract
The utility model relates to an optimize super knot semiconductor device of switching characteristic device, its characterized in that: integrated electric capacity district is introduced on the surface that surpasses knot semiconductor device in the trench gate type, and integrated electric capacity district is including bars capacitor plate, first insulation dielectric layer and the 2nd conductivity type tagma, in integrated electric capacity district cross -section orientation, the first insulation dielectric layer is the 2nd conductivity type tagma with semiconductor substrate adjacent area, be equipped with bars capacitor plate on the first insulation dielectric layer and border on, bars capacitor plate and gate electrode electrical property intercommunication, the utility model discloses introduces at integrated electric capacity district, can effectual increase device input capacitance ciss, and device feedback capacitance crss, output capacitance coss is unchangeable, thereby reduce the feedback, the input capacitance compares crssCiss, and then improve the switching characteristic of device, reduce opening and closing process's dVdt, and this device manufacturing method and current semiconductor compatible, under the prerequisite that does not increase the technology step, can accomplish the preparation in integrated electric capacity district, consequently, do not increase any cost.
Description
Technical field
The utility model is related to a kind of super-junction semiconductor device and manufacture method, and especially a kind of optimization switching characteristic is super
Junction-semiconductor device.
Background technology
In mesohigh power semiconductor field, super-junction structure（Super Junction）It has been widely adopted, it is right
Than conventional power MOSFET element, super-junction structure MOSFET element can obtain the pressure folding with conducting resistance of more excellent device
Middle relation.Super-junction structure is formed in the drift region of semiconductor devices, and being formed at the super-junction structure stated in drift region includes that N is conductive
Type post（N posts）With P conductivity type columns（P posts）, N posts replace multiple P-N posts for being provided adjacent to P posts to forming superjunction knot
Structure.N posts have N conductive type impurities, and P posts have P conductive type impurities, and the impurity level of N posts keeps one with the impurity level of P posts
Cause.When the MOSFET element with super-junction structure is ended, N posts in super-junction structure and P posts difference are depleted, and depletion layer is from every
The P-N junction interface of individual N posts and P intercolumniations extends, and because the impurity level in the impurity level in N posts and P posts is equal, therefore depletion layer prolongs
Stretch and completely depleted N posts and P posts, so as to supports is pressure；When break-over of device, due to the resistance of superjunction devices drift region
Rate is lower, so the conducting resistance of superjunction devices can be greatly lowered compared with commonplace components, the electric conduction of super-junction MOSFET device
The more common VDMOS device of resistance can reduce by 70% or so.
During devices switch, because the P posts and N posts in super-junction structure only needs relatively low drain electrode pressure（Vds）Just
Can respectively exhaust, cause the more common VDMOS of dV/dt during devices switch substantially bigger than normal.Further, since super node MOSFET chip
Area is little by 50% or so compared with the common VDMOS of same specification, corresponding parasitic capacitance（Such as Ciss）Also accordingly to diminish, further add
The increase of dV/dt in acute switching process.In actual applications, the increase of dV/dt can cause higher direction due to voltage spikes, increase
Adding system electromagnetic interference EMI, it is serious in the case of even result in device and burn.
It is the size for reducing dV/dt during devices switch in the practical application of super node MOSFET, improves devices switch
Characteristic, typically can adopt increases the modes such as discrete resistance, electric capacity, but the increasing of these peripheral devices in super node MOSFET periphery
Plus, the rising of system cost can be caused, while can also reduce system reliability.
As can be seen here, a kind of device architecture of optimization switching characteristic, and the superjunction mutually compatible with existing manufacturing process is partly led
Body device architecture and manufacture method are very important.
The content of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art, there is provided a kind of superjunction of optimization switching characteristic
Semiconductor devices, the device making method is compatible with existing semiconductor technology, and the introducing in integrated capacitance area can effectively increase
Plus device Ciss, feedback, input capacitance are reduced than Crss/Ciss, and then improve the switching characteristic of device, reduce switching process
dV/dt。
To realize above technical purpose, the technical solution of the utility model is：A kind of superjunction of optimization switching characteristic is partly led
Body device, including cellular region and terminal protection area, the cellular region is located at the center of device, and the terminal protection area is looped around
Around the cellular region, the cellular region includes semiconductor substrate, and the semiconductor substrate includes the first conductivity type substrate
And in the first conductivity type substrate and the first adjacent conduction type drift region, the first conduction type drift region it is upper
Surface is the first interarea of semiconductor substrate, and the lower surface of first conductivity type substrate is led for the second of semiconductor substrate
Face；Be provided with some super-junction structures in the first conduction type drift region, the super-junction structure by the first conductivity type columns and
Second conductivity type columns are arranged alternately and form, and first conductivity type columns and the second conductivity type columns are pointed to along the first interarea
The direction of the second interarea extends；The second conductivity type body region is provided with the second conductivity type columns in the first conductive drift region,
And second conductivity type body region in the first conductive drift region, be provided with the first conduction type in second conductivity type body region
Source region, the first conduction type source region is arranged on the both sides of the second conductivity type body region, second conductivity type body region it
Between be provided with the first conduction type source region in gate groove, and the second conductivity type body region and adjoin with gate groove, in the gate groove
Gate oxide and gate electrode are provided with, the second insulating medium layer is coated with gate groove, the gate electrode is by gate oxide and second
Insulating medium layer is wrapped up；Source metal, the source metal and the second conduction type are set on the first interarea of semiconductor substrate
Body area, the first conduction type source region Ohmic contact, arrange drain metal, the drain metal under the second interarea of semiconductor substrate
With the first conductivity type substrate Ohmic contact, it is characterised in that：It is integrated several to be provided with the first interarea of semiconductor substrate
Capacitive region, the integrated capacitance area includes gate capacitance plate, the first insulating medium layer and the second conductivity type body region；In integrated electricity
Hold in area's cross-wise direction, the first insulating medium layer is the second conductivity type body region with semiconductor substrate adjacent area；Described
One insulating medium layer is provided with gate capacitance plate and adjacent, the gate capacitance plate and gate electrode electrical communication.
Further, for N-type super-junction semiconductor device, first conduction type is that N-type is conductive, and described second is conductive
Type is P-type conduction；For p-type super-junction semiconductor device, first conduction type is P-type conduction, second conductive-type
Type is that N-type is conductive.
Further, isolated by the second insulating medium layer between the source metal and gate capacitance plate, gate electrode.
Further, the gate capacitance plate and gate electrode electrical communication be interdigital capacitors plate can direct phase with gate electrode
Even, or it is connected with gate electrode by metal.
Further, the super-junction semiconductor device is MOS device or IGBT device.
Further, the material of second insulating medium layer is SiO2Or BPSG.
From the above, it can be seen that the beneficial effects of the utility model are：
1）Increase integrated capacitance plot structure in Superjunction semiconductor device structure, which increase the input capacitance of device,
And then reduce the value of dV/dt during devices switch, while the output capacitance and feedback capacitance of device and unaffected；
2）The utility model devices switch speed does not increase the Muller electric capacity of device while reduction, therefore can be effective
The switching characteristic for improving device, reduce the dV/dt of switching process, reduce impact of the device to system EMI；
3）The formation process in the utility model integrated capacitance area is completely compatible with the manufacturing process of existing semiconductor devices；
4）The utility model completes the manufacture in integrated capacitance area in the case of not increasing any processing step, therefore does not increase
Plus any cost.
5）In high tension apparatus, the impact of the introducing in integrated capacitance area 03 to device on-resistance can be ignored substantially.
Description of the drawings
Accompanying drawing 1 is the utility model embodiment plan view from above.
Accompanying drawing 2 is cross-sectional view of the utility model embodiment accompanying drawing 1 along A-A '.
Accompanying drawing 3 is cross-sectional view of the utility model embodiment accompanying drawing 1 along B-B '.
Accompanying drawing 4 is cross-sectional view of the utility model embodiment accompanying drawing 1 along C-C '.
Accompanying drawing 5～10 is specific implementation step edge of the utility model by taking N-type trench gate super-junction semiconductor device as an example
The cross section structure diagram of C-C ', wherein：
Accompanying drawing 5 is the cross section structure diagram for forming semiconductor substrate.
Accompanying drawing 6 is the cross section structure diagram for forming deep trench.
Accompanying drawing 7 is the cross section structure diagram for forming super-junction structure.
Accompanying drawing 8 is the cross section structure diagram for forming the second conductivity type body region.
Accompanying drawing 9 is the cross section structure diagram for forming gate groove, the first insulating medium layer and gate oxide.
Accompanying drawing 10 is the cross section structure diagram of the gate capacitance plate for forming gate electrode and integrated capacitance area.
Description of reference numerals：001-the first interarea；002-the second interarea；01-the first conduction type drift region；02—
First conductivity type substrate；03-integrated capacitance area；04-gate groove；11-the first conductivity type columns；12-the second conductive-type
Type type post；13-second generation conductivity type body region；14-the first insulating medium layer；15-gate electrode；16-gate capacitance plate；
17 --- the first conduction type source region；18-the second insulating medium layer；19-gate oxide；20-source metal；21-drain electrode
Metal；1-hard mask layer；2-deep trench.
Specific embodiment
With reference to concrete drawings and Examples, the utility model is described in further detail.
As shown in accompanying drawing 1 ~ 4, a kind of optimization switching characteristic by taking N-type trench gate super-junction semiconductor device as an example it is super
Junction-semiconductor device, including cellular region and terminal protection area, the cellular region is located at the center of device, the terminal protection area
It is looped around around the cellular region, the cellular region includes semiconductor substrate, the semiconductor substrate includes the first conductive-type
Type substrate 02 and in the first conductivity type substrate 02 and the first adjacent conduction type drift region 01, first conductive-type
The upper surface of type drift region 01 is the first interarea 001 of semiconductor substrate, and the lower surface of first conductivity type substrate 02 is
Second interarea 002 of semiconductor substrate；Some super-junction structures, the superjunction are provided with the first conduction type drift region 01
Structure is arranged alternately and is formed by the first conductivity type columns 11 and the second conductivity type columns 12, first conductivity type columns 11 and
Two conductivity type columns 12 extend along the direction that the first interarea 001 points to the second interarea 002；In the first conductive drift region 01
Second conductivity type columns 12 are provided with the second conductivity type body region 13, and the second conductivity type body region 13 located at the first conductive drift
In area 01, in second conductivity type body region 13 the first conduction type source region 17, the first conduction type source region 17 are provided with
The both sides of the second conductivity type body region 13 are arranged on, gate groove 04, and second are provided between second conductivity type body region 13
The first conduction type source region 17 in conductivity type body region 13 is adjoined with gate groove 04, and in the gate groove 04 gate oxide is provided with
19 and gate electrode 15, the second insulating medium layer 18 is coated with gate groove 04, the gate electrode 15 is by gate oxide 19 and second
Insulating medium layer 18 is wrapped up；Source metal 20, the source metal 20 and second are set on first interarea 001 of semiconductor substrate
Conductivity type body region 13, the Ohmic contact of the first conduction type source region 17, the source metal 20 and gate capacitance plate 16, gate electrode 15
Between isolated by the second insulating medium layer 18,002 time setting drain metal 21 of the second interarea of semiconductor substrate, the drain electrode
The Ohmic contact of 21 and first conductivity type substrate of metal 02, it is characterised in that：It is provided with the first interarea 001 of semiconductor substrate
Several integrated capacitance areas 03, the integrated capacitance area 03 includes that gate capacitance plate 16, the first insulating medium layer 14 and second are conductive
Type body region 13；In the cross-wise direction of integrated capacitance area 03, the first insulating medium layer 14 is with semiconductor substrate adjacent area
Second conductivity type body region 13；First insulating medium layer 14 is provided with gate capacitance plate 16 and adjacent, the gate capacitance plate 16
With the electrical communication of gate electrode 15, the electrical communication is that interdigital capacitors plate 16 directly can be connected with gate electrode 15, or by gold
Category is connected with gate electrode 16.
For N-type super-junction semiconductor device, first conduction type is that N-type is conductive, and second conduction type is p-type
It is conductive；For p-type super-junction semiconductor device, first conduction type are P-type conduction, second conduction type is led for N-type
Electricity.The super-junction semiconductor device is MOS device or IGBT device.
On device top plan view direction, at least provided with more than one integrated capacitance area in the super-junction semiconductor device
03, the quantity in integrated capacitance area 03 is arranged according to the size of the actually required input capacitance of device, integrated capacitance area 03 can be uniform
Be distributed in device cellular region, or combine the specific region that is distributed in device；In device cross-wise direction,
The first insulating medium layer 14 in any one place's integrated capacitance area 03 is the second conductive-type with the adjacent area of semiconductor substrate
Xing Ti areas 13, the first insulating medium layer 14 in any one place's integrated capacitance area 03 is not direct with the first conduction type drift region 01
It is adjacent.
The present embodiment corresponds to trench gate Superjunction semiconductor device structure, it is notable that the utility model is also fitted
For planar gate device power MOSFET structure, or the IGBT semiconductor device beyond MOSFET element.
As shown in accompanying drawing 5～10, the N-type trench gate superjunction half of the optimization switching characteristic shown in above-described embodiment accompanying drawing 4
Conductor device can be prepared by following processing steps, and specifically, manufacture method comprises the steps：
As shown in Figure 5, step one. semiconductor substrate is provided, the semiconductor substrate is served as a contrast including the first conduction type
Bottom 02 and the first conduction type drift region 01 being grown in the first conductivity type substrate 02, the first conduction type drift region
01 upper surface is the first interarea 001, and the lower surface of the first conductivity type substrate 02 is the second interarea 002；
As shown in Figure 6, step 2. hard mask layer 1, the material of the hard mask layer 1 are deposited on the first interarea 001
For LPTEOS or SiO2Or Si3N4, hard mask layer 1 is optionally etched, multiple hard mask windows for etching groove are formed,
By sheltering for hard mask layer 1, performed etching using anisotropic etching method on the surface of the first interarea 001, led first
Multiple deep trench 2 are formed in electric type drift region 01, the deep trench 2 is from the first interarea 001 to the first conduction type drift region
01 extends, and the material of the hard mask layer 1 is LPTEOS or SiO2Or Si3N4；
As shown in Figure 7, step 3. the second conductivity type material of filling in deep trench 2, then remove hard mask layer
1, the first conductivity type columns 11 and the alternate superjunction knot of the second conductivity type columns 12 are formed in the first conduction type drift region 01
Structure；
As shown in Figure 8, step 4. blocking by reticle, select on the first interarea 001 of semiconductor substrate
Property the second conductive type ion of injection, then push away trap, form the second conductivity type body region 13；
As shown in Figure 9, step 5. the first interarea 001 of the semiconductor substrate between the second conductivity type body region 13
On perform etching, form gate groove 04, then grow layer of oxide layer, gate oxide 19 is formed in the gate groove 04, second
The first insulating medium layer 14 is formed on conductivity type body region 13, the insulating medium layer 14 of the gate oxide 19 and first can be simultaneously
Formed；
As shown in Figure 10, step 6. one layer of conductive semiconductor layer is deposited on the first interarea 001, the conduction is partly led
Body layer is DOPOS doped polycrystalline silicon, and blocking by reticle carries out selective etch to conductive semiconductor layer, retain in gate groove 04
Conductive semiconductor layer formed gate electrode 15；The conductive semiconductor layer retained on the first insulating medium layer 14 forms integrated capacitance area
03 gate capacitance plate 16, the gate electrode 15 and gate capacitance plate 16 can be formed simultaneously；Step 7. blocking by reticle,
The first conductive type ion of injection, forms the first conduction type source region 17 in the second conductivity type body region 13；
As shown in Figure 4, step 8. in surface deposition insulating medium layer, form the second insulating medium layer 18, described the
The material of two insulating medium layers 18 is SiO2Or BPSG, blocking by reticle, the second insulating medium layer 18 is performed etching
Source contact openings are formed on perforate, the first conduction type source region 17 and the second conductivity type body region 13, is filled out in source contact openings
Metal is filled, source metal 20 is formed, metal is deposited on the second interarea 002 of semiconductor substrate, form drain metal 21.
The characteristics of the utility model, is, due to introducing integrated capacitance area 03, can effectively increase the input of device
Electric capacity Ciss, and the increase of input capacitance Ciss is directly proportional to the area in integrated capacitance area 03, by increase or can reduce
The area in integrated capacitance area 03 carrys out the value of precise control input capacitance Ciss, although input capacitance Ciss of device increased, but
Output capacitance Coss and feedback capacity Crss value do not change, therefore can effectively reduce feedback, input capacitance ratio
Crss/Ciss, and then improve the switching characteristic of device, the dV/dt of switching process is reduced, reduce humorous during devices switch
Shake, impact of the device to system EMI is reduced in the case where peripheral circuit need not be adjusted；The technique that the utility model is adopted
It is mutually compatible with existing semiconductor technology, and be not required to increase additional technical steps, you can complete the preparation in device integrated capacitance area 03；
Simultaneously in high tension apparatus, because channel resistance is only accounted within the 5% of total conducting resistance, therefore the presence pair in integrated capacitance area 03
The impact of device on-resistance can be ignored substantially.
The utility model and embodiments thereof are described above, the description does not have restricted, shown in accompanying drawing
Also it is one of embodiment of the present utility model, actual structure is not limited thereto.If generally speaking this area is general
Logical technical staff is enlightened by it, in the case where objective is created without departing from the utility model, is designed and this without creative
The similar frame mode of technical scheme and embodiment, all should belong to protection domain of the present utility model.
Claims (6)
1. a kind of super-junction semiconductor device device of optimization switching characteristic, including cellular region and terminal protection area, the cellular region
Positioned at the center of device, the terminal protection area is looped around around the cellular region, and the cellular region includes semiconductor-based
Plate, the semiconductor substrate includes the first conductivity type substrate（02）And positioned at the first conductivity type substrate（02）Upper and adjacent
First conduction type drift region（01）, the first conduction type drift region（01）Upper surface for semiconductor substrate first master
Face（001）, first conductivity type substrate（02）Lower surface for semiconductor substrate the second interarea（002）；Described first
Conduction type drift region（01）Some super-junction structures are inside provided with, the super-junction structure is by the first conductivity type columns（11）With second
Conductivity type columns（12）It is arranged alternately and forms, first conductivity type columns（11）With the second conductivity type columns（12）Along first
Interarea（001）Point to the second interarea（002）Direction extend；In the first conductive drift region（01）The second interior conductivity type columns
（12）It is provided with the second conductivity type body region（13）, and the second conductivity type body region（13）Located at the first conductive drift region（01）
It is interior, second conductivity type body region（13）Inside it is provided with the first conduction type source region（17）, the first conduction type source region
（17）It is arranged on the second conductivity type body region（13）Both sides, second conductivity type body region（13）Between be provided with gate groove
（04）, and the second conductivity type body region（13）The first interior conduction type source region（17）With gate groove（04）It is adjacent, the grid ditch
Groove（04）Inside it is provided with gate oxide（19）And gate electrode（15）, gate groove（04）On be coated with the second insulating medium layer（18）, institute
State gate electrode（15）By gate oxide（19）With the second insulating medium layer（18）Parcel；First interarea of semiconductor substrate（001）
Upper setting source metal（20）, the source metal（20）With the second conductivity type body region（13）, the first conduction type source region
（17）Ohmic contact, the second interarea of semiconductor substrate（002）Lower setting drain metal（21）, the drain metal（21）With
One conductivity type substrate（02）Ohmic contact, it is characterised in that：In the first interarea of semiconductor substrate（001）It is provided with several
Integrated capacitance area（03）, the integrated capacitance area（03）Including gate capacitance plate（16）, the first insulating medium layer（14）And second lead
Electric type body region（13）；In integrated capacitance area（03）In cross-wise direction, the first insulating medium layer（14）It is adjacent with semiconductor substrate
Region is the second conductivity type body region（13）；First insulating medium layer（14）It is provided with gate capacitance plate（16）And it is adjacent；
The gate capacitance plate（16）With gate electrode（15）Electrical communication.
2. it is according to claim 1 it is a kind of optimization switching characteristic super-junction semiconductor device device, it is characterised in that：For
N-type super-junction semiconductor device, first conduction type is that N-type is conductive, and second conduction type is P-type conduction；For p-type
Super-junction semiconductor device, first conduction type is P-type conduction, and second conduction type is that N-type is conductive.
3. it is according to claim 1 it is a kind of optimization switching characteristic super-junction semiconductor device device, it is characterised in that：It is described
Source metal（20）With gate capacitance plate（16）, gate electrode（15）Between pass through the second insulating medium layer（18）Isolation.
4. it is according to claim 1 it is a kind of optimization switching characteristic super-junction semiconductor device device, it is characterised in that：It is described
Gate capacitance plate（16）With gate electrode（15）Electrical communication is interdigital capacitors plate（16）With gate electrode（15）Can be joined directly together, or it is logical
Cross metal and gate electrode（16）It is connected.
5. it is according to claim 1 it is a kind of optimization switching characteristic super-junction semiconductor device device, it is characterised in that：It is described
Super-junction semiconductor device is MOS device or IGBT device.
6. a kind of super-junction semiconductor device device of optimization switching characteristic according to claim 1, is characterized in that, described the
Two insulating medium layers（18）Material be SiO2Or BPSG.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620945153.8U CN206116403U (en) | 2016-08-25 | 2016-08-25 | Optimize super knot semiconductor device of switching characteristic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620945153.8U CN206116403U (en) | 2016-08-25 | 2016-08-25 | Optimize super knot semiconductor device of switching characteristic |
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| Publication Number | Publication Date |
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| CN206116403U true CN206116403U (en) | 2017-04-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201620945153.8U Expired - Fee Related CN206116403U (en) | 2016-08-25 | 2016-08-25 | Optimize super knot semiconductor device of switching characteristic |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158927A (en) * | 2016-08-25 | 2016-11-23 | 无锡新洁能股份有限公司 | A kind of super-junction semiconductor device optimizing switching characteristic and manufacture method |
| CN112909075A (en) * | 2021-01-28 | 2021-06-04 | 滁州华瑞微电子科技有限公司 | Trench MOSFET with charge balance structure and manufacturing method thereof |
-
2016
- 2016-08-25 CN CN201620945153.8U patent/CN206116403U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158927A (en) * | 2016-08-25 | 2016-11-23 | 无锡新洁能股份有限公司 | A kind of super-junction semiconductor device optimizing switching characteristic and manufacture method |
| CN112909075A (en) * | 2021-01-28 | 2021-06-04 | 滁州华瑞微电子科技有限公司 | Trench MOSFET with charge balance structure and manufacturing method thereof |
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Granted publication date: 20170419 Termination date: 20200825 |