CN206100257U - Compatible processing apparatus of data signal and analog signal - Google Patents
Compatible processing apparatus of data signal and analog signal Download PDFInfo
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- CN206100257U CN206100257U CN201620845069.9U CN201620845069U CN206100257U CN 206100257 U CN206100257 U CN 206100257U CN 201620845069 U CN201620845069 U CN 201620845069U CN 206100257 U CN206100257 U CN 206100257U
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Abstract
The application discloses compatible processing apparatus of data signal and analog signal for realizing the compatible of data signal and analog signal and handling, reduce the influence that data signal and analog signal received the other side processing line, improve image quality, the device includes: a multiplex signal port that is used for multiplexing access data signal and analog signal and exports, be used for handling the data signal and the analog signal of the output of multiplex signal port respectively to data processor's digital signal processor and analog signal processing ware are given in output, be used for handling and exporting the received signal to and confirm that incoming signal was data signal or analog signal present, and when confirming that current incoming signal is data signal, output control signal gives the analog signal treater, controls the analog signal treater and closes, and when confirming that current incoming signal is analog signal, output control signal gives the data signal treater, controls the data signal 4 that the data signal treater was closed.
Description
Technical field
The application is related to signal processing technology field, more particularly to a kind of data signal and analog signal compatible processing dress
Put.
Background technology
In security protection industry, what current head end video collecting device was adopted is mostly digital camera and analog video camera,
Digital camera output is data signal (such as digital serial interface (Serial Digital Interface, SDI) letter
Number), the image time delay of collection is low, quality is high, but digital camera cost is higher, and analog video camera output is simulation letter
Number, comparatively quality is low for the image of collection, but its low cost, and in practical application scene, client is wished in some emphasis fields
Scape uses high-definition digital video camera, to improve picture quality, reduces time delay, and other secondary scene clients wish to continue to use mould
Intend video camera, to reduce the cost of whole scheme.
And because the transformat of the vision signal of both video cameras is different, in order to be adapted to both shootings
Machine, rear end equipment is accomplished by the equipment that can process data signal and the equipment that can process analog signal, and at present on the market
Or rear end equipment only support process data signal, or only support process analog signal, or equipment some interfaces consolidate
Fixed to support to process data signal, some interfaces are fixed and support to process analog signal, and data signal and analog signal usually separate
Independently processed.
Also, with the development of security protection industry, the requirement more and more higher to video definition, if data signal and simulation
Signal is affected by other side's process circuit, it will affect video image quality.
To sum up, data signal and analog signal are that process is separated and independently performed in prior art, it is impossible to compatible processing, and
And, if data signal and analog signal are affected by other side's process circuit, it will affect video image quality.
Utility model content
The embodiment of the present application provides a kind of data signal and analog signal compatible processing device, to realize data signal
With the compatible processing of analog signal, reduce data signal and analog signal is affected by other side's process circuit, improves image matter
Amount.
A kind of data signal and analog signal compatible processing device that the embodiment of the present application is provided includes：Multiplexed signals end
Mouth, digital signal processor, analogue signal processor and data processor；Wherein,
The multiplexed signals port is used to be multiplexed incoming digital signal and analog signal and export；
The digital signal processor is used to process the data signal of the multiplexed signals port output, and exports to described
Data processor；
The analogue signal processor is used to process the analog signal of the multiplexed signals port output, and exports to described
Data processor；
The data processor is used for the signal to receiving and is processed and exported, and determines that current input signal is
Data signal or analog signal, when it is determined that current input signal is data signal, output control signal gives the analog signal
Processor, controls the analogue signal processor and closes, when it is determined that current input signal is analog signal, output control signal
To the digital signal processor, control the digital signal processor and close.
The technical scheme that the embodiment of the present application is provided, by multiplexed signals multiplexed port incoming digital signal and simulation letter
Number, and two-way process circuit is provided with processing data signal and analog signal respectively, realize data signal and analog signal
Compatible processing, also, data processor when it is determined that current input signal be data signal when, output control signal to simulation letter
Number processor, controls the analogue signal processor and closes, when it is determined that current input signal is analog signal, output control signal
To digital signal processor, control the digital signal processor and close, so can reduce data signal and analog signal is subject to
The impact of other side's process circuit, so as to improve picture quality.
It is preferred that the digital signal processor includes：Data signal conversion for being decoded to data signal is single
Unit；The first controlling bus are connected between the data signal converting unit and the data processor；
The data processor is inquired about in the data signal converting unit for characterizing by first controlling bus
The state value of the data signal converting unit working condition, determines whether current input signal is digital letter according to the state value
Number；And when it is determined that current input signal is analog signal, by the first controlling bus output control signal to described
Data signal converting unit, controls the data signal converting unit and closes.
It is preferred that the digital signal processor also includes：
It is serially connected between the multiplexed signals port and the data signal converting unit, basis signal transmission direction is successively
The connected data signal capacitance-resistance match circuit for carrying out impedance matching to data signal and for carrying out letter to data signal
Number recover EQ balanced devices.
It is preferred that the digital signal processor also includes：It is serially connected in the multiplexed signals port and the data signal
High-frequency inductor between capacitance-resistance match circuit.
It is preferred that the analogue signal processor includes：For the analog-digital converter decoded to analog signal；It is described
The second controlling bus are connected between analog-digital converter and the data processor；
The data processor is inquired about in the analog-digital converter for characterizing the mould by second controlling bus
The state value of number converter working condition, determines whether current input signal is analog signal according to the state value；And when true
Determine current input signal for data signal when, by the second controlling bus output control signal give the analog-digital converter,
Control the analog-digital converter to close.
It is preferred that the analogue signal processor also includes：It is serially connected in the multiplexed signals port and the analog-to-digital conversion
The analog signal capacitance-resistance match circuit for carrying out impedance matching to analog signal between device.
It is preferred that the analogue signal processor also includes：It is serially connected in the multiplexed signals port and the analog signal
Data signal isolated location between capacitance-resistance match circuit；Wherein, the data signal isolated location is used to isolate the simulation
Impact of the signal processor to data signal, and the analog signal of the multiplexed signals port output is received, and export to institute
State analog signal capacitance-resistance match circuit；
The data processor is additionally operable to when it is determined that current input signal is data signal, exports enable signal to described
Data signal isolated location, controls the data signal isolated location and closes.
It is preferred that the data signal isolated location includes the analog signal buffer with enabling；Wherein, the simulation letter
Number buffer is used to isolating impact of the analogue signal processor to data signal, and to receive the multiplexed signals port defeated
The analog signal for going out, and export to the analog signal capacitance-resistance match circuit；At the analog signal buffer and the data
The first enable control line is connected between reason device；
The data processor is made when it is determined that current input signal is data signal by the first enable control line output
Energy signal gives the analog signal buffer, controls the analog signal buffer and closes.
By the device, when it is determined that current input signal is data signal, analog signal buffer is closed, such that it is able to
Turn off analog signal processing path, and then reduce data signal is affected by analog signal processing circuit, improves digital video figure
As quality.
It is preferred that the data signal isolated location also includes the power supply unit with enabling；Wherein, the power supply supply
Device is used to be powered to the analog signal buffer；Second is connected between the power supply unit and the data processor makes
Can control line；
The data processor is made when it is determined that current input signal is data signal by the second enable control line output
Energy signal gives the power supply unit, controls the power supply unit and closes.
By the device, when it is determined that current input signal is data signal, power supply unit is also turn off, does not give simulation letter
Number buffer is powered so that analog signal buffer shut-off more thoroughly, is led to such that it is able to preferably turn off analog signal processing
Road, and then further reduction data signal is affected by analog signal processing circuit, improves digital video image quality.
It is preferred that the device also includes：Protection module；Wherein, the protection module is connected to the Digital Signal Processing
Between device and the signal input part and ground of the analogue signal processor.
It is preferred that the multiplexed signals port is coaxial connector.
It is preferred that the data processor is codec.
Description of the drawings
The structural representation of a kind of data signal and analog signal compatible processing device that Fig. 1 is provided for the embodiment of the present application
Figure；
The structural representation of the first digital signal processor that Fig. 2 is provided for the embodiment of the present application；
The structural representation of second digital signal processor that Fig. 3 is provided for the embodiment of the present application；
The structural representation of the third digital signal processor that Fig. 4 is provided for the embodiment of the present application；
The structural representation of the first analogue signal processor that Fig. 5 is provided for the embodiment of the present application；
The structural representation of second analogue signal processor that Fig. 6 is provided for the embodiment of the present application；
The structural representation of the third analogue signal processor that Fig. 7 is provided for the embodiment of the present application；
The structural representation of the first data signal isolated location that Fig. 8 is provided for the embodiment of the present application；
The structural representation of second data signal isolated location that Fig. 9 is provided for the embodiment of the present application；
Another kind of data signal and the structure of analog signal compatible processing device that Figure 10 is provided for the embodiment of the present application is shown
It is intended to；
The data signal and the concrete structure of analog signal compatible processing device that Figure 11 is provided for the embodiment of the present application is illustrated
Figure.
Specific embodiment
The embodiment of the present application provides a kind of data signal and analog signal compatible processing device, to realize data signal
With the compatible processing of analog signal, reduce data signal and analog signal is affected by other side's process circuit, improves image matter
Amount.
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only some embodiments of the present application, rather than the embodiment of whole.It is based on
Embodiment in the application, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of the application protection.
It should be noted that the arrow in the accompanying drawing in the embodiment of the present application represents the flow direction of signal.
As shown in figure 1, a kind of data signal and analog signal compatible processing device of the embodiment of the present application offer, including：
Multiplexed signals port 1, digital signal processor 2, analogue signal processor 3 and data processor 4.
Wherein, multiplexed signals port 1 is used to be multiplexed incoming digital signal and analog signal and export；The multiplexed signals port
1 for example can be coaxial connector (Bayonet Nut Connector, BNC)；
Digital signal processor 2 is used to process the data signal of the output of multiplexed signals port 1, and exports to data processor
4；
Analogue signal processor 3 is used to process the analog signal of the output of multiplexed signals port 1, and exports to data processor
4；
Data processor 4 is used for the signal to receiving and is processed and exported, and determines that current input signal is number
Word signal or analog signal, when it is determined that current input signal is data signal, output control signal is to analogue signal processor
3, control analogue signal processor 3 is closed, and when it is determined that current input signal is analog signal, output control signal gives numeral letter
Number processor 2, control digital signal processor 2 is closed；The data processor 4 for example can be codec.
In the embodiment of the present application, the data signal of digital camera output and the analog signal of analog video camera output can
To be multiplexed the data signal and the analog signal compatible processing device that access that the embodiment of the present application is provided by multiplexed signals port 1,
Then determine that current input signal is data signal or analog signal by data processor 4, when it is determined that current input signal is number
During word signal, output control signal is closed to analogue signal processor 3, control analogue signal processor 3, digital signal processor
2 process the data signal of the output of multiplexed signals port 1, and export to data processor 4,4 pairs of letters for receiving of data processor
Number processed and exported, when it is determined that current input signal is analog signal, output control signal is to digital signal processor
2, control digital signal processor 2 is closed, and analogue signal processor 3 processes the analog signal of the output of multiplexed signals port 1, and defeated
Go out to data processor 4,4 pairs of signals for receiving of data processor are processed and exported, it follows that the embodiment of the present application
The technical scheme of offer processes respectively data signal and analog signal by arranging two-way process circuit, realizes data signal
With the compatible processing of analog signal, also, when it is determined that current input signal be data signal when, close analogue signal processor,
When it is determined that current input signal is analog signal, digital signal processor is closed, can so reduce data signal and simulation
Signal is affected by other side's process circuit, so as to improve picture quality.
Specifically, referring to Fig. 2, digital signal processor 2 (dotted line frame is represented in Fig. 2) includes：Data signal converting unit
24；The data signal converting unit 24 is decoded (for example to the data signal that multiplexed signals port exports：Serial digital is believed
Number be converted to standard BT656 or BT1120 digital parallel signals), and by decoded signal output to data processor 4, its
In, data signal converting unit 24 for example can be field programmable gate array (FPGA) data signal converting unit.
As shown in Fig. 2 being also associated with the first controlling bus (example between data signal converting unit 24 and data processor 4
Such as：IC bus (Inter-Integrated Circuit, IIC))；Data processor 4 passes through first controlling bus
It is used to characterize the state value of the working condition of data signal converting unit 24 in enquiring digital signal conversion unit 24, according to the state
Value determines whether current input signal is data signal；And when it is determined that current input signal is analog signal, by this
One controlling bus output control signal is closed and (for example may be used to data signal converting unit 24, control data signal converting unit 24
To close vision signal output (Video Output, VO) of data signal converting unit 24).
Wherein, data processor 4 characterizes number by being used in the first controlling bus enquiring digital signal conversion unit 24
The state value of the working condition of word signal conversion unit 24, is specifically as follows：In advance storage is used in data signal converting unit 24
In the state value for characterizing the working condition of data signal converting unit 24, for example：Data signal converting unit 24 can be represented with 0X00
Nil signal input, 0X55 represent that the sdi signal of 1080P, 0X54 represent sdi signal of 720P etc., and data processor 4 can be with
Worked for characterizing data signal converting unit 24 by cyclic polling data signal converting unit 24 by the first controlling bus
The state value (such as inquiring about once per 500 milliseconds (ms)) of state, can not also press cyclic polling certainly, but set as needed
Inquiry mode, the embodiment of the present application is not defined to inquiry mode, single when there is data signal to be input into the data signal conversion
Unit 24, then have corresponding state value, misreads herein for avoiding the occurrence of, and can arrange the default time (such as 200ms)
The state value is read once again afterwards to be confirmed, just can determine that whether current input signal is digital letter according to the state value
Number, naturally it is also possible to it is not provided with reading state value again.
It is preferred that the quality in order to improve digital video image, referring to Fig. 3, (the dotted line frame in Fig. 3 of digital signal processor 2
Represent) can also include：It is serially connected between multiplexed signals port 1 and data signal converting unit 24, basis signal transmission direction
The data signal capacitance-resistance match circuit 22 being sequentially connected and EQ balanced devices 23；Wherein, the master of data signal capacitance-resistance match circuit 22
Function is wanted to be to carry out impedance matching to data signal so that the reflection and loss of data signal is reduced, so as to improve data signal
Quality；EQ balanced devices 23 are mainly used in carrying out data signal signal recovery, compensate the signal attenuation caused because of long range propagation,
So that image is not easy distortion.
It is pointed out that EQ balanced devices 23 are desirably integrated on a chip with data signal converting unit 24, also may be used
Being two separately independent chips.
It should be noted that in order to reduce Digital Signal Processing line influence analog signal quality, before use device, pin
To analog signal to be dealt with, the high fdrequency component that by adjusting EQ balanced devices, can as far as possible reduce analog signal passes through, so as to
Reduce Digital Signal Processing line influence analog signal quality.
It is preferred that in order to reduce Digital Signal Processing line influence analog signal quality, referring to Fig. 4, Digital Signal Processing
Device 2 (dotted line frame is represented in Fig. 4) can also include：Be serially connected in multiplexed signals port 1 and data signal capacitance-resistance match circuit 22 it
Between high-frequency inductor 21.
Specifically, referring to Fig. 5, analogue signal processor 3 (dotted line frame is represented in Fig. 5) includes：Analog-digital converter 33；The mould
Number converter 33 is decoded (for example to the analog signal that multiplexed signals port exports：Analog signal is decoded and is converted to mark
Quasi- BT656 or BT1120 digital parallels signal), and by decoded signal output to data processor 4, wherein, modulus (A/D)
Converter 33 for example can be Video Decoder.
As shown in figure 5, the second controlling bus are connected between analog-digital converter 33 and data processor 4 (for example：IIC is total
Line)；Data processor 4 is inquired about in analog-digital converter 33 for characterizing the work shape of analog-digital converter 33 by second controlling bus
The state value of state, determines whether current input signal is analog signal according to the state value；And when determination current input signal
For data signal when, by the second controlling bus output control signal to analog-digital converter 33, control analog-digital converter 33 is closed
Close (the VO outputs that can for example close analog-digital converter 33).
Wherein, data processor 4 is inquired about in analog-digital converter 33 for characterizing analog-to-digital conversion by second controlling bus
The state value of the working condition of device 33, it is similar with above-mentioned data signal converting unit 24, it is specifically as follows：In advance in analog-digital converter
The state value for characterizing the working condition of analog-digital converter 33 is stored in 33, data processor 4 can pass through the second controlling bus
State value by being used to characterize the working condition of analog-digital converter 33 in cyclic polling analog-digital converter 33 (is for example inquired about per 500ms
Once), cyclic polling can not also being pressed certainly, but setting inquiry mode as needed, the embodiment of the present application is not to issuer
Formula is defined, and when there is analog signal to be input into the analog-digital converter 33, then has corresponding state value, herein for avoiding the occurrence of
Misread, the state value was read once again to be confirmed after the default time (such as 200ms) can be set, according to the state
Value just can determine that whether current input signal is analog signal, naturally it is also possible to be not provided with reading state value again.
It is preferred that the quality in order to improve analog video image, referring to Fig. 6, (the dotted line frame in Fig. 6 of analogue signal processor 3
Represent) can also include：The analog signal capacitance-resistance being serially connected between the multiplexed signals port and the analog-digital converter is matched
Circuit 32；Wherein, the major function of analog signal capacitance-resistance match circuit 32 is to carry out impedance matching to analog signal so that simulation
The reflection and loss of signal is reduced, so as to improve analog signal quality.
It is preferred that referring to Fig. 7, in order to reduce analog signal processing line influence digital signal quality, analog signal processing
Device 3 (dotted line frame is represented in Fig. 7) can also include：Be serially connected in multiplexed signals port 1 and analog signal capacitance-resistance match circuit 32 it
Between data signal isolated location 31；Wherein, data signal isolated location 31 is used to isolate 3 pairs of numeral letters of analogue signal processor
Number impact, and receive the analog signal of the output of multiplexed signals port 1, and export to analog signal capacitance-resistance match circuit 32.
Now, as shown in fig. 7, data processor 4 is additionally operable to when it is determined that current input signal is data signal, output makes
Energy signal is closed to data signal isolated location 31, control data signal isolated location.
Specifically, referring to Fig. 8, above-mentioned data signal isolated location 31 (wire frame representation of Fig. 8 midpoints) can include that band is enabled
Analog signal buffer 311 (Buffer)；Wherein, analog signal buffer 311 is used to isolate the logarithm of analogue signal processor 3
The impact of word signal, and receive the analog signal of the output of multiplexed signals port 1, and export and give analog signal capacitance-resistance match circuit
32。
As shown in figure 8, being connected with the first enable control line (example between analog signal buffer 311 and data processor 4
Such as：Universal input output (General Purpose Input Output, GPIO) enables control line)；Data processor 4 is when true
Determine current input signal for data signal when, by first enable control line export enable signal to analog signal buffer 311,
Control analog signal buffer 311 is closed.So, when it is determined that current input signal is data signal, simulation letter can be controlled
Number buffer 311 is closed, and when analog signal buffer 311 is closed, its input pin is high resistant shape
State, such that it is able to reduce analog signal processing line influence digital signal quality.
Although it is pointed out that with enable analog signal buffer 311 when closed input impedance is near in theory
It is infinitely great, but actually still with the presence of impedance, simply impedance ratio is larger, in megaohm (M Ω) rank, therefore, simulation letter
Number process circuit is not to complete switch off, and to data signal a small amount of impact still can be produced.
It is preferred that in order to further reduce analog signal processing line influence digital signal quality, referring to Fig. 9, numeral letter
Number isolated location 31 (wire frame representation of Fig. 9 midpoints) can also include the power supply unit 312 with enabling；Wherein, power supply unit
312 are used to be powered to analog signal buffer 311.
As shown in figure 9, the second enable control line is connected between power supply unit 312 and data processor 4 (for example：
GPIO enables control line)；Data processor 4 enables control line when it is determined that current input signal is data signal by second
Enable signal is exported to power supply unit 312, control power supply unit 312 is closed.So, when it is determined that current input signal is number
During word signal, while control analog signal buffer 311 is closed, power supply unit 312 can be controlled in pass
Closed state, does not power to analog signal buffer 311 so that the shut-off of the analog signal buffer 311 is more thorough, such that it is able to
Reduce analog signal processing line influence digital signal quality.
It is preferred that referring to Figure 10, for the purpose of safety, the data signal and analog signal that the embodiment of the present application is provided is simultaneous
Holding processing meanss can also include：Protection module 5；Wherein, protection module 5 is connected to digital signal processor 2 and analog signal
Between the signal input part and ground of processor 3；The protection module 5 for example can be electrostatic esd protection circuit, or surge
Protection circuit.
It is pointed out that when device starts, data signal converting unit, analog-digital converter, analog signal buffer,
Power supply unit is all to open, and data signal can enter into data signal converting unit, and analog signal can enter into mould
Number converter.
In order to be better understood from the technical scheme of the application, below with sdi signal and analog signal this two-way original video
Signal multiplexing is linked into as a example by a kind of data signal of preferred embodiment offer of the application and analog signal compatible processing device, knot
Close the specific work process of Figure 11 explanation data signals and analog signal compatible processing：
After device starts, the multiplexing of coaxial connector 01 accesses sdi signal and analog signal and exports, through protection module
After 05, sdi signal can enter into FPGA data signals converting unit 2.4, and analog signal can enter into Video Decoder
3.3；
Codec 04 is often crossed 500ms and is inquired about in FPGA data signals converting unit 2.4 for characterizing by an IIC
The state value of the working condition of FPGA data signals converting unit 2.4, and by using in the 2nd IIC inquiry Video Decoders 3.3
In the state value for characterizing the working condition of Video Decoder 3.3, a state value is read again after 200ms to be confirmed, root
According to the state value for inquiring current input signal is determined for sdi signal or analog signal；
When it is determined that current input signal is sdi signal, by the 2nd IIC output control signals to Video Decoder 3.3,
Control Video Decoder 3.3 closes VO outputs, enables control line by a GPIO and exports enable signal to analog signal
Buffer 3.11, control analog signal Buffer 3.11 is closed, and enables control line output enable letter by the 2nd GPIO
Number give power supply unit 3.12, control power supply unit 3.12 close；Sdi signal is accessed by coaxial connector 01, through protection
After module 05, then through high-frequency inductor 2.1, then to data signal capacitance-resistance match circuit 2.2, by data signal capacitance-resistance matching electricity
Road 2.2 is carried out after impedance matching to sdi signal, sends the signal to EQ balanced devices 2.3, then Jing EQ balanced devices 2.3 enter to signal
After row recovers, FPGA data signals converting unit 2.4 is sent to, Jing FPGA data signals converting unit 2.4 is to data according to SDI
After transport protocol standard parsing, BT656 or BT1120 data is activations are converted into codec 04, codec 04 pair is received
Signal processed and exported；
When it is determined that current input signal is analog signal, by an IIC output control signals FPGA data signals are given
Converting unit 2.4, control FPGA data signals converting unit 2.4 closes VO outputs；Analog signal is accessed by coaxial connector 01,
After protection module 05, then through analog signal Buffer 3.11, then to analog signal capacitance-resistance match circuit 3.2, by mould
Intend signal capacitance-resistance match circuit 3.2 is carried out after impedance matching to analog signal, sends the signal to Video Decoder 3.3, and Jing is regarded
After frequency decoder 3.3 is according to the decoding of analog signal standard, BT656 or BT1120 data is activations are converted into codec 04, compile
04 pair of signal for receiving of decoder is processed and exported.
In sum, the technical scheme that the embodiment of the present application is provided, by multiplexed signals multiplexed port incoming digital signal
And analog signal, and be provided with two-way process circuit processing data signal and analog signal respectively, realize data signal and
The compatible processing of analog signal, also, data processor is when it is determined that current input signal is data signal, output control signal
To analogue signal processor, control the analogue signal processor and close, when it is determined that current input signal is analog signal, output
Control signal controls the digital signal processor and closes to digital signal processor, can so reduce data signal and simulation
Signal is affected by other side's process circuit, so as to improve picture quality.
Those skilled in the art are it should be appreciated that embodiments herein can be provided as method, system or computer program
Product.Therefore, the application can be using complete hardware embodiment, complete software embodiment or with reference to the reality in terms of software and hardware
Apply the form of example.And, the application can be adopted and wherein include the computer of computer usable program code at one or more
The shape of the computer program implemented in usable storage medium (including but not limited to magnetic disc store and optical memory etc.)
Formula.
The application is the flow process with reference to method, equipment (system) and computer program according to the embodiment of the present application
Figure and/or block diagram are describing.It should be understood that can be by computer program instructions flowchart and/or each stream in block diagram
The combination of journey and/or square frame and flow chart and/or the flow process in block diagram and/or square frame.These computer programs can be provided
The processor of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing devices is instructed to produce
A raw machine so that produced for reality by the instruction of computer or the computing device of other programmable data processing devices
The device of the function of specifying in present one flow process of flow chart or one square frame of multiple flow processs and/or block diagram or multiple square frames.
These computer program instructions may be alternatively stored in can guide computer or other programmable data processing devices with spy
In determining the computer-readable memory that mode works so that the instruction being stored in the computer-readable memory is produced to be included referring to
Make the manufacture of device, the command device realize in one flow process of flow chart or one square frame of multiple flow processs and/or block diagram or
The function of specifying in multiple square frames.
These computer program instructions also can be loaded in computer or other programmable data processing devices so that in meter
Series of operation steps is performed on calculation machine or other programmable devices to produce computer implemented process, so as in computer or
The instruction performed on other programmable devices is provided for realizing in one flow process of flow chart or multiple flow processs and/or block diagram one
The step of function of specifying in individual square frame or multiple square frames.
Obviously, those skilled in the art can carry out the essence of various changes and modification without deviating from the application to the application
God and scope.So, if these modifications of the application and modification belong to the scope of the application claim and its equivalent technologies
Within, then the application is also intended to comprising these changes and modification.
Claims (12)
1. a kind of data signal and analog signal compatible processing device, it is characterised in that the device includes：Multiplexed signals port,
Digital signal processor, analogue signal processor and data processor；Wherein,
The multiplexed signals port is used to be multiplexed incoming digital signal and analog signal and export；
The digital signal processor is used to process the data signal of the multiplexed signals port output, and exports to the data
Processor；
The analogue signal processor is used to process the analog signal of the multiplexed signals port output, and exports to the data
Processor；
The data processor is used for the signal to receiving and is processed and exported, and determines that current input signal is numeral
Signal or analog signal, when it is determined that current input signal is data signal, output control signal gives the analog signal processing
Device, controls the analogue signal processor and closes, and when it is determined that current input signal is analog signal, output control signal is to institute
Digital signal processor is stated, the digital signal processor is controlled and is closed.
2. device as claimed in claim 1, it is characterised in that the digital signal processor includes：For to data signal
The data signal converting unit for being decoded；First is connected between the data signal converting unit and the data processor
Controlling bus；
The data processor inquires about described for characterizing in the data signal converting unit by first controlling bus
The state value of data signal converting unit working condition, determines whether current input signal is data signal according to the state value；
And when it is determined that current input signal is analog signal, by the first controlling bus output control signal the numeral is given
Signal conversion unit, controls the data signal converting unit and closes.
3. device as claimed in claim 2, it is characterised in that the digital signal processor also includes：
It is serially connected between the multiplexed signals port and the data signal converting unit, basis signal transmission direction is sequentially connected
The data signal capacitance-resistance match circuit for carrying out impedance matching to data signal and extensive for carrying out signal to data signal
Multiple EQ balanced devices.
4. device as claimed in claim 3, it is characterised in that the digital signal processor also includes：It is serially connected in described multiple
With the high-frequency inductor between signal port and the data signal capacitance-resistance match circuit.
5. the device as described in the arbitrary claim of Claims 1 to 4, it is characterised in that the analogue signal processor includes：For
The analog-digital converter that analog signal is decoded；The second control is connected between the analog-digital converter and the data processor
Bus processed；
The data processor is inquired about in the analog-digital converter by second controlling bus and turned for characterizing the modulus
The state value of parallel operation working condition, determines whether current input signal is analog signal according to the state value；And work as when determining
When front input signal is data signal, by the second controlling bus output control signal the analog-digital converter, control are given
The analog-digital converter is closed.
6. device as claimed in claim 5, it is characterised in that the analogue signal processor also includes：It is serially connected in described multiple
Matched with the analog signal capacitance-resistance for carrying out impedance matching to analog signal between signal port and the analog-digital converter
Circuit.
7. device as claimed in claim 6, it is characterised in that the analogue signal processor also includes：It is serially connected in described multiple
With the data signal isolated location between signal port and the analog signal capacitance-resistance match circuit；Wherein, the data signal
Isolated location is used to isolate impact of the analogue signal processor to data signal, and to receive the multiplexed signals port defeated
The analog signal for going out, and export to the analog signal capacitance-resistance match circuit；
The data processor is additionally operable to when it is determined that current input signal is data signal, exports enable signal to the numeral
Signal isolation unit, controls the data signal isolated location and closes.
8. device as claimed in claim 7, it is characterised in that the data signal isolated location includes the letter of the simulation with enabling
Number buffer；Wherein, the analog signal buffer is used to isolate impact of the analogue signal processor to data signal, with
And the analog signal of the multiplexed signals port output is received, and export to the analog signal capacitance-resistance match circuit；The mould
Intend being connected with the first enable control line between signal buffer and the data processor；
The data processor enables control line output and enables letter when it is determined that current input signal is data signal by first
Number the analog signal buffer is given, control the analog signal buffer and close.
9. device as claimed in claim 8, it is characterised in that the data signal isolated location also includes the power supply with enabling
Supply；Wherein, the power supply unit is used to be powered to the analog signal buffer；The power supply unit and the number
According to being connected with the second enable control line between processor；
The data processor enables control line output and enables letter when it is determined that current input signal is data signal by second
Number the power supply unit is given, control the power supply unit and close.
10. device as claimed in claim 1, it is characterised in that the device also includes：Protection module；Wherein, the protection mould
Block is connected between the digital signal processor and the signal input part and ground of the analogue signal processor.
11. devices as claimed in claim 1, it is characterised in that the multiplexed signals port is coaxial connector.
12. devices as claimed in claim 1, it is characterised in that the data processor is codec.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620845069.9U CN206100257U (en) | 2016-08-05 | 2016-08-05 | Compatible processing apparatus of data signal and analog signal |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620845069.9U CN206100257U (en) | 2016-08-05 | 2016-08-05 | Compatible processing apparatus of data signal and analog signal |
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| CN206100257U true CN206100257U (en) | 2017-04-12 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109614033A (en) * | 2019-01-22 | 2019-04-12 | 芯海科技（深圳）股份有限公司 | It is a kind of while detecting the circuit of analog signal and digital signal, device and method |
| CN110572603A (en) * | 2019-09-17 | 2019-12-13 | 浙江大华技术股份有限公司 | Hard disk video recorder |
| CN111294036A (en) * | 2019-07-17 | 2020-06-16 | 锐迪科创微电子（北京）有限公司 | Pad multiplexing device and electronic equipment |
| CN112578266A (en) * | 2020-11-27 | 2021-03-30 | 杭州长川科技股份有限公司 | Self-checking system applied to semiconductor test equipment |
| CN117498288A (en) * | 2023-11-16 | 2024-02-02 | 安徽曦合微电子有限公司 | Voltage stabilizing circuit and chip |
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2016
- 2016-08-05 CN CN201620845069.9U patent/CN206100257U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109614033A (en) * | 2019-01-22 | 2019-04-12 | 芯海科技（深圳）股份有限公司 | It is a kind of while detecting the circuit of analog signal and digital signal, device and method |
| CN111294036A (en) * | 2019-07-17 | 2020-06-16 | 锐迪科创微电子（北京）有限公司 | Pad multiplexing device and electronic equipment |
| CN110572603A (en) * | 2019-09-17 | 2019-12-13 | 浙江大华技术股份有限公司 | Hard disk video recorder |
| CN110572603B (en) * | 2019-09-17 | 2022-02-18 | 浙江大华技术股份有限公司 | Hard disk video recorder |
| CN112578266A (en) * | 2020-11-27 | 2021-03-30 | 杭州长川科技股份有限公司 | Self-checking system applied to semiconductor test equipment |
| CN117498288A (en) * | 2023-11-16 | 2024-02-02 | 安徽曦合微电子有限公司 | Voltage stabilizing circuit and chip |
| CN117498288B (en) * | 2023-11-16 | 2024-06-07 | 安徽曦合微电子有限公司 | Voltage stabilizing circuit and chip |
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