CN206076052U - Chip is combined components and parts - Google Patents
Chip is combined components and parts Download PDFInfo
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- CN206076052U CN206076052U CN201621104168.8U CN201621104168U CN206076052U CN 206076052 U CN206076052 U CN 206076052U CN 201621104168 U CN201621104168 U CN 201621104168U CN 206076052 U CN206076052 U CN 206076052U
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Abstract
The utility model discloses a kind of compound components and parts of chip.A kind of compound components and parts of chip include：Ceramic body, ceramic body include：First medium layer has relative first surface and second surface；First electrode layer is formed at the first surface of first medium layer；At least partly concordant formation draws side to the second electrode lay with a line of second surface；Second dielectric layer is laminated in the surface of the second electrode lay and second surface is completely covered, and second dielectric layer has the 3rd surface；At least partly concordant formation draws side to 3rd electrode layer with a line on the 3rd surface；3rd dielectric layer is laminated on the surface of the 3rd electrode layer and the 3rd surface is completely covered, and the 3rd dielectric layer has the 4th surface；4th electrode layer, is formed at the 4th surface；Resistance, is attached to the side of ceramic body, and resistive layer is electrically connected with first electrode layer and the 3rd electrode layer, and insulate with the 4th electrode layer and the second electrode lay.The compound component structure of this chip is compact.
Description
Technical field
This utility model is related to field of electrical components, more particularly, to a kind of compound components and parts of chip.
Background technology
As the development of science and technology, electronic product are maked rapid progress, the major requirement to components and parts is miniaturization and multifunction.
In many circuit applications, when needing the circuit using resistance and capacitances in series structure, discrete component is generally used, i.e., single electricity
Resistance and single electric capacity, so take more circuit space, are unfavorable for the miniaturization of whole machine, and mount less efficient.
Utility model content
Based on this, it is necessary to provide a kind of compound components and parts of chip of the resistance capacitance series connection of compact conformation.
A kind of chip is combined components and parts, including：
Ceramic body, the ceramic body include：
First medium layer, the first medium layer have relative first surface and second surface；
First electrode layer, is formed at the first surface of the first medium layer；
The second electrode lay, is formed at the second surface of the first medium layer, the second electrode lay and second table
The a line in face is at least partly concordantly formed and draws side；
Second dielectric layer, is laminated in the surface of the second electrode lay and the second surface is completely covered, and described second
Dielectric layer has the 3rd surface, and the 3rd surface is a side surface of the second dielectric layer away from the first medium layer；
3rd electrode layer, is formed at the 3rd surface, and a line on the 3rd electrode layer and the 3rd surface
At least partly concordant formation draws side；
3rd dielectric layer, is laminated in the surface of the 3rd electrode layer and the 3rd surface is completely covered, and the described 3rd
Dielectric layer has the 4th surface, and the 4th surface is a side surface of the 3rd dielectric layer away from the second dielectric layer；
4th electrode layer, is formed at the 4th surface；
Resistance, is attached to the side of the ceramic body；
Wherein, the resistive layer is electrically connected with first electrode layer and the 3rd electrode layer, and with the 4th electrode layer
And the second electrode lay insulation, and/or, the resistance is electrically connected with the second electrode lay and the 4th electrode layer, and with institute
State resistance to insulate with first electrode layer and the 3rd electrode layer.
Wherein in one embodiment, the second electrode lay is electric with described first in the orthographic projection of the first electrode layer
Pole layer is least partially overlapped.
Wherein in one embodiment, projection and the first electrode of the 3rd electrode layer in the first electrode layer
Layer overlaps；And/or, the 4th electrode layer is overlapped with the second electrode lay in the projection of the second electrode lay.
Wherein in one embodiment, at least part of concordant shape of a line of the first electrode layer and the first surface
Into side is drawn, the extraction of the first electrode layer is located at the same of the first medium layer in the extraction with the 3rd electrode layer
One end.
Wherein in one embodiment, at least part of concordant shape of a line on the 4th electrode layer and the 4th surface
Into side is drawn, the extraction of the 4th electrode layer is located at the same of the second dielectric layer in the extraction with the second electrode lay
One end.
Wherein in one embodiment, the first surface, second surface, the 3rd surface and the 4th surface are rectangle,
The first surface has relative first side and second side, and the second surface has relative the 3rd side and the 4th
Side, the 3rd surface have the 5th relative side and the 6th side, and the 4th surface has relative heptalateral side
And the 8th side, the first side is parallel and vertical with the four side with the 5th side, the heptalateral side with
3rd side is parallel and vertical with the first side, and the extraction side of the second electrode lay is with the 3rd side at least
Flush with portions, the extraction side of the 3rd electrode layer are at least partly concordant with the 5th side.
Wherein in one embodiment, the first electrode layer extends to the second side, institute from the first side
Stating the second electrode lay and the 3rd side being extended to from the four side, the 3rd electrode layer extends from the 5th side
To the 6th side, the 4th electrode layer extends to the heptalateral side from the 8th side.
Wherein in one embodiment, the first electrode layer the second surface orthographic projection around the orthographic projection
It is Chong Die with the second electrode lay after 90 ° of central rotation, orthographic projection and the first electrode of the 3rd electrode layer in first surface
Layer is completely overlapped, and the 4th electrode layer is completely superposed with the second electrode lay in the orthographic projection of the second surface.
Wherein in one embodiment, the first surface, second surface, the 3rd surface and the 4th surface are pros
Shape, the second side that the first surface is had first side and intersected with the first side, the second surface have the
Three sides and the four side intersected with the 3rd side, the 3rd surface have the 5th side and with the 5th side
The 6th intersecting side, the 4th surface have heptalateral while and the 8th side intersected during with the heptalateral, described the
One side and the second side are just constituted with the 3rd side and the four side in the orthographic projection of the second surface
It is square, the 5th side and the 6th side the first surface orthographic projection respectively with the first side and described
Second side overlaps, the heptalateral side and the 8th side the second surface orthographic projection respectively with the 3rd side
Side and the four side overlap, and the first electrode layer is at least part of with the first side and second side of the first surface
Concordantly, the second electrode lay is at least partly concordant with the 3rd side of the second surface and four side, and the described 3rd is electric
Pole layer is at least partly concordant with the 5th side and the 6th side on the 3rd surface, the 4th electrode layer and the 4th table
The heptalateral side and the 8th side in face is at least partly concordant.
Above-mentioned chip is combined components and parts, and resistance is attached to the side for drawing the ceramic body that side is located of the 3rd electrode layer,
Resistance is electrically connected with first electrode layer and the 3rd electrode layer, and is insulated with the 4th electrode layer and the second electrode lay, it is electric by first
Pole layer and the 4th electrode layer are formed with outside line and are electrically connected, the 3rd electrode layer, the 3rd dielectric layer and the 4th electrode layer composition electricity
Hold, the part resistance between first electrode layer and the 3rd electrode layer constitutes cascaded structure with capacitances in series, so as to electricity
Resistance and electric capacity are integrated in discrete component；Resistance is attached to into the side for drawing the ceramic body that side is located of the second electrode lay, will
Resistance is electrically connected with the second electrode lay and the 4th electrode layer, and is insulated with first electrode layer and the 3rd electrode layer, by first electrode
Layer and the 4th electrode layer are formed with outside line and are electrically connected, first electrode layer, first medium layer and the second electrode lay composition electric capacity,
Part resistance between the second electrode lay and the 4th electrode layer constitutes cascaded structure with capacitances in series, so as to resistance with
Electric capacity is integrated in discrete component；Resistance is directly attached to the side of ceramic body, simple structure and compact, is capable of achieving chip and is combined
The miniaturization of components and parts, first electrode layer and the 4th electrode layer are located at the surface of the compound components and parts of chip so that the compound unit of chip
Device can be formed with external circuit by the first electrode layer with larger surface area and the 4th electrode layer and be electrically connected.
Description of the drawings
Fig. 1 is the three-dimensional assembling structure schematic diagram of the compound components and parts of chip of an embodiment；
Decomposing schematic representations of the Fig. 2 for the ceramic body of the compound components and parts of chip in Fig. 1；
Fig. 3 is the three-dimensional assembling structure schematic diagram of the compound components and parts of chip of another embodiment；
Decomposing schematic representations of the Fig. 4 for the ceramic body of the compound components and parts of chip in Fig. 3；
Fig. 5 is the three-dimensional assembling structure schematic diagram of the compound components and parts of chip of another embodiment；
Decomposing schematic representations of the Fig. 6 for the ceramic body of the compound components and parts of chip in Fig. 5.
Specific embodiment
The compound components and parts of chip are described in further detail mainly in combination with accompanying drawing below.
Please refer to Fig. 1 and Fig. 2, the compound components and parts 100 of chip of an embodiment include ceramic body 110 and are formed at
The resistance 150 of 110 side of ceramic body.
Ceramic body 110 is cuboid, in the illustrated embodiment, the substantially cuboid of ceramic body 110, certainly, at which
In his embodiment, ceramic body 110 can also be square.Ceramic body 110 includes the first medium layer 111, first for stacking gradually
Electrode layer 112, the second electrode lay 113, second dielectric layer 114, the 3rd electrode layer 115, the 3rd dielectric layer 116 and the 4th electrode layer
117。
In the illustrated embodiment, first medium layer 111 is rectangular patch, with relative first surface (not shown)
And second surface 1112.Certainly, in other embodiments, first medium layer 111 can also be square lamellar or other shapes
Shape.
First surface has relative first side and second side.In the illustrated embodiment, first surface is square
The minor face of shape, first side and second side for rectangle.
Second surface 1112 has the 3rd relative side and four side.In the illustrated embodiment, second surface
1112 is rectangle, the 3rd side and the minor face that four side is rectangle.
First electrode layer 112 is laminated in first surface.First electrode layer 112 extends from first side to second side.
In embodiment illustrated, first electrode layer 112 is rectangle, and the length of first electrode layer 112 is more slightly shorter than the length of first surface,
The gap that width is 0.2mm～0.5mm is formed between first electrode layer 112 and second side；The width of first electrode layer 112
Less than be formed between the two other side of the width of first surface, first electrode layer 112 and first surface width for 0mm～
The gap of 0.5mm, in the illustrated embodiment, gap has certain width, certainly in other embodiments, the width in gap
Degree can be 0, that is, the width of first electrode layer 112 is equal with the width of first surface.First electrode layer 112 and the first side
It is to draw side while concordant.First electrode layer 112 is had larger area and is electrically connected in order to be formed with outside line.In figure
In the embodiment for showing, the width of first electrode layer 112 is more than 1/2nd of the width of first surface, first electrode layer 112
Length more than first surface length 1/2nd.
The second electrode lay 113 is laminated in second surface 1112.The second electrode lay 113 prolongs from four side to the 3rd side
Stretch.3rd side is located at same one end of first medium layer 111 with first side.In the illustrated embodiment, the second electrode lay
113 is rectangle, and the length ratio of the second electrode lay 113 is slightly shorter with the length of second surface 1112, the second electrode lay 113 and the 3rd side
The gap that width is 0.2mm～0.5mm is formed between side；Width of the width of the second electrode lay 113 less than second surface 1112
Degree, forms gap of the width for 0mm～0.5mm, in figure between the second electrode lay 113 and the two other side of second surface 1112
In the embodiment for showing, gap has certain width, and certainly in other embodiments, the width in gap can be 0, that is,
The width of the second electrode lay 113 is identical with the width of second surface 1112.113 side concordant with four side of the second electrode lay is
Draw side.In the illustrated embodiment, orthographic projection and the second electrode lay 113 of the first electrode layer 112 in second surface 1112
Partly overlap.The second electrode lay 113 is not covered with the entire area of second surface, such that it is able to increase 114 He of second dielectric layer
Bonding force between first medium layer 111.In the illustrated embodiment, the width of the second electrode lay 113 is more than second surface
/ 2nd of 1112 width, the length of the second electrode lay 113 is more than 1/2nd of the length of second surface 1112.
Second dielectric layer 114 is laminated in the surface of the second electrode lay 113.Second dielectric layer 114 is rectangular patch, in diagram
Embodiment in, second dielectric layer 114 is completely covered the surface of the second electrode lay 113 and second surface 1112.Second medium
Layer 114 is the 3rd surface 1141 away from a side surface of first medium layer 111.3rd surface 1141 is substantially rectangular, with phase
To the 5th side and the 6th side, the 5th side and the 6th side are minor face.In the illustrated embodiment, first side,
3rd side and the 5th side are located at the first end of ceramic body 110, and second side, four side and the 6th side are located at ceramic body
110 the second end.
3rd electrode layer 115 is formed at a side surface of the second dielectric layer 114 away from first medium layer 111.In diagram
In embodiment, the 3rd electrode layer 115 is rectangle, and the 3rd electrode layer 115 is from the 5th side on the 3rd surface 1141 to the 6th side
Side extends, and the length of the 3rd electrode layer 115 is more slightly shorter than the length on the 3rd surface 1141, the 3rd electrode layer 115 and the 6th side it
Between be formed with width be 0.2mm～0.5mm gap；Width of the width of the 3rd electrode layer 115 less than the 3rd surface 1141, the
Gap of the width for 0mm～0.5mm is formed between three electrode layers 115 and the two other side on the 3rd surface 1141, in diagram
In embodiment, gap has certain width, and certainly in other embodiments, the width in gap can be the 0, that is, the 3rd
The width of electrode layer 115 is identical with 1141 width of the 3rd surface.3rd electrode layer 115 side concordant with the 5th side is extraction
Side.In the illustrated embodiment, the 3rd electrode layer 115 is completely overlapped with first electrode layer 112 in the orthographic projection of first surface,
Certainly, in other embodiments, the 3rd electrode layer 115 also can part with first electrode layer 112 in the orthographic projection of first surface
Overlap.
3rd dielectric layer 116 is laminated in the surface of the 3rd electrode layer 115.3rd dielectric layer 116 is rectangular patch, in diagram
Embodiment in, the 3rd dielectric layer 116 is completely covered the surface on the 3rd electrode layer 115 and the 3rd surface 1141.3rd medium
Layer 116 is the 4th surface 1161 away from a side surface of second dielectric layer 114.4th surface 1161 is substantially rectangular, with phase
To heptalateral side and the 8th side, heptalateral side and the 8th side are minor face.In the illustrated embodiment, first side,
3rd side, the 5th side and heptalateral side be located at ceramic body 110 first end, second side, four side, the 6th side and
8th side is located at the second end of ceramic body 110.
4th electrode layer 117 is laminated in the 4th surface 1161.4th electrode layer 117 prolongs from the 8th side to heptalateral side
Stretch.In the illustrated embodiment, the 4th electrode layer 117 is rectangle, and the length of the 4th electrode layer 117 is than the 4th surface 1161
Length is slightly shorter, and the gap that width is 0.2mm～0.5mm is formed between the 4th electrode layer 117 and heptalateral side；4th electrode layer
Width of 117 width less than the 4th surface 1161, shape between the 4th electrode layer 117 and the two other side on the 4th surface 1161
Into the gap that width is 0mm～0.5mm, in the illustrated embodiment, gap has certain width, implements at other certainly
In example, the width in gap can be 0, that is, the width of the 4th electrode layer 117 is identical with the width on the 4th surface 1161.4th
Surface 1161 it is concordant with the 8th side while for draw while.In the illustrated embodiment, the 4th electrode layer 117 is in second surface
1112 orthographic projection is overlapped with the second electrode lay 113.
In the illustrated embodiment, first electrode layer 112 and the 3rd electrode layer 115 are weighed completely in the projection of first surface
Close, the projection of the second electrode lay 113 and the 4th electrode layer 117 on the 4th surface 1161 is completely superposed, no matter thus, resistance 150
The extraction for being attached to the second electrode lay 113 of ceramic body 110 is located in the extraction of the side or the 3rd electrode layer 115 that are located
Side, the resistance value of the compound components and parts 100 of chip will not produce difference.
First medium layer 111, first electrode layer 112, the second electrode lay 113, second dielectric layer 114, the 3rd electrode layer
115th, the 3rd dielectric layer 116 and the 4th electrode layer 117 stack gradually the ceramic body 110 to form cuboid.Preferably, ceramic body
110 length: width and big more than the 0.2mm of thickness.
In the illustrated embodiment, the thickness of first medium layer 111 and second dielectric layer 114 is identical, certainly, at other
In embodiment, the thickness of second dielectric layer 114 can also be different from first medium layer 111.The thickness pair of second dielectric layer 114
The capacitance of the compound components and parts 100 of chip does not produce impact, therefore can go adjustment by adjusting the thickness of second dielectric layer 114
The thickness of the compound components and parts 100 of chip.When requiring that the compound components and parts of chip have larger capacitance, first Jie can be reduced
The thickness of matter layer 111, while increase the thickness of second dielectric layer 114, to ensure that the compound components and parts 100 of chip have enough thickness
Degree avoids fracture；When requiring that the compound components and parts 100 of chip have less capacitance, first medium layer 111 can be increased
Thickness, while reducing the thickness of second dielectric layer 114.
In the illustrated embodiment, the thickness of first medium layer 111 and the 3rd dielectric layer 116 is identical, no matter thus, electricity
Resistance 150 is attached to the side for drawing side place of the second electrode lay 113 of ceramic body 110 or the extraction of the 3rd electrode layer 115
The side that side is located, the capacitance of the compound components and parts 100 of chip will not produce difference.Certainly, in other embodiments, the 3rd
The thickness of dielectric layer 116 can also be different from first medium layer 111.
Resistance 150 is attached to the side of ceramic body 110, and specifically, resistance 150 is attached to the extraction of the second electrode lay 113
The side that side is located, or it is attached to the side for drawing side place of the 3rd electrode layer 115.When resistance 150, to be attached to second electric
When drawing the side that side is located of pole layer 113, resistance 150 is electrically connected with the second electrode lay 113 and the 4th electrode layer 117, and with
First electrode layer 112 and the 3rd electrode layer 115 insulate, and are formed with outside line by first electrode layer 112 and the 4th electrode layer 117
Electrical connection, first electrode layer 112, first medium layer 111 and the second electrode lay 113 composition electric capacity, positioned at the second electrode lay 113 and
Part resistance between 4th electrode layer 117 constitutes cascaded structure with capacitances in series, so as to resistance and electric capacity are integrated into list
In individual element；When resistance 150 is attached to when drawing the side that side is located of the 3rd electrode layer 115, resistance 150 and first electrode layer
112 and the 3rd electrode layer 115 electrically connect, and insulate with the second electrode lay 113 and the 4th electrode layer 117, the 3rd electrode layer 115,
3rd dielectric layer 116 and the composition electric capacity of the 4th electrode layer 117, that between first electrode layer 112 and the 3rd electrode layer 115
Partial ohmic constitutes cascaded structure with capacitances in series, so as to resistance and electric capacity are integrated in discrete component.
In the illustrated embodiment, it is formed between 0.2mm～0.5mm between first electrode layer 112 and second side
Gap, is formed with the gap of 0.2mm～0.5mm, the 3rd electrode layer 115 and the 6th side between the second electrode lay 113 and the 3rd side
The gap of 0.2mm～0.5mm is formed between side, between the 4th electrode layer 117 and heptalateral side, 0.2mm～0.5mm is formed with
Gap, such that it is able to realize the insulation with resistance 150, certainly in other embodiments, gap can be 0, now pass through
Insulation processing is carried out between resistance 150.
In the illustrated embodiment, first electrode layer 112 is formed with extraction side, and the 4th electrode layer 117 is formed with extraction
Side, electrically connects so as to pass through to draw the realization of side and resistance 150, certainly, in other implementations, first electrode layer 112 and
Can omit on the extraction side of the 4th electrode layer 117, i.e. between first electrode layer 112 and first side, be formed with gap, the 4th is electric
Gap is formed between pole layer 117 and the 8th side, now, resistance 150 is extended directly to first surface or the 4th surface 1161
Electrically connect to realization is contacted with first electrode layer 112 or the 4th electrode layer 117.
Above-mentioned chip is combined components and parts 100, and resistance 150 is attached to the side that side is located of drawing of the second electrode lay 113, or
Person is attached to the side for drawing side place of the 3rd electrode layer 115.When resistance 150 is attached to the extraction side of the second electrode lay 113
During the side at place, resistance 150 is electrically connected with the second electrode lay 113 and the 4th electrode layer 117, and with first electrode layer 112 and
3rd electrode layer 115 insulate, and is formed with outside line and is electrically connected by first electrode layer 112 and the 4th electrode layer 117, first electrode
Layer 112, first medium layer 111 and the composition electric capacity of the second electrode lay 113, positioned at the second electrode lay 113 and the 4th electrode layer 117 it
Between part resistance and capacitances in series constitute cascaded structure, so as to resistance and electric capacity are integrated in discrete component；Work as resistance
150 are attached to when drawing the side that side is located of the 3rd electrode layer 115, resistance 150 and first electrode layer 112 and the 3rd electrode layer
115 electrical connections, and are insulated with the second electrode lay 113 and the 4th electrode layer 117, the 3rd electrode layer 115, the 3rd dielectric layer 116 and
4th electrode layer 117 constitutes electric capacity, the part resistance and electric capacity between first electrode layer 112 and the 3rd electrode layer 115
Cascaded structure is composed in series, so as to resistance and electric capacity are integrated in discrete component；Resistance 150 is directly attached to ceramic body 110
Side, formed with outside line and electrically connected by first electrode layer 112 and the 4th electrode layer 117, simple structure and compact,
Achievable miniaturization；Resistance 150 is attached to the side for drawing side place of the second electrode lay 113, or is attached to the 3rd electrode
The side for drawing side place of layer 115, in the preparation, it is thus only necessary to which resistance is attached to into two sides of ceramic body 110
In any one, without the need for identification, Simplified flowsheet.
By adjust the facing area of first electrode layer 112 and the second electrode lay 113, the thickness of first medium layer 111 and
Dielectric constant can adjust the capacitance of the compound components and parts 100 of chip, by adjust the resistivity of resistance 150, four side with
Spacing between 8th side can adjust the resistance value of the compound components and parts 100 of chip；By adjusting first medium layer 111 and the
The thickness of second medium layer 114 can adjust the thickness of the compound components and parts 100 of chip, increase versatility.
When projection of the first electrode layer 112 on the 3rd surface 1141 it is completely overlapped with the 3rd electrode layer 115, the second electrode lay
113 projections on the 4th surface 1161 are completely overlapped with the 4th electrode layer 117, so as to resistance 150 is arranged on the 3rd electrode layer
Any one in the side that 115 extraction is located in the extraction of the side and the second electrode lay 113 that are located will not causing property
The change of energy.
The preparation method of the compound components and parts of above-mentioned chip, comprises the following steps：
Step S210, prepare starch film.
In the present embodiment, starch, first adhesive and the first solvent mix homogeneously are obtained into starch size, with starch
Slurry prepares starch film for raw material.
Preferably, starch, first adhesive and the first solvent mix homogeneously are obtained into starch size by the way of ball milling.
Further, the time of ball milling is 3 hours～4 hours.
Preferably, the mass ratio of starch, first adhesive and the first solvent is 10：2.5～3：10～15.
Preferably, starch is corn starch.
Preferably, at least one during first adhesive is selected from acrylic resin and polyvinyl butyral resin.
Preferably, the first solvent is that mass ratio is 1：1～1.25：1 toluene and the mixed solvent of dehydrated alcohol.
Preferably, starch size also includes plasticizer, and in one embodiment, plasticizer is dioctyl phthalate
(DOP).Further, plasticizer and the mass ratio of starch are 1：20～1：10.
Preferably, starch size is cast to form starch film using the tape casting.
Preferably, the thickness of starch film is 90 μm～130 μm.
Step S220, prepare ceramic membrane.
In the present embodiment, ceramic size will be obtained after ceramics, second adhesive, the second solvent mix homogeneously, with
Ceramic size prepares ceramic membrane for raw material.
Preferably, ceramics, second adhesive, the second solvent mix homogeneously by the way of ball milling are obtained into ceramic slurry
Material.Further, the time of ball milling is 12 hours～16 hours.
Preferably, ceramics, second adhesive, the mass ratio of the second solvent are 10：3～5：4～6.
Preferably, ceramics are barium titanate ceramic powder, and certainly, other ceramics commonly used in the trade can also.Barium metatitanate. is made pottery
Porcelain powder has higher dielectric constant so that the capacitance swing of the compound components and parts of the chip of preparation is wider.
Preferably, second adhesive is polyvinyl butyral resin, and it is 1 that the second solvent is mass ratio:1～1.5:1 toluene
With the mixed solvent of dehydrated alcohol.
Preferably, ceramic size is cast to form ceramic membrane using the tape casting.
Preferably, the thickness of ceramic membrane is 20 μm～60 μm.
Step S230, multiple ceramic membranes, the protective layer being secured on substrate are laminated in substrate surface.
Preferably, substrate is corrosion resistant plate, and certainly, other intensity and toughness suitable material can serve as the material of substrate
Material.
Preferably, the thickness of protective layer is 0.2mm～0.3mm.
Step S240, at least one starch film is laminated on the protection layer.
Step S250, starch film surface prepare first electrode layer.
In present embodiment, first electrode layer is prepared on starch film surface by the way of silk screen printing.Further, adopt
With silk screen in starch film print electrode on surface slurry, the first electrode layer being layered on starch film after drying, is obtained.
The material of first electrode layer can be silver, palladium or silver palladium alloy.Further, palladium and silver-colored quality in palladium-silver
Than there is no particular restriction.
Preferably, electrode slurry can be silver paste, palladium slurry or silver palladium alloy slurry.
Preferably, when starch film surface prepares first electrode layer using the method for three-point fix positioning substrate.
Preferably, the thickness of first electrode layer is 1 μm～3 μm.
Step S260, a few ceramic membrane is laminated on first electrode layer surface, obtain being layered in first electrode layer surface
First medium layer.
In this step, the quantity of ceramic membrane is determined according to the design thickness of first medium layer, such that it is able to needed for reaching
The thickness wanted.
Preferably, the thickness of first medium layer is 25 μm～200 μm.
Step S270, the second electrode lay is prepared on the surface of first medium layer.
In present embodiment, the second electrode lay is prepared in first medium layer surface by the way of silk screen printing.Further
, to be printed electrode slurry in first medium layer surface using silk screen, obtain being layered on first medium layer after drying second is electric
Pole layer.The silk screen used in silk screen and step S250 used in the step can be the same or different, when in two steps
When the silk screen that uses is identical, without the need for re-registrate again in the step.
The material of the second electrode lay can be silver, palladium or silver palladium alloy.Further, palladium and silver-colored quality in palladium-silver
Than there is no particular restriction.
Preferably, electrode slurry can be silver paste, palladium slurry or silver palladium alloy slurry.
Preferably, the thickness of the second electrode lay is 1 μm～3 μm.
Step S280, a few ceramic membrane is laminated on the surface of the second electrode lay, obtain being layered in the second electrode lay table
The second dielectric layer in face.
In this step, the quantity of ceramic membrane is determined according to the design thickness of second dielectric layer, such that it is able to needed for reaching
The thickness wanted.
Preferably, the thickness of second dielectric layer is 20 μm～350 μm.
Step S290, second dielectric layer surface prepare the 3rd electrode layer.
In present embodiment, the 3rd electrode layer is prepared in second medium layer surface by the way of silk screen printing.Further
, using silk screen in second dielectric layer print electrode on surface slurry, obtain being layered in second dielectric layer after drying the 3rd is electric
Pole layer.
The material of the 3rd electrode layer can be silver, palladium or silver palladium alloy.Further, palladium and silver-colored quality in palladium-silver
Than there is no particular restriction.
Preferably, electrode slurry can be silver paste, palladium slurry or silver palladium alloy slurry.
Preferably, the thickness of the 3rd electrode layer is 1 μm～3 μm.
Step S300, the 3rd electrode layer surface be laminated at least one ceramic membrane, obtain being layered in the 3rd electrode layer surface
The 3rd dielectric layer.
In this step, the quantity of ceramic membrane is determined according to the design thickness of the 3rd dielectric layer, such that it is able to needed for reaching
The thickness wanted.
Preferably, the thickness of the 3rd dielectric layer is 25 μm～200 μm.
Step S310, the 3rd dielectric layer surface prepare the 4th electrode layer obtain multilayer board.
In present embodiment, the 4th electrode layer is prepared in the 3rd dielectric layer surface by the way of silk screen printing.Further
, being printed electrode slurry in the 3rd dielectric layer surface using silk screen, obtain being layered on the 3rd dielectric layer after drying the 4th is electric
Pole layer.
The material of the 3rd electrode layer can be silver, palladium or silver palladium alloy.Further, palladium and silver-colored quality in palladium-silver
Than there is no particular restriction.
Preferably, electrode slurry can be silver paste, palladium slurry or silver palladium alloy slurry.
Preferably, the thickness of the 4th electrode layer is 1 μm～3 μm.
Silk screen printing can use same when preparing first electrode layer, the second electrode lay, the 3rd electrode layer and four electrode layers
One silk screen, therefore when the second electrode lay is printed without the need for re-registrating to silk screen, it is simple to operate；By the printing that misplaces
Mode, can prepare each electrode layer.
Step S320, multilayer board is carried out pressing obtain duplexer.
In the present embodiment, pressing makes in multilayer board each film layer tight bond to avoid using isostatic pressing method pressing
Layering.
In the present embodiment, cut according to required size after pressed multilayer board, afterwards with substrate point
From obtaining duplexer.Separate with substrate and duplexer can be shoveled using blade, in this step, protective layer can guarantee that first
Do not scratched by blade in the operation of electrode layer here.
Step S330, carry out to duplexer that row is viscous and sintering obtains ceramic body.
Wherein in one embodiment, arranging viscous concrete operations is：Duplexer is heated to into 350 DEG C～450 DEG C and 1 is incubated
～3 hours.Further, arranging to glue is carried out in air atmosphere.
One embodiment wherein, the concrete operations of sintering are：Duplexer of the row after viscous is heated to into 900 DEG C～1320 DEG C
And be incubated 2 hours～3 hours and be sintered.Further, sintering is carried out in air atmosphere.
In the step, during sintering, starch film ashing so that protective layer departs from.
First electrode layer that the ceramic body obtained after sintering includes stacking gradually, first medium layer, the second electrode lay, second
Dielectric layer, the 3rd electrode layer, the 3rd dielectric layer and the 4th electrode layer.
Step S340, resistance is formed in side of ceramic body and obtain the compound components and parts of chip.
In the present embodiment, a side in ceramic body by way of dipping forms resistance.
It should be noted that a side described in the step is the side that first side or second side are located.
Preferably, ceramic body is fixed using suitable fixture such as end-blocking plate, by resistance slurry by way of dipping
A side of ceramic body is sticked to, sintering obtains resistance after drying.Further, the temperature of sintering is 840 DEG C～850 DEG C.
Further, resistance slurry is ruthenium system resistance slurry.Further, sintering is carried out in air atmosphere.Further, drying
Temperature is 140 DEG C～150 DEG C.
By the depth for adjusting dipping, it is ensured that resistance slurry only stick on the target surface of ceramic body 110 and not
Other four surfaces adjoined with target surface can be extended to；It is of course also possible to pass through to adjust the depth of dipping, resistance slurry is made
Adhere at least one of first surface and the 4th surface so that the first electrode layer 112 of resistance 150 and ceramic body 110 and
One of formation electrical connection in 4th electrode layer 117.
The length of ceramic body 110 0.2mm more than bigger than the thickness of width and ceramic body 110 of ceramic body 110, Ke Yibao
Card being properly positioned in fixture of ceramic body 110, that is, ensure that resistance slurry will not be adhered to the other surfaces of ceramic body 110 by mistake
On.
The preparation method of the compound components and parts of above-mentioned chip, process is simple.
It should be noted that the order of step S210 and step S220 can be exchanged, it is also possible to synchronous to perform, certainly, exist
In other embodiment, starch film and ceramic membrane can also outsourcing, then step S210 and step S220 can be omitted.Step S230
Can omit, now duplexer be separated from substrate using other modes.Step S240 can be omitted, now by other
Technique directly on starch film prepare first electrode layer.
Refer to Fig. 3 and Fig. 4, structure and the compound components and parts of chip of the compound components and parts 500 of chip of another embodiment
100 structure is roughly the same, and its difference is：First surface, second surface 5112, the 3rd surface 5141 and the 4th surface 5161
Be square, the 5th side on the first side of first surface and the 3rd surface 5141 be parallel to each other and with second surface 5112
Four side it is vertical, the heptalateral side on the 4th surface 5161 is parallel with the 3rd side of second surface 5112 and and first surface
First side it is vertical.The extraction side of the second electrode lay 513 is at least partly concordant with the 3rd side, and the 3rd electrode layer 515 draws
Go out side at least partly concordant with the 5th side.The length and width of ceramic body 510 is equal so that the compound components and parts 500 of chip
Circuit space utilization rate is higher.
In the illustrated embodiment, first electrode layer 512 extends to second side, the second electrode lay from first side
513 extend to four side from the 3rd side, and the 3rd electrode layer 515 extends to the 6th side, the 4th electrode layer from the 5th side
517 extend to the 8th side from heptalateral side.Further, between first electrode layer 512 and other two side of first surface
It is formed with the gap that width is 0.2mm～0.5mm, shape between the second electrode lay 513 and other two side of second surface 5112
Into the gap for having width to be 0.2mm～0.5mm, formed between the 3rd electrode layer 515 and other two side on the 3rd surface 5141
The gap for having width to be 0.2mm～0.5mm, is formed between the 4th electrode layer 517 and other two side on the 4th surface 5161
Gap of the width for 0.2mm～0.5mm.So by resistance 550 located at any one side of ceramic body 510.
Further, first electrode layer 512 in the orthographic projection of second surface 5112 after 90 ° of the central rotation of orthographic projection
Overlap with the second electrode lay 513, the 3rd electrode layer 515 is completely overlapped with first electrode layer 512 in the orthographic projection of first surface, the
Four electrode layers 517 are completely superposed with the second electrode lay 513 in the orthographic projection of second surface 5112.Thus, by resistance 550 located at pottery
Any one side of porcelain body 510, the resistance value and capacitance of the compound components and parts 500 of chip simplify all without the difference for producing
Preparation technology.
It should be noted that in other embodiments, first surface, second surface 5112, the 3rd surface 5141 and
Four surfaces 5161 can not also be square, can be designed as rectangle.
Refer to Fig. 5 and Fig. 6, structure and the compound components and parts of chip of the compound components and parts 700 of chip of another embodiment
100 structure is roughly the same, and its difference is：First surface, second surface 7112, the 3rd surface 7141 and the 4th surface 7161
Square is, the second side that first surface is had first side and intersected with the first side, second surface 7112 have
The four side for having the 3rd side and being intersected with the 3rd side, the 3rd surface 7141 are had the 5th side and are intersected with the 5th side
The 6th side, the 4th surface 7161 have heptalateral while and the 8th side intersected during with heptalateral.
First side and second side are square with the 3rd side and four side composition in the orthographic projection of second surface 7112
Shape, the 5th side and the 6th side are overlapped with first side and second side respectively in the orthographic projection of first surface, heptalateral side
And the 8th side overlapped with the 3rd side and four side in the orthographic projection of second surface 7112 respectively.
First electrode layer 712 is at least partly concordant with the first side of first surface and second side to form two extractions
Side, the second electrode lay 713 is at least partly concordant with the 3rd side of second surface 7112 and four side to form two articles of extraction sides,
At least partly sides are drawn in two articles of concordant formation to 3rd electrode layer 715 with the 5th side and the 6th side on the 3rd surface 7141, the
Four electrode layers 717 and the heptalateral on the 4th surface 7161 while and the 8th side at least partly it is concordant form two articles and draw while.
In the illustrated embodiment, first electrode layer 712, the second electrode lay 713, the 3rd electrode layer 715 and the 4th are electric
Pole layer 717 is square.Orthographic projection of the first electrode layer 712 on the 3rd surface 7141 is overlapped with the 3rd electrode layer 715.4th
Electrode layer 717 is overlapped with the second electrode lay 713 in the orthographic projection of second surface 7112.
In the illustrated embodiment, width is formed between the two other side of first electrode layer 712 and first surface
For the gap of 0.2mm～0.5mm.Width is formed between the two other side of the second electrode lay 713 and second surface 7112 is
The gap of 0.2mm～0.5mm.Width is formed between 3rd electrode layer 715 and the two other side on the 3rd surface 7141 is
The gap of 0.2mm～0.5mm.Width is formed between 4th electrode layer 717 and the two other side on the 4th surface 7161 is
The gap of 0.2mm～0.5mm.
In the illustrated embodiment, first electrode layer 712, the second electrode lay 713, the 3rd electrode layer 715 and the 4th are electric
Pole layer 717 is square and size is identical.The length of side of first electrode layer 712 more than the length of side of first surface 1/2nd,
First electrode layer 712 is partially overlapped with the second electrode lay 713 in the orthographic projection of second surface 7112.
In the illustrated embodiment, first medium layer 711 is equal with the thickness of the 3rd dielectric layer 716.
The thickness of second dielectric layer 714 does not produce impact to the thickness of the compound components and parts 700 of chip, can be used to adjustment sheet
The thickness of the compound components and parts 700 of formula.
Above-mentioned chip is combined components and parts 700, by resistance 750 located at any one side of ceramic body 710, the compound unit of chip
The resistance value and capacitance of device 700 simplifies preparation technology all without the difference for producing.
Embodiment described above only expresses several embodiments of the present utility model, and its description is more concrete and detailed,
But therefore can not be interpreted as the restriction to this utility model the scope of the claims.It should be pointed out that common for this area
For technical staff, without departing from the concept of the premise utility, some deformations and improvement can also be made, these all belong to
In protection domain of the present utility model.Therefore, the protection domain of this utility model patent should be defined by claims.
Claims (9)
1. a kind of chip is combined components and parts, it is characterised in that include：
Ceramic body, the ceramic body include：
First medium layer, the first medium layer have relative first surface and second surface；
First electrode layer, is formed at the first surface of the first medium layer；
The second electrode lay, is formed at the second surface of the first medium layer, the second electrode lay and the second surface
A line is at least partly concordantly formed and draws side；
Second dielectric layer, is laminated in the surface of the second electrode lay and the second surface is completely covered, the second medium
Layer has the 3rd surface, and the 3rd surface is a side surface of the second dielectric layer away from the first medium layer；
3rd electrode layer, is formed at the 3rd surface, and a line on the 3rd electrode layer and the 3rd surface is at least
Flush with portions is formed draws side；
3rd dielectric layer, is laminated in the surface of the 3rd electrode layer and the 3rd surface is completely covered, the 3rd medium
Layer has the 4th surface, and the 4th surface is a side surface of the 3rd dielectric layer away from the second dielectric layer；
4th electrode layer, is formed at the 4th surface；
Resistance, is attached to the side of the ceramic body；
Wherein, the resistive layer is electrically connected with first electrode layer and the 3rd electrode layer, and with the 4th electrode layer and
Two electrode layers insulate, and/or, the resistance is electrically connected with the second electrode lay and the 4th electrode layer, and with the electricity
Resistance is insulated with first electrode layer and the 3rd electrode layer.
2. chip as claimed in claim 1 is combined components and parts, it is characterised in that the second electrode lay is in the first electrode
The orthographic projection of layer is least partially overlapped with the first electrode layer.
3. chip as claimed in claim 1 is combined components and parts, it is characterised in that the 3rd electrode layer is in the first electrode
The projection of layer is overlapped with the first electrode layer；And/or, the 4th electrode layer the second electrode lay projection with it is described
The second electrode lay overlaps.
4. chip as claimed in claim 1 is combined components and parts, it is characterised in that the first electrode layer and the first surface
A line at least partly concordantly formed draw side, the first electrode layer extraction in the extraction with the 3rd electrode layer
Positioned at same one end of the first medium layer.
5. chip as claimed in claim 1 is combined components and parts, it is characterised in that the 4th electrode layer and the 4th surface
A line at least partly concordantly formed draw side, the 4th electrode layer extraction in the extraction with the second electrode lay
Positioned at same one end of the second dielectric layer.
6. chip as claimed in claim 1 is combined components and parts, it is characterised in that the first surface, second surface, the 3rd table
Face and the 4th surface are rectangle, and the first surface has relative first side and second side, the second surface tool
There are the 3rd relative side and a four side, the 3rd surface has the 5th relative side and the 6th side, the described 4th
Surface has relative heptalateral side and the 8th side, the first side it is parallel with the 5th side and with the 4th side
Side is vertical, the heptalateral side is parallel and vertical with the first side with the 3rd side, and the second electrode lay draws
Go out side at least partly concordant with the 3rd side, the extraction side of the 3rd electrode layer is at least partly put down with the 5th side
Together.
7. chip as claimed in claim 6 is combined components and parts, it is characterised in that the first electrode layer is from the first side
The second side is extended to, the second electrode lay extends to the 3rd side from the four side, and the described 3rd is electric
Pole layer extends to the 6th side from the 5th side, and the 4th electrode layer extends to described from the 8th side
Heptalateral side.
8. chip as claimed in claim 7 is combined components and parts, it is characterised in that the first electrode layer is in the second surface
Orthographic projection it is Chong Die with the second electrode lay after 90 ° of the central rotation of the orthographic projection, the 3rd electrode layer is in first surface
Orthographic projection it is completely overlapped with the first electrode layer, orthographic projection and described of the 4th electrode layer in the second surface
Two electrode layers are completely superposed.
9. chip as claimed in claim 1 is combined components and parts, it is characterised in that the first surface, second surface, the 3rd table
Face and the 4th surface are square, the second side that the first surface is had first side and intersected with the first side
Side, the second surface have the 3rd side and the four side that intersect with the 3rd side, and the 3rd surface is with the
Five sides and the 6th side intersected with the 5th side, the 4th surface have heptalateral while and during with the heptalateral
The 8th intersecting side, the first side and the second side are in orthographic projection and the 3rd side of the second surface
And the four side constitutes square, the 5th side and the 6th side are distinguished in the orthographic projection of the first surface
Overlap with the first side and the second side, the heptalateral side and the 8th side in the second surface just
Projection is overlapped with the 3rd side and the four side respectively, the first side of the first electrode layer and the first surface
Side and second side are at least partly concordant, and the 3rd side of the second electrode lay and the second surface and four side are at least
Flush with portions, the 3rd electrode layer are at least partly concordant with the 5th side and the 6th side on the 3rd surface, and described
Four electrode layers are at least partly concordant with the heptalateral side and the 8th side on the 4th surface.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106409508A (en) * | 2016-09-30 | 2017-02-15 | 广东风华高新科技股份有限公司 | Chip-type composite component and fabrication method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106409508A (en) * | 2016-09-30 | 2017-02-15 | 广东风华高新科技股份有限公司 | Chip-type composite component and fabrication method thereof |
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