CN201708806U - Clock synchronous signal transmission circuit - Google Patents
Clock synchronous signal transmission circuit Download PDFInfo
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- CN201708806U CN201708806U CN201020232205XU CN201020232205U CN201708806U CN 201708806 U CN201708806 U CN 201708806U CN 201020232205X U CN201020232205X U CN 201020232205XU CN 201020232205 U CN201020232205 U CN 201020232205U CN 201708806 U CN201708806 U CN 201708806U
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Abstract
The utility model relates to the technical field of clock signal transmission, in particular to a clock synchronous signal transmission circuit for synchronizing clock signals of main equipment and sub equipment. The clock synchronous signal transmission circuit is characterized in that the clock synchronous signal transmission circuit comprises a synchronous clock sending unit and a plurality of synchronous clock receiving units, wherein the synchronous clock sending unit comprises a synchronous clock sending module element and an RS485 sending circuit, the synchronous clock sending module element is connected with the RS485 sending circuit and outputs TTL electric level to the RS485 sending circuit, each synchronous clock receiving unit comprises a synchronous clock receiving module element and an RS485 receiving circuit, the RS485 receiving circuit is connected with the synchronous clock receiving module element and outputs the TTL electric level to the synchronous clock receiving module element, and the RS485 sending circuit is connected with each RS485 receiving circuit and outputs RS485 differential electric level to each RS485 receiving circuit. The circuit provided by the utility model can improve the transmission quality and the driving capability of the clock synchronous signals between multiple circuits or multiple module elements, in addition, the anti-jamming capability is strong, and the utility model is applicable to the synchronous transmission of the clock signals of the main equipment and the sub equipment.
Description
Technical field
The utility model relates to the clock signal transmission technology, particularly a kind of clock sync signal transmission circuit that is used for synchronous master-slave equipment clock signal.
Background technology
In the higher master-slave equipment of some clock requests, main equipment often needs the clock of synchronous slave unit, make master-slave equipment can synchronous working in same environment.General clock synchronization mode can be divided into code synchronism and impulsive synchronization mode.
The method of synchronization of coding is mainly used in the clock synchronization of main equipment, and for the clock synchronization of slave unit, impulsive synchronization mode commonly used.Be to disclose a kind of affair sequential record method in the application for a patent for invention of 200610148163.X as application number, main DPU in this application for a patent for invention (dispersion treatment unit) is by IRIG-B sign indicating number and GPS (satellite navigation circuit) clock synchronization, and synchronous by pulse per second (PPS) and main DPU (dispersion treatment unit) from DPU (dispersion treatment unit), and implementation adopts the hardwire method of synchronization; Application number is to disclose a kind of multi-event sequence recording and test circuit in 200510095427.5 the patent application for another example, adopted in this patent application to the time signal, also adopt the method for synchronization of pulse per second (PPS).
But in above patent of invention, only the method for synchronization of signal is studied, transmission method of signal is not studied.In actual use, the hard wired connection of the normal employing of the transmission means of such synchronizing signal, the interference free performance of this connected mode is poor, and driving force is also limited.
The utility model content
At the defective that exists in the above-mentioned prior art, technical problem to be solved in the utility model provides and a kind ofly can improve transmission quality and the driving force of clock sync signal between multicircuit or multimode part, and the strong clock sync signal transmission circuit of antijamming capability.
In order to solve the problems of the technologies described above, the technical solution adopted in the utility model is: a kind of clock sync signal transmission circuit that provides is characterized in that: comprise a synchronised clock transmitting element and a plurality of synchronised clock receiving element;
Described synchronised clock transmitting element comprises synchronised clock transmission module, is used for Transistor-Transistor Logic level is converted to the RS485 transtation mission circuit of RS485 differential level, and described synchronised clock sends the module connection and also exports Transistor-Transistor Logic level to the RS485 transtation mission circuit;
Described synchronised clock receiving element comprises synchronised clock reception module, is used for the RS485 differential level is converted to the RS485 receiving circuit of Transistor-Transistor Logic level, and described RS485 receiving circuit connects and output Transistor-Transistor Logic level to synchronised clock receives module;
Described RS485 transtation mission circuit connects and exports the RS485 differential level to each RS485 receiving circuit.
Further, described RS485 transtation mission circuit comprises transmitting terminal RS485 transceiving chip, transmitting terminal optical coupling chip, transmitting terminal DC/DC power supply chip;
The power input of described transmitting terminal DC/DC power supply chip connects external power source;
The input of described transmitting terminal optical coupling chip connects the output that synchronised clock sends module, and be connected in series a current-limiting resistance, its output connects the data receiver of transmitting terminal RS485 transceiving chip, and connects the positive supply output of transmitting terminal DC/DC power supply chip through a pull-up resistor;
Described transmitting terminal RS485 transceiving chip is arranged to sending mode, is connected to a terminal resistance between two output.
Further, described RS485 receiving circuit comprises receiving terminal RS485 transceiving chip, receiving terminal optical coupling chip, receiving terminal DC/DC power supply chip;
The power input of described receiving terminal DC/DC power supply chip connects external power source;
The input of described receiving terminal optical coupling chip connects the data output end of receiving terminal RS485 transceiving chip, and be connected in series a current-limiting resistance, its output connects the input that synchronised clock receives module, and connects the positive supply output of transmitting terminal DC/DC power supply chip through a pull-up resistor;
Described receiving terminal RS485 transceiving chip is configured to receive pattern, is connected to a terminal resistance between two input.
Good effect of the present utility model is: the clock sync signal transmission circuit that provides is by the RS485 transtation mission circuit, the clock sync signal that synchronised clock is sent module output converts the RS485 differential level to from Transistor-Transistor Logic level, receive the clock sync signal that transmits in the differential level mode by the RS485 receiving circuit, and transport to synchronised clock reception module after converting thereof into Transistor-Transistor Logic level, because clock sync signal transmits in the differential transfer mode, therefore can improve transmission quality and the driving force of clock sync signal between multicircuit or multimode part, and antijamming capability is strong.
Description of drawings
Fig. 1 is the structured flowchart of the clock sync signal transmission circuit of the utility model embodiment;
Fig. 2 is the circuit diagram of the RS485 transtation mission circuit in the clock sync signal transmission circuit;
Fig. 3 is the circuit diagram of the RS485 receiving circuit in the clock sync signal transmission circuit.
Embodiment
Below in conjunction with description of drawings embodiment of the present utility model is described in further detail, but present embodiment is not limited to the utility model, every employing analog structure of the present utility model and similar variation thereof all should be listed protection range of the present utility model in.
As shown in Figure 1, a kind of clock sync signal transmission circuit that the utility model embodiment is provided is characterized in that: comprise a synchronised clock transmitting element and a plurality of synchronised clock receiving element;
Described synchronised clock transmitting element comprises synchronised clock transmission module 1, is used for Transistor-Transistor Logic level is converted to the RS485 transtation mission circuit 2 of RS485 differential level, and described synchronised clock sends module 1 to be passed through the connection of I/O output line and export Transistor-Transistor Logic level to RS485 transtation mission circuit 2;
Described synchronised clock receiving element comprises synchronised clock reception module 4, is used for the RS485 differential level is converted to the RS485 receiving circuit 3 of Transistor-Transistor Logic level, and described RS485 receiving circuit 3 connects by the I/O incoming line and output Transistor-Transistor Logic level to synchronised clock receives module 4;
Described RS485 transtation mission circuit 2 connects by the RS485 bus and exports the RS485 differential level to each RS485 receiving circuit 3;
As shown in Figure 2, described RS485 transtation mission circuit 2 comprises transmitting terminal RS485 transceiving chip U11, transmitting terminal optical coupling chip U12, transmitting terminal DC/DC power supply chip U13;
The power input of described transmitting terminal DC/DC power supply chip U13 connects external power source;
The input (pin two, 3) of described transmitting terminal optical coupling chip U12 connects the output that synchronised clock sends module 1, and be connected in series a current-limiting resistance R13, its output (pin 6) connects the data receiver DI of transmitting terminal RS485 transceiving chip U11, and connects the positive supply output of transmitting terminal DC/DC power supply chip U13 through a pull-up resistor R11;
Described transmitting terminal RS485 transceiving chip U11 is arranged to sending mode, is about to its transmitting-receiving control end
, DE is connected to high level, is connected to a terminal resistance R12 between two output terminals A, the B;
As shown in Figure 3, described RS485 receiving circuit 3 comprises receiving terminal RS485 transceiving chip U21, receiving terminal optical coupling chip U22, receiving terminal DC/DC power supply chip U23;
The power input of described receiving terminal DC/DC power supply chip U23 connects external power source;
The input (pin two, 3) of described receiving terminal optical coupling chip U22 connects the data output end R0 of receiving terminal RS485 transceiving chip U21, and be connected in series a current-limiting resistance R21, its output (pin 6) connects the input that synchronised clock receives module 4, and connects the positive supply output of transmitting terminal DC/DC power supply chip U23 through a pull-up resistor R23;
Described receiving terminal RS485 transceiving chip U21 is configured to receive pattern, is about to its transmitting-receiving control end
DE is connected to low level, is connected to a terminal resistance R22 between two input A, B;
Among the utility model embodiment, the model of described transmitting terminal RS485 transceiving chip U11, receiving terminal RS485 transceiving chip U21 is SN65176B, and its transmission rate is 10Mbps; The model of described transmitting terminal optical coupling chip U12, receiving terminal optical coupling chip U22 is 6N137; Described transmitting terminal DC/DC power supply chip U13 isolates for transmitting terminal RS485 transceiving chip U11, transmitting terminal optical coupling chip U12 provide power supply, and described receiving terminal DC/DC power supply chip U23 isolates for receiving terminal RS485 transceiving chip U21, receiving terminal optical coupling chip U22 provide power supply.
The operation principle of the utility model embodiment is as follows:
Synchronised clock sends module 1 output clock sync signal, this clock sync signal inputs to transmitting terminal RS485 transceiving chip U11 after transmitting terminal optical coupling chip U12 light-coupled isolation, transmitting terminal RS485 transceiving chip U11 passes through the synchronizing signal of data receiver DI reception through light-coupled isolation, and it is exported after Transistor-Transistor Logic level converts the RS485 differential level to;
The clock sync signal with the differential mode input of receiving terminal RS485 transceiving chip U21 receiving end/sending end RS485 transceiving chip U11 output, and convert it to Transistor-Transistor Logic level from the RS485 differential level and export receiving terminal optical coupling chip U22 to, receiving terminal optical coupling chip U22 carries out exporting synchronised clock to after the light-coupled isolation to the signal of receiving and receives module 4.
Claims (3)
1. the clock sync signal transmission circuit is characterized in that: comprise a synchronised clock transmitting element and a plurality of synchronised clock receiving element;
Described synchronised clock transmitting element comprises synchronised clock transmission module, is used for Transistor-Transistor Logic level is converted to the RS485 transtation mission circuit of RS485 differential level, and described synchronised clock sends the module connection and also exports Transistor-Transistor Logic level to the RS485 transtation mission circuit;
Described synchronised clock receiving element comprises synchronised clock reception module, is used for the RS485 differential level is converted to the RS485 receiving circuit of Transistor-Transistor Logic level, and described RS485 receiving circuit connects and output Transistor-Transistor Logic level to synchronised clock receives module;
Described RS485 transtation mission circuit connects and exports the RS485 differential level to each RS485 receiving circuit.
2. circuit according to claim 1 is characterized in that: described RS485 transtation mission circuit comprises transmitting terminal RS485 transceiving chip, transmitting terminal optical coupling chip, transmitting terminal DC/DC power supply chip;
The power input of described transmitting terminal DC/DC power supply chip connects external power source;
The input of described transmitting terminal optical coupling chip connects the output that synchronised clock sends module, and be connected in series a current-limiting resistance, its output connects the data receiver of transmitting terminal RS485 transceiving chip, and connects the positive supply output of transmitting terminal DC/DC power supply chip through a pull-up resistor;
Described transmitting terminal RS485 transceiving chip is arranged to sending mode, is connected to a terminal resistance between two output.
3. circuit according to claim 1 is characterized in that: described RS485 receiving circuit comprises receiving terminal RS485 transceiving chip, receiving terminal optical coupling chip, receiving terminal DC/DC power supply chip;
The power input of described receiving terminal DC/DC power supply chip connects external power source;
The input of described receiving terminal optical coupling chip connects the data output end of receiving terminal RS485 transceiving chip, and be connected in series a current-limiting resistance, its output connects the input that synchronised clock receives module, and connects the positive supply output of transmitting terminal DC/DC power supply chip through a pull-up resistor;
Described receiving terminal RS485 transceiving chip is configured to receive pattern, is connected to a terminal resistance between two input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020232205XU CN201708806U (en) | 2010-06-21 | 2010-06-21 | Clock synchronous signal transmission circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020232205XU CN201708806U (en) | 2010-06-21 | 2010-06-21 | Clock synchronous signal transmission circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201708806U true CN201708806U (en) | 2011-01-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201020232205XU Expired - Lifetime CN201708806U (en) | 2010-06-21 | 2010-06-21 | Clock synchronous signal transmission circuit |
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| Country | Link |
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| CN (1) | CN201708806U (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102221818A (en) * | 2011-05-24 | 2011-10-19 | 国网电力科学研究院 | Transmission method for converting pulse time signals into differential bus signals by GPS (global positioning system) |
| CN109358256A (en) * | 2018-12-20 | 2019-02-19 | 上海欧秒电力监测设备有限公司 | The arrester on-line monitoring system of synchronized sampling is realized in RS485 communication |
| CN109557501A (en) * | 2019-01-31 | 2019-04-02 | 广东电网有限责任公司 | A kind of centralized time dissemination system for electric energy meter automatic calibrator |
| CN112180813A (en) * | 2020-10-22 | 2021-01-05 | 湖南中车时代通信信号有限公司 | Hard wire synchronous processing device and control system |
| CN113708879A (en) * | 2021-09-10 | 2021-11-26 | 北京广利核***工程有限公司 | Distributed system's time synchronization system |
-
2010
- 2010-06-21 CN CN201020232205XU patent/CN201708806U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102221818A (en) * | 2011-05-24 | 2011-10-19 | 国网电力科学研究院 | Transmission method for converting pulse time signals into differential bus signals by GPS (global positioning system) |
| CN109358256A (en) * | 2018-12-20 | 2019-02-19 | 上海欧秒电力监测设备有限公司 | The arrester on-line monitoring system of synchronized sampling is realized in RS485 communication |
| CN109358256B (en) * | 2018-12-20 | 2021-09-03 | 上海欧秒电力监测设备有限公司 | Lightning arrester on-line monitoring system for realizing synchronous sampling in RS485 communication |
| CN109557501A (en) * | 2019-01-31 | 2019-04-02 | 广东电网有限责任公司 | A kind of centralized time dissemination system for electric energy meter automatic calibrator |
| CN112180813A (en) * | 2020-10-22 | 2021-01-05 | 湖南中车时代通信信号有限公司 | Hard wire synchronous processing device and control system |
| CN113708879A (en) * | 2021-09-10 | 2021-11-26 | 北京广利核***工程有限公司 | Distributed system's time synchronization system |
| CN113708879B (en) * | 2021-09-10 | 2024-03-26 | 北京广利核***工程有限公司 | Time setting system of distributed system |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20110112 |