CN205946319U - Circuit board structure - Google Patents
Circuit board structure Download PDFInfo
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- CN205946319U CN205946319U CN201620822470.0U CN201620822470U CN205946319U CN 205946319 U CN205946319 U CN 205946319U CN 201620822470 U CN201620822470 U CN 201620822470U CN 205946319 U CN205946319 U CN 205946319U
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- hole
- metallize
- circuit board
- board structure
- layer
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Abstract
The utility model provides a circuit board structure, it is including metallizing insulation substrate, chemical plating kind sublayer and the patterned circuit layer. The insulation substrate that can metallize includes lower surface, through -hole and a plurality of circuit recess of upper surface, relative upper surface, and wherein the through -hole runs through the insulation substrate that can metallize, and the circuit recess sets up respectively in upper surface and lower surface. Chemical plating kind sublayer covers the inner wall of circuit recess and through -hole. The the patterned circuit layer sets up on chemical plating kind sublayer, and the the patterned circuit layer is packed the circuit recess and is covered the inner wall of through -hole at least. The utility model discloses effectively simplified circuit board structure's technology step, promoted technology efficiency, also can avoid simultaneously having the problem that the photoresist layer is difficult to to clear away now, therefore can promote circuit board structure's technology yield.
Description
Technical field
This utility model is related to a kind of circuit board structure, more particularly, to a kind of circuit board structure with embedded line.
Background technology
Wiring board techniques now have been developed in buried circuit board (embedded circuit board), and this line
Road plate has buried circuit structure (structure with embedded circuit).Specifically, buried circuit board
Feature be its surface cabling be interior be embedded in dielectric layer, rather than protrude from the surface of dielectric layer.
In general, the technique of the known circuit board structure with embedded line is first to provide to be coated with a layers of copper
Substrate.Then, coating one patterning photoresist layer, in layers of copper, wherein patterns the layers of copper of photoresist layer expose portion.Then, to quilt
The part layers of copper exposing is electroplated to form a line layer.Remove patterning photoresist design layer afterwards again.Then half is solid
Change film (prepreg) to be pressed on line layer, make to be embedded in line layer in semi-solid preparation film, finally removing the cu layer and base again
Plate has the circuit board structure of embedded line known to completing.However, above-mentioned processing step is various and considerably complicated, and scheme
The residue of case photoresist layer is difficult to clean off, and also can affect the process yields of circuit board structure.
Utility model content
This utility model provides a kind of circuit board structure, and its technique is relatively simple and process yields are higher.
Circuit board structure of the present utility model include first can metallize insulated substrate, the first chemical plating Seed Layer, first
Patterned line layer, second can metallize insulated substrate, the second chemical plating Seed Layer and the second patterned line layer.First can
Metallization insulated substrate includes upper surface, the lower surface of opposing upper, first through hole and multiple first line groove, wherein
First through hole runs through first and can metallize insulated substrate, and first line groove is respectively arranged at upper surface and lower surface.First change
Learn the inwall that plating sublayer covers first line groove and first through hole.First patterned line layer is arranged at the first chemical plating
In sublayer, and the first patterned line layer is filled first line groove and is at least covered the inwall of first through hole.Second can metal
Change insulated substrate and include the second through hole and multiple second line groove, wherein said second through hole runs through described second can metal
Change insulated substrate, the plurality of second line groove is arranged at second and can metallize on insulated substrate.Second chemical plating Seed Layer
Cover the inwall of the plurality of second line groove and described second through hole.Second patterned line layer is arranged at described second change
Learn in plating sublayer, and described second patterned line layer is filled the plurality of second line groove and at least covered described second
The inwall of through hole.
In an embodiment of the present utility model, above-mentioned first line groove at least one with first through hole even
Logical.
In an embodiment of the present utility model, above-mentioned the second line groove at least one with the second through hole even
Logical.
In an embodiment of the present utility model, the above-mentioned outer surface of the first patterned line layer and corresponding upper surface
And lower surface copline.
In an embodiment of the present utility model, the second above-mentioned patterned line layer is arranged at second and can metallize insulation
The surface of substrate, the outer surface of the second patterned line layer and second can metallize the surface copline of insulated substrate.
In an embodiment of the present utility model, above-mentioned first line groove, the second line groove, first through hole and the
The inwall of two through holes is smooth surface.
In an embodiment of the present utility model, above-mentioned circuit board structure also includes filling material, and it is filled in first and leads to
In hole and the second through hole.
Based on above-mentioned, this utility model forms multiple line groove and through hole on the surface that can metallize insulated substrate,
Chemical plating Seed Layer is being formed in the surface of the insulated substrate that can metallize by chemical plating process, afterwards, chemical plating just can be utilized
Seed Layer carries out electroplating technology as conductive path, to form the patterned line layer being filled in line groove and through hole.Cause
This, this utility model is effectively simplified the processing step of circuit board structure, and lifting process efficiency, additionally, this utility model also may be used
Avoid the problem that known photoresist layer is difficult to clean off, thus the process yields of circuit board structure can be lifted.
It is that features described above of the present utility model and advantage can be become apparent, special embodiment below, and coordinate accompanying drawing
It is described in detail below.
Brief description
Figure 1A to Fig. 1 G is a kind of schematic diagram of the circuit board structure according to an embodiment of the present utility model；
Fig. 2 is a kind of schematic diagram of the circuit board structure according to another embodiment of the present utility model.
Reference：
100、100a：Circuit board structure
110：First can metallize insulated substrate
112：Upper surface
114：Lower surface
116：First through hole
118：First line groove
120：First chemical plating Seed Layer
130：Metal level
132：First patterned line layer
140：Filling material
150：Second can metallize insulated substrate
156：Second through hole
158：Second line groove
160：Second chemical plating Seed Layer
172：Second patterned line layer
Specific embodiment
About of the present utility model aforementioned and other technology contents, feature and effect, each in following cooperation refer to the attached drawing
In the detailed description of embodiment, can clearly present.The direction term being previously mentioned in following examples, for example：" on ",
D score, "front", "rear", "left", "right" etc., are only the directions with reference to attached drawings.Therefore, the direction term of use is used to
Bright, and be not used for limiting this utility model.And, in following examples, same or analogous assembly will be using identical
Or similar label.
Figure 1A to Fig. 1 G is a kind of schematic diagram of the circuit board structure according to an embodiment of the present utility model.The present embodiment
The manufacture method of circuit board structure may include the following step.First, refer to Figure 1A, provide first can metallize insulated substrate
110, it includes the lower surface 114 of upper surface 112, opposing upper 112.In the present embodiment, first can metallize insulation base
The material of plate 110 includes polyimides (polyimide, PI).
Then, refer to Figure 1B, form at least one first through hole 116 and can metallize on insulated substrate 110 in first.At this
In embodiment, first through hole 116 runs through first and can metallize insulated substrate 110 to connect upper surface 112 and lower surface 114.Tool
For body, the method forming first through hole 116 may include laser drill or machine drilling, and certainly, the present embodiment is only in order to illustrate
Illustrate, this utility model is not intended to limit quantity and the forming method of first through hole 116.
Then, refer to Fig. 1 C, form multiple first line grooves 118 and can metallize on insulated substrate 110 in first.The
One line groove 118 is respectively arranged at first and can metallize the upper surface 112 of insulated substrate 110 and lower surface 114.And, the
At least one of one line groove 118 is connected with first through hole 116.Specifically, form the side of first line groove 118
Method may include laser ablation, and certainly, only in order to illustrate, this utility model is not intended to limit first line groove to the present embodiment
118 quantity, configuration mode and forming method.And, in the present embodiment, first line groove 118 and first through hole 116
Inwall is all smooth surface.
Then, refer to Fig. 1 D, by chemical plating process, can metal in first to form the first chemical plating Seed Layer 120
Change on insulated substrate 110.Specifically, the comprehensive covering first of the first chemical plating Seed Layer 120 can be metallized insulated substrate 110
Upper surface 112 and lower surface 114, and cover the inwall of first line groove 118 and first through hole 116.In the present embodiment,
Chemical plating process is the surface deposited plating layer reacting the insulated substrate 110 that can metallize first using chemistry redox.
In the present embodiment, the material of the first chemical plating Seed Layer 120 include nickel that is to say, that the present embodiment first
Chemical plating Seed Layer 120 can be chemical Ni-plating layer.Specifically, chemical nickel plating is with reducing agent, the nickel ion in solution to be reduced
It is deposited on the surface with catalysis activity.For example, the present embodiment can for example first by insulated substrate through special activation
And sensitized treatment, can be metallized insulated substrate 110 with forming first.So, chemical plating process may include and first can metallize
Insulated substrate 110 is immersed in the mixed solution being for example made into nickel sulfate, sodium dihydric hypophosphite, sodium acetate and boric acid etc., makes
Its certain acidity and at a temperature of change, allow the nickel ion in solution to be reduced to atom and be deposited on by sodium dihydric hypophosphite
First can metallize insulated substrate 110 surface on and form the first chemical plating Seed Layer 120 as shown in figure ip.
Then, refer to Fig. 1 E, electroplating technology is carried out as conductive path using the first chemical plating Seed Layer 120, to be formed
Metal level 130 as referring to figure 1e, wherein, the material of metal level 130 includes copper, and its comprehensive covering the first chemical plating seed
Layer 120, and fill first through hole 116 and first line groove 118.
Then, refer to Fig. 1 F, by microetch technique, will be above the first upper surface 112 that can metallize insulated substrate 110
And the partial metal layers 130 of lower surface 114 and the first chemical plating Seed Layer 120 remove, to form as shown in Figure 1 F first
Patterned line layer 132, wherein, the first patterned line layer 132 is arranged in the first chemical plating Seed Layer 120, and the first figure
Case line layer 132 is filled first line groove 118 and is at least covered the inwall of first through hole 116.In the present embodiment, first
The outer surface of patterned line layer 132 and corresponding upper surface 112 and lower surface 114 copline, and the first patterned line layer
132 fill up first through hole 116 and first line groove 118.
Then, refer to Fig. 1 G, setting second insulated substrate 150 that can metallize can metallize insulated substrate 110 in first
On.In the present embodiment, second insulated substrate 150 that can metallize is to be stacked at the first following table that can metallize insulated substrate 110
Face 114, however, the present embodiment is only in order to illustrate, in other embodiments, second insulated substrate 150 that can metallize also may be used
It is stacked at the first upper surface 112 that can metallize insulated substrate 110, this utility model is not limited thereto.In the present embodiment,
With first, second material that can metallize insulated substrate 150 can metallize that insulated substrate 110 is identical, its material may also comprise poly-
Acid imide.
Then, repeat aforesaid processing technology, for example, form the second through hole 156 and multiple second line groove 158
Can metallize insulated substrate 150 in second, and the second through hole 156 runs through second and can metallize insulated substrate 150, the second circuit is recessed
Groove 158 be arranged at second can metallize insulated substrate 150 surface on, and at least one of the second line groove 158 with
Second through hole 156 connects.In the present embodiment, the second through hole 156 can be formed by laser drill, the second line groove 158
Can be formed by laser ablation.Therefore, the second line groove and the inwall of the second through hole can be smooth surface.
Afterwards, then by chemical plating process form the second chemical plating Seed Layer 160 so as to cover the second line groove
158 and second through hole 156 inwall, then by electroplating technology formed the second patterned line layer 172 in the second chemical plating seed
On layer 160, and the second patterned line layer 172 is filled the second line groove 158 and is at least covered the interior of described second through hole 156
Wall.In the present embodiment, the second patterned line layer 172 is arranged at the second surface (under for example that can metallize insulated substrate 150
Surface, but this utility model is not limited thereto), the outer surface of the second patterned line layer 172 then can be able to metallize with second
This surface copline of insulated substrate 150.So, that is, substantially form the circuit board structure 100 of the present embodiment.
For structure, circuit board structure 100 include as shown in Figure 1 G first can metallize insulated substrate 110, first change
Learn plating sublayer 120, the first patterned line layer 132, second can metallize insulated substrate 150, the second chemical plating Seed Layer 160
And second patterned line layer 172.First insulated substrate 110 that can metallize includes upper surface 112, opposing upper 112
Lower surface 114, at least one first through hole 116 and multiple first line groove 118, wherein, first through hole 116 runs through first can
Metallization insulated substrate 110, and first line groove 118 is then respectively arranged at the first upper table that can metallize insulated substrate 110
Face 112 and lower surface 114.First chemical plating Seed Layer 120 covers the inwall of first line groove 118 and first through hole 116.The
One patterned line layer 132 is arranged in the first chemical plating Seed Layer 120, and the first patterned line layer 132 filling First Line
The inwall of road groove 118 at least covering first through hole 116.In the present embodiment, the first patterned line layer 132 fills up first
Line groove 118 and first through hole 116, and the outer surface of the first patterned line layer 132 and corresponding upper surface 112 and following table
Face 114 copline.At least one of first line groove 118 is connected with first through hole 116, with by the first patterned lines
Road floor 132 is electrically connected.
Second insulated substrate 150 that can metallize includes the second through hole 156 and multiple second line groove 158, wherein institute
State the second through hole 156 and run through second and can metallize insulated substrate 150.Second line groove 158 is arranged at second and can metallize absolutely
On edge substrate 150.Second chemical plating Seed Layer 160 covers the inwall of the second line groove 158 and the second through hole 156.Second figure
Case line layer 172 is arranged in the second chemical plating Seed Layer 160, and the second patterned line layer 172 filling the second circuit is recessed
Groove 158 simultaneously at least covers the inwall of the second through hole 156.
It should be noted that, the circuit board structure 100 of the present embodiment only show two-layer can metallize insulated substrate 110, can
Metallization insulated substrate 150 and three pattern layers line layers.However, in other embodiments, circuit board structure can also be by
Structure shown in multiple Fig. 1 F overlies one another and forms, and, second can metallize insulated substrate 150 also can on single surface or
Two surfaces relatively are all provided with patterned line layer.This utility model is not intended to limit folded structure substrate and the patterning of circuit board structure
The quantity of line layer.
Fig. 2 is a kind of schematic diagram of the circuit board structure according to another embodiment of the present utility model.In this mandatory declaration
, the circuit board structure 100 of the circuit board structure 100a and Fig. 1 G of the present embodiment is similar, and therefore, the present embodiment is continued to use aforementioned
The reference numerals of embodiment and partial content, wherein adopt the identical or approximate assembly that is denoted by the same reference numerals, and omit
The explanation of constructed content.Explanation with regard to clipped refers to previous embodiment, and it is no longer repeated for the present embodiment.
Refer to Fig. 2, the difference below for the circuit board structure 100 of circuit board structure 100a and Fig. 1 G of the present embodiment is said
Bright.
In the present embodiment, circuit board structure 100a also includes filling material 140.First patterned line layer 132 and
Two patterned line layer 172 are only covered each by first through hole 116 and the inwall of the second through hole 156.Therefore, filling material 140 is used
To fill up in the space do not filled up by the first patterned line layer 132 in first through hole 116 and the second through hole 156 not by
The space that two patterned line layer 172 are filled up.For example, filling material 140 may include resin, filling ink or conductive paste
Deng.Certainly, only in order to illustrate, this utility model is not intended to limit material and the first through hole of filling material 140 to the present embodiment
116 and second through hole 156 form.
Similarly, the circuit board structure 100a of the present embodiment only show two-layer can metallize insulated substrate 110, can metal
Change insulated substrate 150 and three pattern layers line layers.However, in other embodiments, circuit board structure of the present utility model
Can be that structure shown in multiple Fig. 2 overlies one another and forms, and, second can metallize insulated substrate 150 also can be single
Surface or relatively two surfaces are all provided with patterned line layer.This utility model is not intended to limit the folded structure substrate of circuit board structure
And the quantity of patterned line layer.
In sum, this utility model forms multiple line groove and through hole on the surface that can metallize insulated substrate,
Chemical plating Seed Layer is being formed in the surface of the insulated substrate that can metallize by chemical plating process, afterwards, chemical plating just can be utilized
Seed Layer carries out electroplating technology as conductive path, to form the patterned line layer being filled in line groove and through hole.Cause
This, this utility model is effectively simplified the processing step of circuit board structure, lifting process efficiency.In addition, this utility model
Also the problem that known photoresist layer is difficult to clean off can be avoided, thus the process yields of circuit board structure can be lifted.
Finally it should be noted that：Various embodiments above is only in order to illustrating the technical solution of the utility model, rather than it is limited
System；Although being described in detail to this utility model with reference to foregoing embodiments, those of ordinary skill in the art should
Understand：It still can be modified to the technical scheme described in foregoing embodiments, or to wherein some or all of
Technical characteristic carries out equivalent；And these modifications or replacement, do not make the essence of appropriate technical solution depart from this practicality new
The scope of type each embodiment technical scheme.
Claims (7)
1. a kind of circuit board structure is it is characterised in that include：
First can metallize insulated substrate, including upper surface, the lower surface of relatively described upper surface, first through hole and multiple
One line groove, wherein said first through hole runs through described first and can metallize insulated substrate, the plurality of first line groove
It is respectively arranged at described upper surface and described lower surface；
First chemical plating Seed Layer, covers the inwall of the plurality of first line groove and described first through hole；
First patterned line layer, is arranged in described first chemical plating Seed Layer, and described first patterned line layer filling
The plurality of first line groove simultaneously at least covers the inwall of described first through hole；
Second can metallize insulated substrate, and including the second through hole and multiple second line groove, wherein said second through hole passes through
Wear described second can metallize insulated substrate, the plurality of second line groove is arranged at second and can metallize on insulated substrate；
Second chemical plating Seed Layer, covers the inwall of the plurality of second line groove and described second through hole；And
Second patterned line layer, is arranged in described second chemical plating Seed Layer, and described second patterned line layer filling
The plurality of second line groove simultaneously at least covers the inwall of described second through hole.
2. circuit board structure according to claim 1 it is characterised in that the plurality of first line groove at least within
One of connect with described first through hole.
3. circuit board structure according to claim 1 it is characterised in that the plurality of second line groove at least within
One of connect with described second through hole.
4. circuit board structure according to claim 1 it is characterised in that the outer surface of described first patterned line layer with
Corresponding described upper surface and described lower surface copline.
5. circuit board structure according to claim 1 it is characterised in that described second patterned line layer be arranged at described
Second surface that can metallize insulated substrate, the outer surface of described second patterned line layer can metallize insulation with described second
The described surface copline of substrate.
6. circuit board structure according to claim 1 is it is characterised in that the plurality of first line groove, the plurality of
Second line groove, described first through hole are smooth surface with the inwall of described second through hole.
7. circuit board structure according to claim 1 is it is characterised in that also include filling material, it is filled in described first
In through hole and described second through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620822470.0U CN205946319U (en) | 2016-07-29 | 2016-07-29 | Circuit board structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620822470.0U CN205946319U (en) | 2016-07-29 | 2016-07-29 | Circuit board structure |
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| Publication Number | Publication Date |
|---|---|
| CN205946319U true CN205946319U (en) | 2017-02-08 |
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ID=57924873
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620822470.0U Active CN205946319U (en) | 2016-07-29 | 2016-07-29 | Circuit board structure |
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| Country | Link |
|---|---|
| CN (1) | CN205946319U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107666765A (en) * | 2016-07-29 | 2018-02-06 | 同扬光电（江苏）有限公司 | Circuit board structure |
-
2016
- 2016-07-29 CN CN201620822470.0U patent/CN205946319U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107666765A (en) * | 2016-07-29 | 2018-02-06 | 同扬光电（江苏）有限公司 | Circuit board structure |
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| GR01 | Patent grant |