CN205487356U - Reinforcing memory cell writes static RAM of ability - Google Patents
Reinforcing memory cell writes static RAM of ability Download PDFInfo
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- CN205487356U CN205487356U CN201620269489.7U CN201620269489U CN205487356U CN 205487356 U CN205487356 U CN 205487356U CN 201620269489 U CN201620269489 U CN 201620269489U CN 205487356 U CN205487356 U CN 205487356U
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Abstract
The utility model provides a reinforcing memory cell writes static RAM of ability, it is empty through floating the memory cell earthing terminal when the write operation under the prerequisite that does not influence memory cell storage data's ability when keeping with the read operation, break among the memory cell positive feedbacks between two cross coupling phase inverters to improve memory cell's the ability of writing. It includes control circuit and decoder in advance, bit line precharge and balanced device, sensitive amplifier and write driver, word line decoder and driver, NMOS electric current source, storage array, when the write operation, to by the inrow memory cell that is chosen in the storage array, the word line signal is drawn high, writes the word line inverted signal and draws lowly, and turn -off in NMOS electric current source, and the virtual earth floats in vain, is used for the positive feedback between two cross coupling's of storage phase inverter to be interrupted among the memory cell, and memory cell is rewritten, at the falling edge of word line signal, memory cell gets into and keeps the mode.
Description
Technical field
This utility model relates to SRAM design field, is specially one enhancing memory element and writes
The SRAM of ability.
Background technology
SRAM is as the important memory element in integrated circuit, due to its high-performance, high
Reliability, the advantage such as low-power consumption is widely used in high-performance calculation device system (CPU), sheet is
System (SOC), handheld device etc. calculates field.
Along with the continuous evolution of Technology, constantly reducing of dimensions of semiconductor devices, this locality and the overall situation
Process deviation, the performance to integrated circuit, the impact that reliability causes is increasing.Meanwhile, electricity
The also reliability to circuit that constantly declines of source voltage proposes bigger challenge.SRAM is deposited
The write capability of storage unit, refers to when write operation, and when wordline is opened, write driver drives bit line to rewrite and deposits
The ability of storage unit.
Such as Figure of description 2, Fig. 2 is traditional memory element design principle figure.This memory element 200
It is made up of four transistors, respectively first and second NMOS transfer tube 205,206, first and second time
Draw nmos pass transistor 201,202 and first and second pullup PMOS transistor 203,204.Wordline
The 115 grid ends connecing first and second NMOS transfer tube 205,206.Bit line 220 meets a NMOS and passes
The source of defeated pipe 205.Bit line anti-221 connects the source of the 2nd NMOS transfer tube 206.Memory element
Data 222 connect on the first pulldown NMOS transistor the 201, the 2nd NMOS transfer tube 205, first
Draw the drain terminal of PMOS transistor 203；Connect the second pulldown NMOS transistor 202, second to pull up
The grid end of PMOS transistor 204.Memory cell data anti-223 connects the second pulldown NMOS transistor
202, the drain terminal of the second pullup PMOS transistor 204；Connect the first pulldown NMOS transistor 201,
The grid end of the first pullup PMOS transistor 203.Supply voltage 224 connects first and second pull-up PMOS
The source of transistor 203,204.Ground 225 connects first and second pulldown NMOS transistor 201,202
Source.
Due to the source ground connection of first and second pulldown NMOS transistor 201,202, by first and second time
Nmos pass transistor 201,202 and first and second pullup PMOS transistor 205,206 is drawn to form
Cross-linked phase inverter joins end to end formation positive feedback, is therefore difficult to be written over.When write operation, the
One or two NMOS transfer tubes 205/206 must be better than first and second pullup PMOS transistor
203/204, data 222 and the data anti-223 of memory element 200 could be rewritten.Along with supply voltage
Decline, and the threshold voltage variation of transistor that process deviation causes is increasing, rewrite memory element
More and more difficult.Under some technique and voltage conditions, write operation failure can be caused, thus reduce whole
The yield of memorizer.
Therefore, when not affecting holding and read operation on the premise of the ability of storage unit stores data,
During write operation, strengthen memory element write capability, be the most helpful for improving the yield of whole memorizer
's.
Utility model content
For problems of the prior art, this utility model provides one to strengthen memory element write capability
SRAM, keep and during read operation before the ability of storage unit stores data not affecting
Put, by when write operation by memory element earth terminal floating, interrupt in memory element two and intersect coupling
Close the positive feedback between phase inverter, thus improve the write capability of memory element.
This utility model is to be achieved through the following technical solutions:
A kind of SRAM strengthening memory element write capability, including control circuit and pre-decode
Device, bit line precharge and equalizer, sense amplifier and write driver, word-line decoder and driver,
NMOS current source, storage array；Control circuit and decoder are by a plurality of row pre-decode and a basis
Write enable inverted signal and connect word-line decoder and driver；Control circuit and decoder are also by a plurality of row
Control signal connects bit line precharge and equalizer, sense amplifier and write driver；Control circuit with translate
Code device input link address signal, write enable signal is anti-, chip selection signal is anti-and clock signal；Bit line
Precharge is connected with the input/output terminal of equalizer, sense amplifier and write driver writes data and reading
According to；Word-line decoder and driver are connected storage array by a plurality of word-line signal, word-line decoder with drive
Dynamic device connects NMOS current source also by a plurality of write word line inverted signal；NMOS current source is by a plurality of
Virtual earth connects storage array；Storage array connects bit line precharge and equalizer, sensitive by multiple bit lines
Amplifier and write driver.
Preferably, storage array is made up of several memory element, and the quantity of memory element is equal to memorizer
Middle word length line number is multiplied by bit wide columns；Wherein memory element is by two cross coupling inverters for storage
Constitute with two NMOS transfer tubes for read-write, drop-down in two cross coupling inverters
The source of nmos pass transistor connects virtual earth, and same line storage unit shares a virtual earth.
Preferably, described NMOS current source is made up of several nmos pass transistors, NMOS crystal
The quantity of pipe is equal to word length number in memorizer；The drain terminal correspondence of each nmos pass transistor connects one
The virtual earth of line storage unit, grid termination write word line inverted signal, source ground connection.
Preferably, described word-line decoder and driver, by several word-line decoders and driver submodule
Block forms, and the quantity of word-line decoder and driver submodule is equal to word length number in memorizer；Described word
Line decoder and driver submodule by word-line decoder submodule, a phase inverter and one two input or
Door composition；The output word-line signal that the input of phase inverter connects word-line decoder submodule is anti-, and output connects wordline
Signal；Two inputs or an input of door connect locally-written enable inverted signal, and another input connects that wordline is counter to be believed
Number, output connects write word line inverted signal.
Compared with prior art, this utility model has a following useful technique effect:
Memorizer described in the utility model is storage unit stores data when not affecting holding and read operation
On the premise of ability, the NMOS current source being correspondingly arranged by line storage unit each with storage array
When write operation by memory element earth terminal floating, interrupt in memory element between two cross coupling inverters
Positive feedback, thus improve the write capability of memory element.This utility model is permissible by SRAM
The minimum supply voltage of writing of normal work reduces 360 millivolts.
Accompanying drawing explanation
Fig. 1 is the SRAM structural schematic block diagram described in this utility model example.
Fig. 2 is memory element design principle structure chart in prior art.
Fig. 3 is the memory element design principle structure chart described in this utility model example.
Fig. 4 is the storage that the NMOS current source described in this utility model example and a line share virtual earth
Unit design principle structure chart.
Fig. 5 is the word-line decoder described in this utility model example and driver design submodule principle
Figure.
Detailed description of the invention
Below in conjunction with specific embodiment, this utility model is described in further detail, described in be to this
The explanation of utility model rather than restriction.
As it is shown in figure 1, a kind of SRAM bag strengthening memory element write capability of this utility model
Include, control circuit and Pre-decoder 101, bit line precharge and equalizer, sense amplifier and write driving
Device 102, word-line decoder and driver 103, NMOS current source 104, and storage array
105。
Control circuit and decoder 101 are by a plurality of row pre-decode 113 and a locally-written enable inverted signal
114 connect word-line decoder and driver 103；Control circuit and decoder 101 are also by a plurality of row control
Signal 112 processed connects bit line precharge and equalizer, sense amplifier and write driver 102；
Word-line decoder is connected storage array 105, word with driver 103 by a plurality of word-line signal 115
Line decoder is connected NMOS current source with driver 103 also by a plurality of write word line inverted signal 116
104；
NMOS current source 104 connects storage array 105 by a plurality of virtual earth 117；
Storage array 105 connects bit line precharge and equalizer, sense amplifier by multiple bit lines 118
With write driver 102.
The write operation method of a kind of SRAM strengthening memory element write capability, at write operation
Time, for the memory element 300 in row selected in storage array 105, word-line signal 115 draws
Height, write word line inverted signal 116 drags down, and NMOS current source 104 turns off, virtual earth 117 floating, storage
In unit 300, the positive feedback between two cross-linked phase inverters of storage is interrupted, memory element
300 are written over；At the end of the trailing edge of word-line signal, i.e. write operation, write word line inverted signal 116 is drawn
Height, NMOS current source 104 opens, and virtual earth 117 is pulled to ground, and memory element enters holding pattern.
When keeping pattern and read operation, write word line inverted signal 116 is high, and NMOS current source 104 is opened,
Virtual earth 117 is pulled to ground.
As it is shown on figure 3, memory element 300 is made up of four transistors, respectively first and second
NMOS transfer tube 205,206, first and second pulldown NMOS transistor 201,202 and first,
Two pullup PMOS transistor 203,204.Wordline 115 connect first and second NMOS transfer tube 205,
The grid end of 206.Bit line 220 connects the source of a NMOS transfer tube 205.Bit line anti-221 connects second
The source of NMOS transfer tube 206.Memory cell data 222 connects the first pulldown NMOS transistor
201, the drain terminal of the 2nd NMOS transfer tube the 205, first pullup PMOS transistor 203；Connect second
The grid end of pulldown NMOS transistor the 202, second pullup PMOS transistor 204.Number of memory cells
According to anti-223 leakages connecing second pulldown NMOS transistor the 202, second pullup PMOS transistor 204
End；Connect the grid end of first pulldown NMOS transistor the 201, first pullup PMOS transistor 203.
Supply voltage 224 connects the source of first and second pullup PMOS transistor 203,204.Virtual earth 117 connects
The source of first and second pulldown NMOS transistor 201,202.
First and second pulldown NMOS transistor 201,202 and first and second pullup PMOS transistor
205, the phase inverter cross-couplings of 206 compositions joins end to end, and is responsible for storage memory cell data 222 He
Memory cell data anti-223.
First and second NMOS transfer tube 205,206 is controlled by wordline 115, by bit line 220 and position
The anti-221 pairs of memory cell data 222 of line and memory cell data anti-223 are written and read operation.
As shown in Figure 4, NMOS current source 400 is made up of nmos pass transistor 401, and its drain terminal connects
Virtual earth 117, grid termination write word line inverted signal 116, source ground connection 225.A line shares the storage of virtual earth
Unit 402 is made up of memory element 300 in bit wide Fig. 3, they share same wordline 115 and with
One virtual earth 117.
When keeping pattern and read operation, write word line inverted signal 116 is high, NMOS current source 400
Middle nmos pass transistor 402 is opened, and virtual earth is pulled to ground 117, now in memory element 300 and Fig. 2
Conventional memory cell 200 is identical.When write operation, for selected row 402, word-line signal is drawn high
115, write word line inverted signal drags down 116, and in NMOS current source 400, nmos pass transistor 402 closes
Disconnected, virtual earth floating 117, memory element 300 is responsible between two cross-linked phase inverters of storage
Positive feedback is interrupted, and memory element 300 is easier to be written over.At the trailing edge of word-line signal 115, i.e.
At the end of write operation, anti-116 signals of write word line are drawn high, NMOS crystal in NMOS current source 400
Pipe 402 is opened, and virtual earth 117 is pulled to ground, and memory element 300 enters holding pattern.
As it is shown in figure 5, word-line decoder and driver submodule are by word-line decoder submodule 501, anti-
Phase device 502, two input or door 503 form.The input of phase inverter 502 connects word-line decoder submodule
The output word-line signal anti-510 of 501, output connects wordline 115.One input of two inputs or door connects this
Write enable inverted signal 512, another input connects wordline inverted signal 510, and output connects write word line inverted signal
116。
When keeping, wordline inverted signal 510 is high, and therefore wordline 115 is low, write word line inverted signal
116 is high.
When read operation, for decoding invalid word-line decoder submodule 501, wordline inverted signal 510
For height, therefore wordline 115 is low, and write word line inverted signal 116 is high；Translate for decoding effective wordline
Code device submodule 501, wordline inverted signal 510 is low, and therefore wordline 115 is high, and due to read operation
Time locally-written enable inverted signal 512 be high, therefore write word line inverted signal 116 be height.
When write operation, for decoding invalid word-line decoder submodule 501, wordline inverted signal 510
For height, therefore wordline 115 is low, and write word line inverted signal 116 is high；Translate for decoding effective wordline
Code device submodule 501, wordline inverted signal 510 is low, and therefore wordline 115 is high, and due to read operation
Time locally-written enable inverted signal 512 be low, therefore write word line inverted signal 116 is low.
At the end of write operation, wordline inverted signal 510 is drawn high, and therefore wordline 115 is low, and write word line is anti-
Signal 116 is high.
Claims (4)
1. the SRAM strengthening memory element write capability, it is characterised in that include controlling
Circuit and Pre-decoder (101), bit line precharge and equalizer, sense amplifier and write driver
(102), word-line decoder and driver (103), NMOS current source (104), storage array
(105)；
Control circuit and decoder (101) are by a plurality of row pre-decode (113) and a locally-written enable
Inverted signal (114) connects word-line decoder and driver (103)；Control circuit and decoder (101)
Bit line precharge and equalizer, sense amplifier and write is connected also by a plurality of row control signal (112)
Driver (102)；The input link address signal of control circuit and decoder (101), write enable
Signal is anti-, chip selection signal is anti-and clock signal (110)；
Bit line precharge connects with the input/output terminal of equalizer, sense amplifier and write driver (102)
Connect and write data and read data (111)；
Word-line decoder is connected storage array with driver (103) by a plurality of word-line signal (115)
(105), word-line decoder is connected also by a plurality of write word line inverted signal (116) with driver (103)
NMOS current source (104)；
NMOS current source (104) connects storage array (105) by a plurality of virtual earth (117)；
Storage array (105) connects bit line precharge and equalizer, sensitive by multiple bit lines (118)
Amplifier and write driver (102).
A kind of SRAM strengthening memory element write capability the most according to claim 1,
It is characterized in that, storage array (105) is made up of several memory element (300), memory element
Quantity is multiplied by bit wide columns equal to word length line number in memorizer；Wherein memory element (300) is deposited by being used for
Two cross coupling inverters of storage and two NMOS transfer tubes for reading and writing are constituted, two intersections
The source of the pulldown NMOS transistor in coupled inverters connects virtual earth (117), same line storage unit
(300) virtual earth (117) is shared.
A kind of SRAM strengthening memory element write capability the most according to claim 1,
It is characterized in that, described NMOS current source (104) is made up of several nmos pass transistors,
The quantity of nmos pass transistor is equal to word length number in memorizer；The drain terminal pair of each nmos pass transistor
The virtual earth (117) connecing a line storage unit (300), grid termination write word line inverted signal should be connected
(116), source ground connection.
A kind of SRAM strengthening memory element write capability the most according to claim 1,
It is characterized in that, described word-line decoder and driver (103), by several word-line decoders and driving
Device submodule (500) forms, and the quantity of word-line decoder and driver submodule (500) is equal to storage
Word length number in device；Described word-line decoder and driver submodule (500) are by word-line decoder submodule
Block (501), a phase inverter (502) and one two input or door (503) composition；Phase inverter
(502) the output word-line signal that input connects word-line decoder submodule (501) is anti-(510), output
Connect word-line signal (115)；One input of two inputs or door (503) connects locally-written enable inverted signal
(114), another input connects wordline inverted signal (510), and output connects write word line inverted signal (116).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620269489.7U CN205487356U (en) | 2016-03-31 | 2016-03-31 | Reinforcing memory cell writes static RAM of ability |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620269489.7U CN205487356U (en) | 2016-03-31 | 2016-03-31 | Reinforcing memory cell writes static RAM of ability |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105719689A (en) * | 2016-03-31 | 2016-06-29 | 西安紫光国芯半导体有限公司 | Static random access memory capable of improving writing capacity of storage units as well as write operation method of static random access memory |
| CN111402944A (en) * | 2019-01-02 | 2020-07-10 | 爱思开海力士有限公司 | Memory device with improved program and erase operations and method of operating the same |
| US11880582B2 (en) | 2019-01-02 | 2024-01-23 | SK Hynix Inc. | Memory device having improved program and erase operations and operating method of the memory device |
-
2016
- 2016-03-31 CN CN201620269489.7U patent/CN205487356U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105719689A (en) * | 2016-03-31 | 2016-06-29 | 西安紫光国芯半导体有限公司 | Static random access memory capable of improving writing capacity of storage units as well as write operation method of static random access memory |
| CN111402944A (en) * | 2019-01-02 | 2020-07-10 | 爱思开海力士有限公司 | Memory device with improved program and erase operations and method of operating the same |
| CN111402944B (en) * | 2019-01-02 | 2023-05-16 | 爱思开海力士有限公司 | Memory device having improved program and erase operations and method of operating the same |
| US11880582B2 (en) | 2019-01-02 | 2024-01-23 | SK Hynix Inc. | Memory device having improved program and erase operations and operating method of the memory device |
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