CN105976859A - Static random access memory with ultralow writing power consumption and control method of writing operation of static random access memory - Google Patents
Static random access memory with ultralow writing power consumption and control method of writing operation of static random access memory Download PDFInfo
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- CN105976859A CN105976859A CN201610340529.7A CN201610340529A CN105976859A CN 105976859 A CN105976859 A CN 105976859A CN 201610340529 A CN201610340529 A CN 201610340529A CN 105976859 A CN105976859 A CN 105976859A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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Abstract
The invention relates to a static random access memory with ultralow writing power consumption and a control method of writing operation of the static random access memory. A traditional 6-tube storage unit is changed into a PMOS (P-channel Metal Oxide Semiconductor) tube from an NMOS (N-channel Metal Oxide Semiconductor) transistor and a ground end connected with a previous NMOS pulling-down tube source end is changed into a dummy ground end of an NMOS current source controlled by a writing line opposite WWL_N; the traditional 6-tube storage unit is modified into a voltage type sensitive amplifier; the sensitive amplifier is added into a writing data channel to be used as writing data cache. When writing operation is carried out, the writing data is written to the sensitive amplifier firstly and stored; an amplification line and an alignment line of the sensitive amplifier are discharged and the self amplification capability of the storage unit is utilized; the writing operation of the storage unit can be finished by only very small bit line voltage difference so that bit line overturning power consumption consumed by the writing operation is saved. Compared with traditional bit line full-swing writing operation, the bit line overturning power consumption consumed by single time of the writing operation is reduced by 4.2 times.
Description
Technical field
The present invention relates to SRAM design field, particularly to a kind of ultralow SRAM writing power consumption.
Background technology
SRAM is as the important memory element in integrated circuit, due to its high-performance, high reliability, low-power consumption
Being widely used in high-performance calculation device system (CPU), SOC(system on a chip) (SOC) etc. advantage, handheld device etc. calculates field.
According to the estimation of ITRS ITRS, by 2016, Embedded SRAM area accounts for whole
Calculator system (CPU), the 90% of SOC(system on a chip) (SOC) area.Its power consumption consumed accounts for whole calculator system on sheet
(CPU), the 40% of SOC(system on a chip) (SOC), wherein dynamic power consumption accounts for about 14%.SRAM is write
Operation, usual bit line needs full swing to operate, and has only to, compared to bit line during read operation, the least voltage difference of discharging, sensitive put
For big device small voltage difference is amplified to full swing, the power consumption that write operation consumes is bigger.
Such as Figure of description 2, the SRAM that Fig. 2 is traditional writes data-path circuit design principle figure.This writes data
Path includes multiple 6 transistor memory units, bit line precharge and equalizer, write driver.
Multiple 6 transistor memory unit shared bit line BL and the anti-BL_N of bit line.Assume the load on bit line BL and the anti-BL_N of bit line
Electric capacity is respectively CBL and CBL_N.
Multiple 6 transistor memory units connect bit line by bit line BL and the anti-BL_N of bit line and are pre-charged and equalizer, write driver；
Bit line precharge, equalizer are by 2 precharge PMOS transistor P0, P1 and equilibrium PMOS transistor P2
Composition.Bit line BL connects drain terminal and the source of P2 of P0.The anti-BL_N of bit line connects drain terminal and the drain terminal of P2 of P1.Position
Line precharge inverted signal PRE_N connects the grid end of P0-P2.Supply voltage VCC connects the source of P0, P1.
Write driver is made up of phase inverter I0, tristate inverter I1, I2.The input of write driver connects writes data D, and output is even
Meet bit line BL and the anti-BL_N of bit line.
In conjunction with Fig. 3, traditional SRAM writes the oscillogram of data path so that the operation principle of this circuit to be described.
When keeping pattern, write enable signal WE is low, and write driver is closed.Bit line pre-charge signal PRE_N is low, position
In line precharge, equalizer, 3 PMOS transistor are charged in advance all in conducting state, bit line BL and the anti-BL_N of bit line
Supply voltage VCC.
All of word-line signal WL is low, the most all of 6 transistor memory units be in holding data mode.
When write operation, first, bit line precharge inverted signal PRE_N is drawn high, bit line precharge and 3 PMOS in equalizer
Transistor P0-P2 turns off, bit line BL and bit line anti-BL_N floating.Then, write enable signal WE is high, write driver
Opening, write driver will be write data D and drive to the anti-BL_N of bit line BL and bit line.Its in bit line BL and the anti-BL_N of bit line
In one be maintained at pre-charge level VCC, another by from VCC discharged into ground VSS, this process is not due to from power supply VCC
Extraction electric current, the energy of consumption is 0.Then, 6 selected transistor memory unit wordline WL are drawn high, and write driver is by driving
The data rewriting of storage in 6 transistor memory units that dynamic bit line BL and the anti-BL_N of bit line will choose.When 6 selected pipe storages
When in unit, the data rewriting of storage completes, wordline WL drags down, and 6 selected pipe storages keep its data being written over.So
Rear write enable signal drags down, and write driver is closed, bit line BL and bit line anti-BL_N floating.Then, the anti-letter of bit line precharge
Number PRE_N drags down, 3 PMOS transistor conductings in bit line precharge, equalizer, bit line BL and the anti-BL_N of bit line
Before in, the bit lines for supply voltage VCC is maintained at VCC, and the bit lines for ground VSS is charged to VCC before.
This process extracts electric current from power supply VCC, and the energy of consumption is CBL VCC VCC, i.e. CBL VCC2.After to sum up institute
State, for write operation each time, drive bit line BL and the anti-BL_N of bit line including write driver during write operation, and write operation completes
Time bit line precharge, the equilibrium of equalizer BL_N anti-to bit line BL and bit line and precharge operation, to every pair of bit lines BL and
For the anti-BL_N of bit line, its upset power consumption consumed is, the energy of consumption during write operation adds up line precharge, equilibrium behaviour
The energy consumed when making, i.e. 0+CBL VCC2, for CBL VCC2。
Summary of the invention
In order to reduce write operation consumption, the present invention provides a kind of ultralow SRAM writing power consumption and the control of write operation thereof
Method.
The technical solution of the present invention is as follows:
The ultralow SRAM writing power consumption provided by the present invention, pre-including control circuit and Pre-decoder 101, bit line
Charging and equalizer, write driver 102, word-line decoder and driver 103 and storage array 105, described storage array 105
Including multirow 6 transistor memory unit, it is characterized in that
Two access pipes of each 6 transistor memory units are PMOS transistor, and two NMOS of each 6 transistor memory units are drop-down
Pipe source is connected with the virtual earth end of the NMOS current source 104 controlled by the anti-WWL_N of write word line, and often row 6 transistor memory unit is altogether
Enjoy a NMOS current source 104；
Described SRAM also includes sense amplifier, and described write driver 102 is by sense amplifier and bit line preliminary filling
Electricity is connected with equalizer, and described sense amplifier writes for writing data and caches, then is carried out bit line by sense amplifier
Electric discharge, thus writing full swing small signal difference that data are converted on bit line and being sent to 6 selected transistor memory units
Memory node on.
Above-mentioned sense amplifier includes that PMOS transistor P3, PMOS transistor P4, cross coupling inverter, NMOS are brilliant
Body pipe N30, output phase inverter I3, output phase inverter I4 and sense amplifier precharge and equalizer；
The grid termination read-write of PMOS transistor P3 and PMOS transistor P4 enables anti-RWE_N, described PMOS transistor
The source of P3, drain terminal meet bit line BL respectively and amplify line SL, and the source of described PMOS transistor P4, drain terminal connect respectively
The anti-BL_N of bit line and the amplification anti-SL_N of line；
Described cross coupling inverter is by pulldown NMOS transistor N31, pulldown NMOS transistor N32 and pull-up PMOS
Transistor P31, pullup PMOS transistor P32 form, wherein pulldown NMOS transistor N31 and pull-down NMOS crystal
The source of pipe N32 connects virtual earth, and pullup PMOS transistor P31, the source of pullup PMOS transistor P32 connect supply voltage
The drain terminal of VCC, pulldown NMOS transistor N31 and grid end distinguish the corresponding drain terminal with pullup PMOS transistor P31 and grid
End connects, the most corresponding drain terminal with pullup PMOS transistor P32 of the drain terminal of pulldown NMOS transistor N32 and grid end and
Grid end connects, and has data section between drain terminal and the drain terminal of pullup PMOS transistor P31 of pulldown NMOS transistor N31
Between grid end and the grid end of pullup PMOS transistor P31 of some C, pulldown NMOS transistor N31, there is back end D,
Between grid end and the grid end of pullup PMOS transistor P32 of pulldown NMOS transistor N32, there is back end C ', under
Draw and there are between the drain terminal of nmos pass transistor N32 and the drain terminal of pullup PMOS transistor P32 back end D ', data
Node C is connected with back end C ', and back end D is connected with back end D '；
The input of described back end C and output phase inverter I3 is connected with amplifying line SL_, the outfan of output phase inverter I3
Meet the reading anti-Q_N of data；The input of described back end D ' and output phase inverter I4 is connected with amplifying the anti-SL_N of line, described
The output termination of output phase inverter I4 reads data Q；
The grid termination sense amplifier of described nmos pass transistor N30 enables SAE, and the source of nmos pass transistor N30 connects void
Ground Virtual_VSS<W>；The drain terminal ground connection of nmos pass transistor N30；
The precharge of described sense amplifier includes three PMOS transistor with equalizer, and the grid end of three PMOS transistor is tied altogether
Point, the source of two of which PMOS transistor connects power supply VCC, and drain terminal connects one respectively and amplifies line；Another one PMOS
The drain terminal of transistor and source are connected to two and amplify between line.
Above-mentioned NMOS current source 104 is made up of nmos pass transistor N10, and the drain terminal of nmos pass transistor N10 connects a line 6
The virtual earth end of transistor memory unit, the grid termination anti-WWL_N of write word line, source ground connection VSS.
Above-mentioned control circuit is with decoder 101 by locally-written enable inverted signal LWEN of a plurality of row pre-decode YPD and even
Connect word-line decoder and driver 103, be pre-charged anti-BL_PRE_N and bit line precharge by bit line and equalizer is connected, lead to
Cross the read-write anti-RE_N of enable to be connected with sense amplifier PMOS transistor P3 and sense amplifier PMOS transistor P4, lead to
Cross sense amplifier and be pre-charged the grid end of anti-SA_PRE_N and sense amplifier precharge with three PMOS transistor of equalizer
Connect, by sense amplifier enable SAE and nmos pass transistor N30 grid end is connected, by write enable WE connection write
Driver 102；Described word-line decoder and driver 103 by the anti-WL_N of a plurality of word-line signal and 6 transistor memory units the
One accesses PMOS transistor and second accesses the grid end connection of PMOS transistor, and every word-line signal anti-WL_N correspondence is even
Connect 6 transistor memory units；Described word-line decoder is connected also by a plurality of write word line inverted signal WWL_N with driver 103
Multiple NMOS current sources 104；Every write word line inverted signal WWL_N correspondence connects a NMOS current source 104.
The control method of the ultralow SRAM write operation writing power consumption based on preceding claim, it is characterized in that
Keeping control method during pattern it is:
Write enable signal WE is low, and write driver is closed；
Meanwhile, line precharging signal BL_PRE_N is low, bit line precharge, in equalizer 3 PMOS transistor all in
Conducting state, bit line BL and the anti-BL_N of bit line are charged to supply voltage VCC in advance；
Meanwhile, the anti-WL_N of all of wordline is high, accesses PMOS transistor and turn off in all 6 transistor memory units；
Meanwhile, the anti-WWL_N of all of write word line is high, and all of shared NMOS current source is opened, all of virtual earth
Virtual_VSS is low, the most all of 6 transistor memory units be in holding data mode；
Meanwhile, it is high that read-write enables anti-RWE_N, and sense amplifier input switch PMOS transistor P3, P4 turn off, position
The anti-BL_N of line BL, bit line and amplification line SL, the amplification anti-SL_N of line are isolated；
Meanwhile, it is low that sense amplifier enables SAE, and NMOS current switch N30 turns off；
Meanwhile, it is low for amplify line SL/SL_N being pre-charged anti-SA_PRE_N, and sense amplifier amplifies line precharge and Jun Heng PMOS
Transistor P5-P7 turns on, and amplification line SL, the amplification anti-SL_N of line are maintained at supply voltage VCC, simultaneously virtual earth
Virtual_VSS<W>to be maintained at VCC-Vtn, Vtn be sense amplifier pulldown NMOS transistor N31, nmos pass transistor
The threshold voltage of N32；
Control method when writing data is:
1) the sense amplifier amplification line anti-SA_PRE_N of precharge draws high, and sense amplifier amplifies line and is pre-charged with Jun Heng 3
Individual PMOS transistor turns off, and amplifies line SL and bit line anti-SL_N floating；
2) write enable signal WE is high, and write driver is opened, and write driver will be write data D and drive to amplifying line SL and amplification
The anti-SL_N of line, amplify line SL and amplify in the anti-SL_N of line wherein one be maintained at pre-charge level VCC, another by from
VCC discharges into ground VSS；
3) write enable signal WE drags down, and write driver is closed；Meanwhile, it is high that sense amplifier enables SAE, NMOS electricity
Stream switch N30 opens, virtual earth Virtual_VSS<W>it is pulled to ground VSS；By sense amplifier pulldown NMOS transistor N31,
The cross-couplings of pullup PMOS transistor P31, pullup PMOS transistor P31P32 composition reversely forms positive feedback, will have
Data D of writing of write driver write are saved in amplification line SL and amplify on the anti-SL_N of line；
4) the 6 selected anti-WWL_N of transistor memory unit write word line drag down, and NMOS current source turns off, virtual earth Virtual_VSS
Floating；The anti-WL_N of wordline drags down, and two access PMOS transistor and open, and memory cell data BIT and BITB are by bit line
BL and the anti-BL_N of bit line is charged to supply voltage VCC in advance；
5) the anti-BL_PRE_N of bit line precharge draws high, and bit line precharge turns off with 3 PMOS transistor in equalizer, position
Line BL and bit line anti-BL_N floating；
6) the anti-RWE_N of read-write enable drags down, sense amplifier input switch PMOS transistor P3, PMOS transistor P4
Opening, the anti-BL_N of bit line BL, bit line and amplification line SL, the amplification anti-SL_N of line connect；
If data D of write are 0, then sense amplifier amplifies line SL is low, and it is high for amplifying the anti-SL_N of line；Due to PMOS
Transistor P3, nmos pass transistor N31, nmos pass transistor N30 turn on, and sense amplifier is by amplifying line SL to bit line
BL discharges；And other end, SL_N remains VCC, and PMOS transistor P4 turns on, so the anti-BL_N of bit line protects
Hold at supply voltage VCC；Voltage difference between bit line BL and the anti-BL_N of bit line can pass to store data BIT and the anti-BITB of data
On；
When the voltage difference of bit line BL and the anti-BL_N of bit line arrives the offset voltage Voffset of this sense amplifier, read-write enables
Anti-RWE_N draws high, and sense amplifier input switch PMOS transistor P3, PMOS transistor P4 turn off, bit line BL,
The anti-BL_N of bit line and amplification line SL, the amplification anti-SL_N of line are isolated；Meanwhile, 6 selected transistor memory unit wordline are anti-
WL_N draws high, and accesses PMOS transistor and turn off in 6 selected transistor memory units；Meanwhile, selected memory element
The anti-WWL_N of write word line draws high, and NMOS current source is opened, and virtual earth Virtual_VSS is pulled to ground；Selected storage list
In unit, cross-linked phase inverter passes through positive feedback, the voltage difference between anti-to data BIT and data BITB is amplified to rapidly entirely
The amplitude of oscillation；
If data D of write are 1, then sense amplifier amplifies the anti-SL_N of line is low, and it is high for amplifying line SL；Due to P4,
N32, N30 turn on, and bit line BL_N is discharged by sense amplifier by amplifying the anti-SL_N of line；And other end, SL keeps
For VCC, and P3 conducting, so bit line BL is maintained at supply voltage VCC；Electricity between bit line BL and the anti-BL_N of bit line
Pressure reduction can pass to store on data BIT and the anti-BITB of data；
When the voltage difference of bit line BL and the anti-BL_N of bit line arrives the offset voltage Voffset of this sense amplifier, read-write enables
Anti-RWE_N draws high, and sense amplifier input switch PMOS transistor P3, PMOS transistor P4 turn off, bit line BL,
The anti-BL_N of bit line and amplification line SL, the amplification anti-SL_N of line are isolated；Meanwhile, 6 selected transistor memory unit wordline are anti-
WL_N draws high, and accesses PMOS transistor and turn off in 6 selected transistor memory units；Meanwhile, selected memory element
The anti-WWL_N of write word line draws high, and NMOS current source is opened, and virtual earth Virtual_VSS is pulled to ground.Selected storage list
In unit, cross-linked phase inverter passes through positive feedback, the voltage difference between anti-to data BIT and data BITB is amplified to rapidly entirely
The amplitude of oscillation；
7) at the end of write operation, sense amplifier enables SAE and drags down, and NMOS current switch N30 turns off, and, puts meanwhile
Big line SL/SL_N is pre-charged anti-SA_PRE_N and drags down, and amplifies line SL/SL_N precharge and Jun Heng PMOS transistor P5-P7
Open, amplification line SL and the amplification anti-SL_N of line is charged to supply voltage VCC.
Compared with prior art, advantage is the present invention:
The present invention first will write data and write in sense amplifier and be cached, then by the amplification line of sense amplifier to bit line discharges,
And utilize the amplifying power of memory element self, it is only necessary to the least bit-line voltage is poor, can complete the write operation to memory element,
Save the bit line upset power consumption that write operation is consumed.Compared with traditional bit line full swing write operation, mono-recordable operation is consumed
Bit line upset power consumption have dropped 4.2 times.
Accompanying drawing explanation
Fig. 1 is the SRAM schematic diagram implemented according to the present invention.
The SRAM that Fig. 2 is traditional writes data-path circuit design principle figure.
The SRAM that Fig. 3 is traditional writes the oscillogram of data path.
Fig. 4 is that the SRAM of the present invention writes data-path circuit design principle figure.
Fig. 5 is the oscillogram that the SRAM of the present invention writes data path.
Fig. 6 is the memory element design principle figure that NMOS current source and a line share virtual earth.
Detailed description of the invention
The present invention is by being changed the access pipe of 6 traditional transistor memory units into PMOS transistor by nmos pass transistor, and by former
The ground end that under the NMOS come, trombone slide source is connect changes the virtual earth end of the NMOS current source controlled by the anti-WWL_N of write word line into,
6 traditional transistor memory units are transformed into voltage-type sense amplifier；And in writing data path, add sense amplifier as writing
Data buffer storage.When write operation, first pass through write driver and will write in data write sense amplifier and be cached, then by spirit
Bit line is discharged by quick amplifier, thus by full swing write small signal difference that data are converted on bit line and be sent to by
On the memory node of 6 transistor memory units chosen, when the voltage difference of memory node reaches by 6 transistor memory units and NMOS electric current
During the offset voltage of the sense amplifier that source is formed, the anti-WWL_N of write word line is effective, and NMOS current source is opened, by virtual earth
End moves ground to, and 6 transistor memory units pass through positive feedback, and the small signal difference on memory node is amplified to rapidly full swing, from
And complete write operation.
Below in conjunction with the accompanying drawings embodiments of the present invention are described further.
Fig. 1 is the SRAM schematic diagram implemented according to the present invention.This SRAM includes control circuit
With Pre-decoder 101, bit line is pre-charged and Jun Heng, sense amplifier, write driver 102, word-line decoder and driver 103,
NMOS current source 104, storage array 105.
Control circuit is connected wordline with decoder by locally-written enable inverted signal LWEN of a plurality of row pre-decode YPD and and translates
Code device and driver 103；Control circuit and decoder are pre-charged anti-BL_PRE_N also by bit line, read-write enables anti-RWE_N,
Sense amplifier be pre-charged anti-SA_PRE_N, sense amplifier enable SAE, write enable WE connect bit line precharge with Jun Heng,
Sense amplifier, write driver 102；
Word-line decoder is connected storage array, word-line decoder and driving with driver 103 by the anti-WL_N of a plurality of word-line signal
Device 103 connects NMOS current source 104 also by a plurality of write word line inverted signal WWL_N；
NMOS current source 104 connects storage array 105 by a plurality of virtual earth Virtual_VSS；
Storage array 105 connects bit line precharge and Jun Heng, sense amplifier, write driver by multiple bit lines BL/BL_N
102。
Fig. 4 show the SRAM of the present invention and writes data-path circuit design principle figure.This is write data path and includes many
Individual 6 transistor memory units and shared NMOS current source, bit line precharge and equalizer, sense amplifier, write driver.
Each 6 transistor memory units include by the first pulldown NMOS transistor, the second pulldown NMOS transistor, the first pull-up
PMOS transistor, the second pullup PMOS transistor, the first access PMOS transistor and second access PMOS transistor；
First pulldown NMOS transistor, the second pulldown NMOS transistor, the first pullup PMOS transistor, the second pull-up PMOS
Transistor composition cross coupling inverter, wherein the first pulldown NMOS transistor and the source of the second pulldown NMOS transistor
Connecing virtual earth, the first pullup PMOS transistor, the source of the second pullup PMOS transistor meet supply voltage VCC, first time
Drain terminal and the grid end correspondence respectively of drawing nmos pass transistor are connected with drain terminal and the grid end of the first pullup PMOS transistor, second time
Drain terminal and the grid end correspondence respectively of drawing nmos pass transistor are connected with drain terminal and the grid end of the second pullup PMOS transistor, first time
Drawing and have memory node A between the drain terminal of nmos pass transistor and the drain terminal of the first pullup PMOS transistor, first is drop-down
Between grid end and the grid end of the first pullup PMOS transistor of nmos pass transistor, there is memory node B, the second pull-down NMOS
There is between grid end and the grid end of the second pullup PMOS transistor of transistor memory node A ', the second pull-down NMOS crystal
Between drain terminal and the drain terminal of the second pullup PMOS transistor of pipe, there is memory node B ', memory node A and memory node A '
Connecting, memory node B is connected with memory node B '；
First accesses PMOS transistor and second accesses the grid termination wordline inverted signal of PMOS transistor, and first accesses PMOS
Transistor and second accesses the drain terminal correspondence respectively of PMOS transistor and is connected with bit line and bit line inverted signal；First accesses PMOS
The source of transistor accesses memory node A, and the second source accessing PMOS transistor accesses memory node B.
Sharing NMOS current source to be made up of nmos pass transistor N10, the drain terminal of N10 connects the virtual earth of a line 6 transistor memory unit
End, as shown in Figure 6；Grid the termination anti-WWL_N of write word line, source ground connection VSS.
Multiple 6 transistor memory unit shared bit line BL and the anti-BL_N of bit line.Assume the load on bit line BL and the anti-BL_N of bit line
Electric capacity is respectively CBL and CBL_N.
Multiple 6 transistor memory units connect bit line by bit line BL and the anti-BL_N of bit line and are pre-charged and equalizer, sense amplifier；
Bit line precharge, equalizer are by 2 precharge PMOS transistor P0, PMOS transistor P1 and an equilibrium PMOS
Transistor P2 forms.Bit line BL connects drain terminal and the source of PMOS transistor P2 of PMOS transistor P0.Bit line is anti-
BL_N connects drain terminal and the drain terminal of PMOS transistor P2 of PMOS transistor P1.Bit line precharge inverted signal BL_PRE_N
Connect the grid end of 3 PMOS transistor.Supply voltage VCC connects PMOS transistor P0 and PMOS transistor P1
Source.
Sense amplifier includes switching PMOS transistor P3, PMOS transistor P4, by two pulldown NMOS transistor
N31, nmos pass transistor N32 and the intersection of two pullup PMOS transistor P31, pullup PMOS transistor P32 compositions
Coupled inverters, NMOS current source N30, export phase inverter I3, I4, amplify line SL/SL_N, be pre-charged and equalize PMOS
Transistor P5, PMOS transistor P6 and PMOS transistor P7.
Wherein the source of pulldown NMOS transistor N31, N32 meets virtual earth Virtual_VSS<W>.
Write driver is made up of phase inverter I0, tristate inverter I1, I2.The input of write driver connects writes data D, and output connects
Amplify line SL and amplify the anti-SL_N of line.
In conjunction with Fig. 5, traditional SRAM writes the oscillogram of data path so that the operation principle of this circuit to be described.
When keeping pattern, write enable signal WE is low, and write driver is closed.Bit line pre-charge signal BL_PRE_N is low,
In bit line precharge, equalizer, PMOS transistor P0, PMOS transistor P1, PMOS transistor P2 are all in conducting
State, bit line BL and the anti-BL_N of bit line are charged to supply voltage VCC in advance.
The anti-WL_N of all of wordline is high, accesses PMOS transistor P13, PMOS transistor in all 6 transistor memory units
P14, PMOS transistor P23, PMOS transistor P24 etc. turn off；The anti-WWL_N of all of write word line is high, all
Shared NMOS current source N10, NMOS current source N20 etc. open, all of virtual earth Virtual_VSS is low, because of
These all of 6 transistor memory units be in holding data mode.
It is high that read-write enables anti-RWE_N, and sense amplifier input switch PMOS transistor P3, P4 turn off, bit line BL,
The anti-BL_N of bit line and amplification line SL, the amplification anti-SL_N of line are isolated.
It is low that sense amplifier enables SAE, and NMOS current switch N30 turns off.
It is low for amplify line SL/SL_N being pre-charged anti-SA_PRE_N, and it is brilliant with Jun Heng PMOS that sense amplifier amplifies line precharge
Body pipe P5, PMOS transistor P6, PMOS transistor P7 turn on, and amplification line SL, the amplification anti-SL_N of line are maintained at power supply
Voltage VCC, simultaneously virtual earth Virtual_VSS<W>to be maintained at VCC-Vtn, Vtn be sense amplifier pull-down NMOS crystal
Pipe N31, the threshold voltage of nmos pass transistor N32.
When write operation, first, sense amplifier amplifies the line anti-SA_PRE_N of precharge and draws high, and it is pre-that sense amplifier amplifies line
Shutoff is led in charging with Jun Heng PMOS transistor P5, PMOS transistor P6, PMOS transistor P7, amplifies line SL and position
Line anti-SL_N floating.Then, write enable signal WE is high, and write driver is opened, and write driver will be write data D and drive extremely
Amplify line SL and amplify the anti-SL_N of line.Amplify line SL and amplify in the anti-SL_N of line wherein one be maintained at pre-charge level
VCC, another is discharged into ground VSS from VCC.Then, write enable signal WE drags down, and write driver is closed.Meanwhile,
It is high that sense amplifier enables SAE, and NMOS current switch N30 opens, virtual earth Virtual_VSS<W>it is pulled to ground VSS.
Nmos pass transistor N31, pullup PMOS transistor P31, pullup PMOS transistor P32 group is pulled up by sense amplifier
The cross-couplings become reversely forms positive feedback, data D of writing having that write driver write is preserved and amplifies line SL and amplification line is anti-
On SL_N.Then, the 6 selected anti-WWL_N of transistor memory unit write word line drag down, and NMOS current source turns off, virtual earth
Virtual_VSS floating；The anti-WL_N of wordline drags down, and accesses PMOS transistor and opens, memory cell data BIT and BITB
Supply voltage VCC it is charged in advance by the anti-BL_N of bit line BL and bit line.Then, bit line is pre-charged anti-BL_PRE_N and draws high, position
Line precharge turns off with 3 PMOS transistor in equalizer, bit line BL and bit line anti-BL_N floating.Then, read-write makes
Can drag down by anti-RWE_N, sense amplifier input switch PMOS transistor P3, PMOS transistor P4 are opened, bit line BL,
The anti-BL_N of bit line and amplification line SL, the amplification anti-SL_N of line connect.For convenience of describing, it is now assumed that data D of write are 0,
Then sense amplifier amplification line SL is low and amplifies the anti-SL_N of line for height.Due to PMOS transistor P3, pull-down NMOS crystalline substance
Body pipe N31, nmos pass transistor N30 turn on, and bit line BL is discharged by sense amplifier by amplifying line SL；And other one
End, SL_N remains VCC, and PMOS transistor P4 turns on, so the anti-BL_N of bit line is maintained at supply voltage VCC.
It is in the conduction state, between bit line BL and the anti-BL_N of bit line owing to 6 selected transistor memory units accessing PMOS transistor
Voltage difference can pass to store on data BIT and the anti-BITB of data.6 the most selected transistor memory units and connection virtual earth
NMOS current source combines and is equivalent to a sense amplifier, is somebody's turn to do when the voltage difference of bit line BL and the anti-BL_N of bit line arrives
During the offset voltage Voffset of sense amplifier, read-write enables anti-RWE_N and draws high, and sense amplifier input switch PMOS is brilliant
Body pipe P3, PMOS transistor P4 turn off, the anti-BL_N of bit line BL, bit line and amplification line SL, amplification line anti-SL_N quilt
Isolation.Meanwhile, the 6 selected anti-WL_N of transistor memory unit wordline draw high, and access PMOS in 6 selected transistor memory units
Transistor turns off；Meanwhile, the anti-WWL_N of write word line of selected memory element draws high, and NMOS current source is opened, virtual earth
Virtual_VSS is pulled to ground.In selected memory element, cross-linked phase inverter passes through positive feedback, by data BIT sum
Full swing it is amplified to rapidly according to the voltage difference between anti-BITB.In this course, sense amplifier is by amplifying line SL and putting
Bit line BL and bit line BL_N is discharged by the big anti-SL_N of line, owing to not extracting electric current from supply voltage VCC, therefore consumes
Energy is 0.When read-write enables after anti-RWE_N draws high, and bit line is pre-charged anti-BL_PRE_N and drags down, bit line precharge with all
Weighing apparatus PMOS transistor is opened, and anti-to bit line BL and bit line BL_N is charged to supply voltage VCC.At the end of write operation,
Sense amplifier enables SAE and drags down, and NMOS current switch N30 turns off, and meanwhile, amplifies line SL/SL_N precharge anti-
SA_PRE_N drags down, and amplifies line SL/SL_N precharge and opens with Jun Heng PMOS transistor, will amplify line SL and amplify line
Anti-SL_N charges to supply voltage VCC.In this course, bit line BL is charged to VCC from VCC-Voffset, from
Supply voltage VCC extracts electric current, and the energy of consumption is CBL Voffset VCC.After in sum, for writing each time
Operation, including sense amplifier by amplifying line SL and amplifying the anti-SL_N of line BL_N anti-to bit line BL and bit line electric discharge, and
Bit line precharge, the equilibrium of equalizer BL_N anti-to bit line BL and bit line and precharge operation when write operation completes, to each
For BL_N anti-to bit line BL and bit line, its upset power consumption consumed is that it is pre-that the energy of consumption during write operation adds up line
The energy consumed when charging, equalization operation, i.e. 0+CBL Voffset VCC, for CBL Voffset VCC.Receive 40
Under rice logic process, under the conditions of room temperature 25 DEG C and normal voltage VCC=1.1V, by the Monte Carlo simulation of 1000 times,
The offset voltage of sense amplifier obtaining being made up of 6 transistor memory units and NMOS current source is 0.26V.Therefore, the present invention
Mono-recordable operates, and the bit line inversion energy consumed is 0.26 CBL VCC；CBL VCC with conventional art2, wherein
Supply voltage VCC=1.1V, i.e. 1.1 CBL VCC compare, and have dropped 4.2 times.
Claims (5)
1. the ultralow SRAM writing power consumption, including control circuit and Pre-decoder (101), bit line precharge with
Equalizer, write driver (102), word-line decoder and driver (103) and storage array (105), described storage array (105)
Including multirow 6 transistor memory unit, it is characterised in that:
Two access pipes of each 6 transistor memory units are PMOS transistor, and two NMOS of each 6 transistor memory units are drop-down
Pipe source is connected with the virtual earth end of the NMOS current source (104) controlled by the anti-WWL_N of write word line, and often the storage of row 6 pipe is single
A NMOS current source (104) is shared by unit；
Described SRAM also includes sense amplifier, and described write driver (102) is pre-by sense amplifier and bit line
Charging is connected with equalizer, and described sense amplifier writes for writing data and caches, then is entered bit line by sense amplifier
Row electric discharge, thus by full swing write small signal difference that data are converted on bit line and to be sent to 6 selected pipes storages single
On the memory node of unit.
The ultralow SRAM writing power consumption the most according to claim 1, it is characterised in that:
Described sense amplifier includes that PMOS transistor P3, PMOS transistor P4, cross coupling inverter, NMOS are brilliant
Body pipe N30, output phase inverter I3, output phase inverter I4 and sense amplifier precharge and equalizer；
The grid termination read-write of PMOS transistor P3 and PMOS transistor P4 enables anti-RWE_N, described PMOS transistor
The source of P3, drain terminal meet bit line BL respectively and amplify line SL, and the source of described PMOS transistor P4, drain terminal connect respectively
The anti-BL_N of bit line and the amplification anti-SL_N of line；
Described cross coupling inverter is by pulldown NMOS transistor N31, pulldown NMOS transistor N32 and pull-up PMOS
Transistor P31, pullup PMOS transistor P32 form, wherein pulldown NMOS transistor N31 and pull-down NMOS crystal
The source of pipe N32 connects virtual earth, and pullup PMOS transistor P31, the source of pullup PMOS transistor P32 connect supply voltage
The drain terminal of VCC, pulldown NMOS transistor N31 and grid end distinguish the corresponding drain terminal with pullup PMOS transistor P31 and grid
End connects, the most corresponding drain terminal with pullup PMOS transistor P32 of the drain terminal of pulldown NMOS transistor N32 and grid end and
Grid end connects, and has data section between drain terminal and the drain terminal of pullup PMOS transistor P31 of pulldown NMOS transistor N31
Between grid end and the grid end of pullup PMOS transistor P31 of some C, pulldown NMOS transistor N31, there is back end D,
Between grid end and the grid end of pullup PMOS transistor P32 of pulldown NMOS transistor N32, there is back end C ', under
Draw and there are between the drain terminal of nmos pass transistor N32 and the drain terminal of pullup PMOS transistor P32 back end D ', data
Node C is connected with back end C ', and back end D is connected with back end D '；
The input of described back end C and output phase inverter I3 is connected with amplifying line SL_, the outfan of output phase inverter I3
Meet the reading anti-Q_N of data；The input of described back end D ' and output phase inverter I4 is connected with amplifying the anti-SL_N of line, described
The output termination of output phase inverter I4 reads data Q；
The grid termination sense amplifier of described nmos pass transistor N30 enables SAE, and the source of nmos pass transistor N30 connects void
Ground；The drain terminal ground connection of nmos pass transistor N30；
The precharge of described sense amplifier includes three PMOS transistor with equalizer, and the grid end of three PMOS transistor is tied altogether
Point, the source of two of which PMOS transistor connects power supply VCC, and drain terminal connects one respectively and amplifies line；Another one PMOS
The drain terminal of transistor and source are connected to two and amplify between line.
The ultralow SRAM writing power consumption the most according to claim 1 and 2, it is characterised in that:
Described NMOS current source (104) is made up of nmos pass transistor N10, and the drain terminal of nmos pass transistor N10 connects one
The virtual earth end of row 6 transistor memory unit, the grid termination anti-WWL_N of write word line, source ground connection.
The ultralow SRAM writing power consumption the most according to claim 3, it is characterised in that:
Described control circuit and decoder (101) are by locally-written enable inverted signal LWEN of a plurality of row pre-decode YPD and
Connect word-line decoder and driver (103), be pre-charged by bit line anti-BL_PRE_N be pre-charged with bit line and equalizer is connected,
Be connected with sense amplifier PMOS transistor P3 and sense amplifier PMOS transistor P4 by the read-write anti-RE_N of enable,
The grid of anti-SA_PRE_N and sense amplifier precharge with three PMOS transistor of equalizer it are pre-charged by sense amplifier
The grid end connecting, being enabled by sense amplifier SAE and nmos pass transistor N30 is held to be connected, by writing enable WE connection
Write driver (102)；Described word-line decoder is stored by the anti-WL_N of a plurality of word-line signal and 6 pipes with driver (103)
First access PMOS transistor of unit and second accesses the grid end of PMOS transistor and connects, every anti-WL_N of word-line signal
One 6 transistor memory unit of corresponding connection；Described word-line decoder and driver (103) are also by a plurality of write word line inverted signal
WWL_N connects multiple NMOS current sources (104)；Every write word line inverted signal WWL_N correspondence connects a NMOS
Current source (104).
5. control method based on the ultralow SRAM write operation writing power consumption described in claim 4, it is characterised in that:
Keeping control method during pattern it is:
Write enable signal WE is low, and write driver is closed；
Meanwhile, line precharging signal BL_PRE_N is low, bit line precharge, in equalizer 3 PMOS transistor all in
Conducting state, bit line BL and the anti-BL_N of bit line are charged to supply voltage VCC in advance；
Meanwhile, the anti-WL_N of all of wordline is high, accesses PMOS transistor and turn off in all 6 transistor memory units；
Meanwhile, the anti-WWL_N of all of write word line is high, and all of shared NMOS current source is opened, and all of virtual earth is low,
The most all of 6 transistor memory units be in holding data mode；
Meanwhile, it is high that read-write enables anti-RWE_N, and sense amplifier input switch PMOS transistor P3, P4 turn off, position
The anti-BL_N of line BL, bit line and amplification line SL, the amplification anti-SL_N of line are isolated；
Meanwhile, it is low that sense amplifier enables SAE, and NMOS current switch N30 turns off；
Meanwhile, it is low for amplify line SL/SL_N being pre-charged anti-SA_PRE_N, and sense amplifier amplifies line precharge and Jun Heng PMOS
Transistor P5-P7 turns on, and amplification line SL, the amplification anti-SL_N of line are maintained at supply voltage VCC, and virtual earth is maintained at simultaneously
VCC-Vtn, Vtn are sense amplifier pulldown NMOS transistor N31, the threshold voltage of nmos pass transistor N32；
Control method when writing data is:
1) the sense amplifier amplification line anti-SA_PRE_N of precharge draws high, and sense amplifier amplifies line and is pre-charged with Jun Heng 3
Individual PMOS transistor turns off, and amplifies line SL and bit line anti-SL_N floating；
2) write enable signal WE is high, and write driver is opened, and write driver will be write data D and drive to amplifying line SL and amplification
The anti-SL_N of line, amplify line SL and amplify in the anti-SL_N of line wherein one be maintained at pre-charge level VCC, another by from
VCC discharges into ground VSS；
3) write enable signal WE drags down, and write driver is closed；Meanwhile, it is high that sense amplifier enables SAE, NMOS electricity
Stream switch N30 opens, and virtual earth is pulled to ground VSS；By sense amplifier pulldown NMOS transistor N31, pull up PMOS
The cross-couplings of transistor P31, pullup PMOS transistor P31P32 composition reversely forms positive feedback, and write driver will be had to write
Data D of writing be saved in amplification line SL and amplify on the anti-SL_N of line；
4) the 6 selected anti-WWL_N of transistor memory unit write word line drag down, and NMOS current source turns off, virtual earth floating；Word
The anti-WL_N of line drags down, and two access PMOS transistor and open, and memory cell data BIT and BITB are by bit line BL and position
The anti-BL_N of line is charged to supply voltage VCC in advance；
5) the anti-BL_PRE_N of bit line precharge draws high, and bit line precharge turns off with 3 PMOS transistor in equalizer, position
Line BL and bit line anti-BL_N floating；
6) the anti-RWE_N of read-write enable drags down, sense amplifier input switch PMOS transistor P3, PMOS transistor P4
Opening, the anti-BL_N of bit line BL, bit line and amplification line SL, the amplification anti-SL_N of line connect；
If data D of write are 0, then sense amplifier amplifies line SL is low, and it is high for amplifying the anti-SL_N of line；Due to PMOS
Transistor P3, nmos pass transistor N31, nmos pass transistor N30 turn on, and sense amplifier is by amplifying line SL to bit line
BL discharges；And other end, SL_N remains VCC, and PMOS transistor P4 turns on, so the anti-BL_N of bit line protects
Hold at supply voltage VCC；Voltage difference between bit line BL and the anti-BL_N of bit line can pass to store data BIT and the anti-BITB of data
On；
When the voltage difference of bit line BL and the anti-BL_N of bit line arrives the offset voltage Voffset of this sense amplifier, read-write enables
Anti-RWE_N draws high, and sense amplifier input switch PMOS transistor P3, PMOS transistor P4 turn off, bit line BL,
The anti-BL_N of bit line and amplification line SL, the amplification anti-SL_N of line are isolated；Meanwhile, 6 selected transistor memory unit wordline are anti-
WL_N draws high, and accesses PMOS transistor and turn off in 6 selected transistor memory units；Meanwhile, selected memory element
The anti-WWL_N of write word line draws high, and NMOS current source is opened, and virtual earth is pulled to ground；Cross-couplings in selected memory element
Phase inverter by positive feedback, the voltage difference between anti-to data BIT and data BITB is amplified to rapidly full swing；
If data D of write are 1, then sense amplifier amplifies the anti-SL_N of line is low, and it is high for amplifying line SL；Due to P4,
N32, N30 turn on, and bit line BL_N is discharged by sense amplifier by amplifying the anti-SL_N of line；And other end, SL keeps
For VCC, and P3 conducting, so bit line BL is maintained at supply voltage VCC；Electricity between bit line BL and the anti-BL_N of bit line
Pressure reduction can pass to store on data BIT and the anti-BITB of data；
When the voltage difference of bit line BL and the anti-BL_N of bit line arrives the offset voltage Voffset of this sense amplifier, read-write enables
Anti-RWE_N draws high, and sense amplifier input switch PMOS transistor P3, PMOS transistor P4 turn off, bit line BL,
The anti-BL_N of bit line and amplification line SL, the amplification anti-SL_N of line are isolated；Meanwhile, 6 selected transistor memory unit wordline are anti-
WL_N draws high, and accesses PMOS transistor and turn off in 6 selected transistor memory units；Meanwhile, selected memory element
The anti-WWL_N of write word line draws high, and NMOS current source is opened, and virtual earth is pulled to ground；Cross-couplings in selected memory element
Phase inverter by positive feedback, the voltage difference between anti-to data BIT and data BITB is amplified to rapidly full swing；
7) at the end of write operation, sense amplifier enables SAE and drags down, and NMOS current switch N30 turns off, and, puts meanwhile
Big line SL/SL_N is pre-charged anti-SA_PRE_N and drags down, and amplifies line SL/SL_N precharge and Jun Heng PMOS transistor P5-P7
Open, amplification line SL and the amplification anti-SL_N of line is charged to supply voltage VCC.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110232941A (en) * | 2019-06-24 | 2019-09-13 | 安徽大学 | It is a kind of with low-power consumption and to write the mixing 10T TFET-MOSFET SRAM cell circuit of enhancing |
| CN112992202A (en) * | 2021-03-24 | 2021-06-18 | 长鑫存储技术有限公司 | Sense amplifier, memory and control method |
| CN113496721A (en) * | 2020-03-20 | 2021-10-12 | 中芯国际集成电路制造(上海)有限公司 | Read amplifier and method and device for enhancing read reliability of load module |
| CN116994616A (en) * | 2023-08-17 | 2023-11-03 | 合芯科技(苏州)有限公司 | Sense amplifier, static random access memory and control method of sense amplifier |
| US11823763B2 (en) | 2021-03-24 | 2023-11-21 | Changxin Memory Technologies, Inc. | Sense amplifier, memory and control method |
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US894541A (en) * | 1903-12-05 | 1908-07-28 | Charles Scudder | Blind-stitching sewing-machine. |
| US5986923A (en) * | 1998-05-06 | 1999-11-16 | Hewlett-Packard Company | Method and apparatus for improving read/write stability of a single-port SRAM cell |
| CN1606096A (en) * | 2004-11-03 | 2005-04-13 | 东南大学 | Low power consumption static random memory with low level thread amplitude of oscillation |
| CN1629981A (en) * | 2003-12-15 | 2005-06-22 | 松下电器产业株式会社 | Semiconductor integrated circuit |
| CN1755836A (en) * | 2004-09-27 | 2006-04-05 | 国际商业机器公司 | SRAM array with improved cell stability |
| CN1774766A (en) * | 2003-04-11 | 2006-05-17 | 飞思卡尔半导体公司 | Memory device with sense amplifier and self-timed latch |
| CN101246740A (en) * | 2008-03-13 | 2008-08-20 | 复旦大学 | Ultra-low power consumption nonvolatile static random access memory cell and operation method thereof |
| CN103886896A (en) * | 2014-03-31 | 2014-06-25 | 西安华芯半导体有限公司 | Static random access memory for reducing writing power consumption by adopting static writing technology |
| CN104321817A (en) * | 2012-03-30 | 2015-01-28 | 英特尔公司 | Memory cell with improved write margin |
| CN104425008A (en) * | 2013-08-30 | 2015-03-18 | 三星电子株式会社 | Static random access memory device including dual power line and bit line precharge method thereof |
| CN205656856U (en) * | 2016-05-20 | 2016-10-19 | 西安紫光国芯半导体有限公司 | Ultralow static RAM who writes consumption |
-
2016
- 2016-05-20 CN CN201610340529.7A patent/CN105976859B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US894541A (en) * | 1903-12-05 | 1908-07-28 | Charles Scudder | Blind-stitching sewing-machine. |
| US5986923A (en) * | 1998-05-06 | 1999-11-16 | Hewlett-Packard Company | Method and apparatus for improving read/write stability of a single-port SRAM cell |
| CN1774766A (en) * | 2003-04-11 | 2006-05-17 | 飞思卡尔半导体公司 | Memory device with sense amplifier and self-timed latch |
| CN1629981A (en) * | 2003-12-15 | 2005-06-22 | 松下电器产业株式会社 | Semiconductor integrated circuit |
| CN1755836A (en) * | 2004-09-27 | 2006-04-05 | 国际商业机器公司 | SRAM array with improved cell stability |
| CN1606096A (en) * | 2004-11-03 | 2005-04-13 | 东南大学 | Low power consumption static random memory with low level thread amplitude of oscillation |
| CN101246740A (en) * | 2008-03-13 | 2008-08-20 | 复旦大学 | Ultra-low power consumption nonvolatile static random access memory cell and operation method thereof |
| CN104321817A (en) * | 2012-03-30 | 2015-01-28 | 英特尔公司 | Memory cell with improved write margin |
| CN104425008A (en) * | 2013-08-30 | 2015-03-18 | 三星电子株式会社 | Static random access memory device including dual power line and bit line precharge method thereof |
| CN103886896A (en) * | 2014-03-31 | 2014-06-25 | 西安华芯半导体有限公司 | Static random access memory for reducing writing power consumption by adopting static writing technology |
| CN205656856U (en) * | 2016-05-20 | 2016-10-19 | 西安紫光国芯半导体有限公司 | Ultralow static RAM who writes consumption |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110232941A (en) * | 2019-06-24 | 2019-09-13 | 安徽大学 | It is a kind of with low-power consumption and to write the mixing 10T TFET-MOSFET SRAM cell circuit of enhancing |
| CN110232941B (en) * | 2019-06-24 | 2024-03-15 | 安徽大学 | Hybrid 10T TFET-MOSFET SRAM cell circuit with low power consumption and write enhancement |
| CN113496721A (en) * | 2020-03-20 | 2021-10-12 | 中芯国际集成电路制造(上海)有限公司 | Read amplifier and method and device for enhancing read reliability of load module |
| CN112992202A (en) * | 2021-03-24 | 2021-06-18 | 长鑫存储技术有限公司 | Sense amplifier, memory and control method |
| US11823763B2 (en) | 2021-03-24 | 2023-11-21 | Changxin Memory Technologies, Inc. | Sense amplifier, memory and control method |
| US11894101B2 (en) | 2021-03-24 | 2024-02-06 | Changxin Memory Technologies, Inc. | Sense amplifier, memory and control method |
| US12033690B2 (en) | 2021-03-24 | 2024-07-09 | Changxin Memory Technologies, Inc. | Sense amplifier, memory and control method |
| CN116994616A (en) * | 2023-08-17 | 2023-11-03 | 合芯科技(苏州)有限公司 | Sense amplifier, static random access memory and control method of sense amplifier |
| CN116994616B (en) * | 2023-08-17 | 2024-02-27 | 合芯科技(苏州)有限公司 | Sense amplifier, static random access memory and control method of sense amplifier |
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