CN205195591U

CN205195591U - Intelligence power module and air conditioner

Info

Publication number: CN205195591U
Application number: CN201520976521.0U
Authority: CN
Inventors: 冯宇翔
Original assignee: Midea Group Co Ltd; Chongqing Midea Refrigeration Equipment Co Ltd
Current assignee: Midea Group Co Ltd; Chongqing Midea Refrigeration Equipment Co Ltd
Priority date: 2015-11-30
Filing date: 2015-11-30
Publication date: 2016-04-27
Anticipated expiration: 2025-11-30

Abstract

The utility model provides an intelligence power module and air conditioner, intelligent power module includes: under bridge arm signal input part, three -phase bridge arm signal input part, current detection end and PFC control input end on the three -phase, be provided with on the HVIC pipe corresponding to the first port of current detection end and the second port of holding corresponding to the PFC control input, self -adaptive circuit's first input end is connected to first port, and self -adaptive circuit's second input is connected to the second port, and self -adaptive circuit's output can be held as the messenger that HVIC managed, wherein, when self -adaptive circuit is in the rising edge at the incoming signal of second input, carry out the enable signal of the corresponding level of result output of twice detection according to the incoming signal to the first input end, when self -adaptive circuit is in the rising edge at the incoming signal of second input, the enable signal of the corresponding level of result output that once detects according to the incoming signal to the first input end.

Description

Intelligent Power Module and air conditioner

Technical field

The utility model relates to Intelligent Power Module technical field, in particular to a kind of Intelligent Power Module and a kind of air conditioner.

Background technology

Intelligent Power Module (IntelligentPowerModule, be called for short IPM) be a kind of analog line driver that power electronics discrete device and integrated circuit technique are integrated, Intelligent Power Module comprises device for power switching and high-voltage driving circuit, and with overvoltage, overcurrent and the failure detector circuit such as overheated.The logic input terminal of Intelligent Power Module receives the control signal of master controller, and output drives compressor or subsequent conditioning circuit work, sends the system status signal detected back to master controller simultaneously.Relative to traditional discrete scheme; Intelligent Power Module has the advantages such as high integration, high reliability, self-inspection and protective circuit; being particularly suitable for the frequency converter of drive motors and various inverter, is the desired power level electronic device of frequency control, metallurgical machinery, electric traction, servo-drive, frequency-conversion domestic electric appliances.

The structural representation of existing Intelligent power module circuit as shown in Figure 1, as current detecting end, protect Intelligent Power Module 100 with the size of current that basis detects by MTRIP port.PFCIN port is as PFC (PowerFactorCorrection, the power factor correction) control input end of Intelligent Power Module.

In the Intelligent Power Module course of work, PFCINP end frequently switches between low and high level by certain frequency, make that IGBT pipe 127 continues to be on off state and FRD pipe 131 continues to be in freewheeling state, this frequency be generally LIN1 ~ LIN3,2 ~ 4 times of HIN1 ~ HIN3 switching frequency, and not contact directly with the switching frequency of LIN1 ~ LIN3, HIN1 ~ HIN3.

As shown in Figure 2, UN, VN, WN connect one end of milliohm resistance 138, another termination GND, MTRIP of milliohm resistance 138 are current detecting pins, connect one end of milliohm resistance 138, by detecting the pressure drop measuring and calculating electric current of milliohm resistance, as shown in Figure 3, when current is excessive, Intelligent Power Module 100 is made to quit work, avoid because of overcurrent produce overheated after, permanent damage is produced to Intelligent Power Module 100.

-VP, COM, UN, VN, WN have electrical connection in actual use.Therefore, current noise when voltage noise during IGBT pipe 121 ~ IGBT pipe 127 switch and FRD pipe 111 ~ FRD pipe 116,131 afterflow of FRD pipe all can intercouple, and impacts the input pin of each low-voltage area.

In each input pin, the threshold value of HIN1 ~ HIN3, LIN1 ~ LIN3, PFCINP is generally at about 2.3V, and the threshold voltage of ITRIP generally only has 0.5V once, and therefore, ITRIP is the pin be the most easily interfered.When ITRIP is triggered, Intelligent Power Module 100 will quit work, and because now really there is not overcurrent, so ITRIP triggering now belongs to false triggering.As shown in Figure 4, be high level at PFCIN, when moment opened by IGBT pipe 127, because the existence of the reverse recovery current of FRD pipe 131, superpose out I ₁₃₁current waveform, this electric current has larger concussion noise, passes through-VP, COM, UN, VN, WN electrical connection in peripheral circuit, and concussion noise can close out certain voltage and raise by lotus root at MTRIP end.If the condition making MTRIP trigger is: voltage >Vth, and duration >Tth; In the diagram, if Ta<Tth<Tb, then make MTRIP produce false triggering too high being not enough to of the voltage in first three cycle, to the 4th cycle, MTRIP will produce false triggering.

The length of the reverse recovery time of FRD pipe is relevant with temperature, temperature is higher, reverse recovery time is longer, therefore along with the continuous firing of system, the constant temperature of Intelligent Power Module 100 rises, and the probability that MTRIP is triggered is increasing, in the application scenario that some are severe, finally can produce false triggering, make system stalls.Although this false triggering can recover over time and can not form destruction to system, puzzlement can be caused to user undoubtedly.As the application scenario for transducer air conditioning, time the higher user just of ambient temperature more needs air-conditioning system continuous firing, but high ambient temperature can make increase the reverse recovery time of FRD pipe, MTRIP improves by the probability of false triggering, once MTRIP is by false triggering, air-conditioning system can quit work 3 ~ 5 minutes because thinking generation overcurrent by mistake, makes user during this period of time cannot obtain cold wind, and this causes air-conditioning system because refrigerating capacity deficiency is by the one of the main reasons of customer complaint.

Therefore, how under guaranteeing that Intelligent Power Module has the prerequisite of high reliability and high-adaptability, effectively can reduce Intelligent Power Module and to be become technical problem urgently to be resolved hurrily by the probability of false triggering.

Utility model content

The utility model is intended at least to solve one of technical problem existed in prior art or correlation technique.

For this reason, an object of the present utility model is to propose a kind of new Intelligent Power Module, under guaranteeing that Intelligent Power Module has the prerequisite of high reliability and high-adaptability, can effectively reduce Intelligent Power Module by the probability of false triggering.

Another object of the present utility model is to propose a kind of air conditioner.

For achieving the above object, according to the embodiment of first aspect of the present utility model, propose a kind of Intelligent Power Module, comprising: brachium pontis signal input part, three-phase low reference voltage end, current detecting end and PFC control input end under brachium pontis signal input part, three-phase on three-phase; HVIC manages, described HVIC pipe is provided with the terminals being connected to brachium pontis signal input part under brachium pontis signal input part and described three-phase on described three-phase respectively, and correspond to the first port of described current detecting end and correspond to the second port of described PFC control input end, described first port is connected with described current detecting end by connecting line, and described second port is connected with described PFC control input end by connecting line; Sampling resistor, described three-phase low reference voltage end and described current detecting end are all connected to the first end of described sampling resistor, and the second end of described sampling resistor is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module; Adaptive circuit, the power supply positive pole of described adaptive circuit and negative pole are connected to low-pressure area power supply anode and the negative terminal of described Intelligent Power Module respectively, the first input end of described adaptive circuit is connected to described first port, second input of described adaptive circuit is connected to described second port, and the output of described adaptive circuit is as the Enable Pin of described HVIC pipe;

Wherein, described adaptive circuit, when the input signal of described second input is in rising edge, exports the enable signal of corresponding level according to the result of the input signal of described first input end being carried out to twice detection; Described adaptive circuit, when the input signal of described second input is not in rising edge, exports the enable signal of corresponding level according to the result of the input signal of described first input end being carried out to one-time detection.

According to the Intelligent Power Module of embodiment of the present utility model, owing to being in high level moment at the second port (i.e. PFCINP), if the voltage fluctuation of the first port (ITRIP) is because circuit noise causes, so ITRIP voltage is a process continuing to reduce, therefore by arranging adaptive circuit, with when the input signal of the second input (i.e. PFC control input end) is in rising edge, the enable signal of corresponding level is exported according to the result of the input signal of first input end (current detecting end) being carried out to twice detection, make in PFCINP high level moment, can by secondary detection filtering because circuit noise causes the possible of misoperation, if and from real overcurrent during the voltage fluctuation of ITRIP, so ITRIP voltage is a process continued to increase, secondary detection confirms that rear output low level in time can be guaranteed that Intelligent Power Module quits work and form protection.

By when the input signal of the second input is not in rising edge; the enable signal of corresponding level is exported according to the result of the input signal of first input end being carried out to one-time detection; make after PFCINP high level; Intelligent Power Module can carry out conventional sense judgement; time excessive with the current signal detected at current detecting end, Intelligent Power Module provided and protects timely.

According to the Intelligent Power Module of above-described embodiment of the present utility model, following technical characteristic can also be had:

According to an embodiment of the present utility model, described adaptive circuit is when the input signal of described second input is in rising edge, when the result of the input signal of described first input end being carried out to twice detection is magnitude of voltage higher than predetermined value, export the enable signal of the first level, to forbid the work of described HVIC pipe; Otherwise, export the enable signal of described second electrical level, to allow the work of described HVIC pipe;

Described adaptive circuit when the input signal of described second input is not in rising edge, when the result of the input signal of described first input end being carried out to one-time detection be magnitude of voltage higher than predetermined value time, export the enable signal of described first level; Otherwise, export the enable signal of described second electrical level.

Wherein, the enable signal of the first level can be low level signal, and the enable signal of second electrical level can be high level signal.

According to an embodiment of the present utility model, described adaptive circuit comprises:

First voltage comparator, the positive input terminal of described first voltage comparator is as the first input end of described adaptive circuit, the negative input end of described first voltage comparator is connected to the positive pole of voltage source, the negative pole of described voltage source is as the power supply negative pole of described adaptive circuit, and the output of described first voltage comparator is connected to the first selecting side of analog switch;

The first not gate be connected in series and the second not gate, the input of described first not gate is as the second input of described adaptive circuit, and the output of described second not gate is connected to the first input end of the first NAND gate;

The 3rd not gate be connected in series, the 4th not gate and the 5th not gate, the input of described 3rd not gate is connected to the input of described first not gate, the output of described 5th not gate is connected to the second input of described first NAND gate, the output of described first NAND gate is connected to the input of the 6th not gate, and the output of described 6th not gate is connected to the control end of described analog switch;

First electric capacity, between the input being connected to described 4th not gate and the power supply negative pole of described adaptive circuit;

Second electric capacity, between the input being connected to described 5th not gate and the power supply negative pole of described adaptive circuit;

The 7th not gate be connected in series and the 8th not gate, the input of described 7th not gate is connected to the input of described first not gate, and the output of described 8th not gate is connected to the first input end of the second NAND gate;

The 9th not gate be connected in series, the tenth not gate and the 11 not gate, the input of described 9th not gate is connected to the input of described first not gate, the output of described 11 not gate is connected to the second input of described second NAND gate, and the output of described second NAND gate is connected to the input of the 12 not gate;

3rd electric capacity, between the input being connected to described 11 not gate and the power supply negative pole of described adaptive circuit;

Rest-set flip-flop, the R end of described rest-set flip-flop is connected to the output of described 12 not gate;

The AD converter be connected in series and D/A converter, the input of described AD converter is connected to the positive input terminal of described first voltage comparator positive input terminal and the second voltage comparator, the output of described D/A converter is connected to the negative input end of described second voltage comparator, and the output of described second voltage comparator is connected to the S end of described rest-set flip-flop;

3rd NAND gate, the Q end of the output of described 6th not gate, the output of described first voltage comparator and described rest-set flip-flop is connected to three inputs of described 3rd NAND gate respectively, the output of described 3rd NAND gate is connected to the input of the 13 not gate, the output of described 13 not gate is connected to the second selecting side of described analog switch, the stiff end of described analog switch is connected to the input of the 14 not gate, and the output of described 14 not gate is as the output of described adaptive circuit.

According to an embodiment of the present utility model, described HVIC pipe is also provided with the signal output part of PFC drive circuit, described Intelligent Power Module also comprises: the first power switch pipe and the first diode, the anode of described first diode is connected to the emitter of described first power switch pipe, the negative electrode of described first diode is connected to the collector electrode of described first power switch pipe, the collector electrode of described first power switch pipe is connected to the anode of the second diode, the negative electrode of described second diode is connected to the high voltage input of described Intelligent Power Module, the base stage of described first power switch pipe is connected to the signal output part of described PFC drive circuit, the emitter of described first power switch pipe is as the PFC low reference voltage end of described Intelligent Power Module, the collector electrode of described first power switch pipe is held as the PFC of described Intelligent Power Module.

Wherein, the first power switch pipe can be IGBT (InsulatedGateBipolarTransistor, insulated gate bipolar transistor).

According to an embodiment of the present utility model, also comprise: boostrap circuit, described boostrap circuit comprises: the first bootstrap diode, the anode of described first bootstrap diode is connected to the low-pressure area power supply anode of described Intelligent Power Module, and the negative electrode of described first bootstrap diode is connected to the U phase higher-pressure region power supply anode of described Intelligent Power Module; Second bootstrap diode, the anode of described second bootstrap diode is connected to the low-pressure area power supply anode of described Intelligent Power Module, and the negative electrode of described second bootstrap diode is connected to the V phase higher-pressure region power supply anode of described Intelligent Power Module; 3rd bootstrap diode, the anode of described 3rd bootstrap diode is connected to the low-pressure area power supply anode of described Intelligent Power Module, and the negative electrode of described 3rd bootstrap diode is connected to the W phase higher-pressure region power supply anode of described Intelligent Power Module.

According to an embodiment of the present utility model, also comprise: bridge arm circuit on three-phase, in each phase on described three-phase in bridge arm circuit, the input of bridge arm circuit is connected to the signal output part of corresponding phase in the three-phase high-voltage district of described HVIC pipe; Bridge arm circuit under three-phase, under each phase under described three-phase in bridge arm circuit, the input of bridge arm circuit is connected to the signal output part of corresponding phase in the three-phase low-voltage district of described HVIC pipe.

Wherein, on three-phase, bridge arm circuit comprises: bridge arm circuit in bridge arm circuit, W phase in bridge arm circuit, V phase in U phase; Under three-phase, bridge arm circuit comprises: the lower bridge arm circuit of the lower bridge arm circuit of U phase, V phase, the lower bridge arm circuit of W phase.

According to an embodiment of the present utility model, in each phase described, bridge arm circuit comprises: the second power switch pipe and the 3rd diode, the anode of described 3rd diode is connected to the emitter of described second power switch pipe, the negative electrode of described 3rd diode is connected to the collector electrode of described second power switch pipe, the collector electrode of described second power switch pipe is connected to the high voltage input of described Intelligent Power Module, the base stage of described second power switch pipe is as the input of bridge arm circuit in each phase described, the emitter of described second power switch pipe is connected to the higher-pressure region power supply negative terminal of the corresponding phase of described Intelligent Power Module.Wherein, the second power switch pipe can be IGBT.

According to an embodiment of the present utility model, under each phase described, bridge arm circuit comprises: the 3rd power switch pipe and the 4th diode, the anode of described 4th diode is connected to the emitter of described 3rd power switch pipe, the negative electrode of described 4th diode is connected to the collector electrode of described 3rd power switch pipe, the collector electrode of described 3rd power switch pipe is connected to the anode of described 3rd diode in corresponding upper bridge arm circuit, the base stage of described 3rd power switch pipe is as the input of bridge arm circuit under each phase described, the emitter of described 3rd power switch pipe is as the low reference voltage end of the corresponding phase of described Intelligent Power Module.Wherein, the 3rd power switch pipe can be IGBT.

According to an embodiment of the present utility model, the voltage of the high voltage input of described Intelligent Power Module is 300V.

According to an embodiment of the present utility model, between the anode of each phase higher-pressure region power supply of described Intelligent Power Module and negative terminal, be connected with filter capacitor.

According to the embodiment of the utility model second aspect, also proposed a kind of air conditioner, comprising: as the Intelligent Power Module described in above-mentioned any one embodiment.

Additional aspect of the present utility model and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present utility model.

Accompanying drawing explanation

Above-mentioned and/or additional aspect of the present utility model and advantage will become obvious and easy understand from accompanying drawing below combining to the description of embodiment, wherein:

Fig. 1 shows the structural representation of the Intelligent Power Module in correlation technique;

Fig. 2 shows the external circuit schematic diagram of Intelligent Power Module;

Fig. 3 shows current signal and triggers the out-of-work waveform schematic diagram of Intelligent Power Module;

Fig. 4 shows the waveform schematic diagram of the noise that the Intelligent Power Module in correlation technique produces;

Fig. 5 shows the structural representation of the Intelligent Power Module according to embodiment of the present utility model;

Fig. 6 shows the internal structure schematic diagram of the adaptive circuit according to embodiment of the present utility model.

Embodiment

In order to more clearly understand above-mentioned purpose of the present utility model, feature and advantage, below in conjunction with the drawings and specific embodiments, the utility model is further described in detail.It should be noted that, when not conflicting, the feature in the embodiment of the application and embodiment can combine mutually.

Set forth a lot of detail in the following description so that fully understand the utility model; but; the utility model can also adopt other to be different from other modes described here and implement, and therefore, protection range of the present utility model is not by the restriction of following public specific embodiment.

Fig. 5 shows the structural representation of the Intelligent Power Module according to embodiment of the present utility model.

As shown in Figure 5, according to the Intelligent Power Module of embodiment of the present utility model, comprising: HVIC pipe 1101 and adaptive circuit 1105.

The VCC of HVIC pipe 1101 holds the low-pressure area power supply anode VDD as Intelligent Power Module 1100, and VDD is generally 15V;

Inner at HVIC pipe 1101:

ITRIP end connects the first input end of adaptive circuit 1105; PININP end connects the second input of adaptive circuit 1105; VCC end connects the power supply anode of adaptive circuit 1105; GND end connects the power supply negative terminal of adaptive circuit 1105; The output of adaptive circuit 1105 is designated as ICON, for the validity of control HIN1 ~ HIN3, LIN1 ~ LIN3, PFCINP signal.

HVIC pipe 1101 inside also has boostrap circuit structure as follows:

VCC end is connected with the anode of bootstrap diode 1102, bootstrap diode 1103, bootstrap diode 1104; The negative electrode of bootstrap diode 1102 is connected with the VB1 of HVIC pipe 1101; The negative electrode of bootstrap diode 1103 is connected with the VB2 of HVIC pipe 1101; The negative electrode of bootstrap diode 1104 is connected with the VB3 of HVIC pipe 1101.

HVIC pipe 1101 HIN1 end for Intelligent Power Module 1100 U phase on brachium pontis signal input part UHIN; HVIC pipe 1101 HIN2 end for Intelligent Power Module 1100 V phase on brachium pontis signal input part VHIN; HVIC pipe 1101 HIN3 end for Intelligent Power Module 1100 W phase on brachium pontis signal input part WHIN; The LIN1 end of HVIC pipe 1101 is the lower brachium pontis signal input part ULIN of U phase of Intelligent Power Module 1100; The LIN2 end of HVIC pipe 1101 is the lower brachium pontis signal input part VLIN of V phase of Intelligent Power Module 1100; The LIN3 end of HVIC pipe 1101 is the lower brachium pontis signal input part WLIN of W phase of Intelligent Power Module 1100; The ITRIP of HVIC pipe 1101 holds as the MTRIP of Intelligent Power Module 1100 holds; The PFCINP of HVIC pipe 1101 holds the PFC control input end PFCIN as Intelligent Power Module 100; The GND of HVIC pipe 1101 holds the low-pressure area power supply negative terminal COM as Intelligent Power Module 1100.Wherein, Intelligent Power Module 1100 UHIN, VHIN, WHIN, ULIN, VLIN, WLIN six tunnel input and PFCIN termination receive the input signal of 0V or 5V.

The VB1 end of HVIC pipe 1101 connects one end of electric capacity 1131, and as the U phase higher-pressure region power supply anode UVB of Intelligent Power Module 1100; The HO1 end of HVIC pipe 1101 is connected with the grid of brachium pontis IGBT pipe 1121 in U phase; The VS1 end of HVIC pipe 1101 is connected with the anode of the emitter-base bandgap grading of IGBT pipe 1121, FRD pipe 1111, the collector electrode of the lower brachium pontis IGBT pipe 1124 of U phase, the negative electrode of FRD pipe 1114, the other end of electric capacity 1131, and as the U phase higher-pressure region power supply negative terminal UVS of Intelligent Power Module 1100.

The VB2 end of HVIC pipe 1101 connects one end of electric capacity 1132, and as the V phase higher-pressure region power supply anode VVB of Intelligent Power Module 1100; The HO2 end of HVIC pipe 1101 is connected with the grid of brachium pontis IGBT pipe 1123 in V phase; The VS2 end of HVIC pipe 1101 is connected with the anode of the emitter-base bandgap grading of IGBT pipe 1122, FRD pipe 1112, the collector electrode of the lower brachium pontis IGBT pipe 1125 of V phase, the negative electrode of FRD pipe 1115, the other end of electric capacity 1132, and as the V phase higher-pressure region power supply negative terminal VVS of Intelligent Power Module 1100.

The VB3 end of HVIC pipe 1101 connects one end of electric capacity 1133, as the W phase higher-pressure region power supply anode WVB of Intelligent Power Module 1100; The HO3 end of HVIC pipe 1101 is connected with the grid of brachium pontis IGBT pipe 1123 in W phase; The VS3 end of HVIC pipe 1101 is connected with the anode of the emitter-base bandgap grading of IGBT pipe 1123, FRD pipe 1113, the collector electrode of the lower brachium pontis IGBT pipe 1126 of W phase, the negative electrode of FRD pipe 1116, the other end of electric capacity 1133, and as the W phase higher-pressure region power supply negative terminal WVS of Intelligent Power Module 1100.

The LO1 end of HVIC pipe 1101 is connected with the grid of IGBT pipe 1124; The LO2 end of HVIC pipe 1101 is connected with the grid of IGBT pipe 1125; The LO3 end of HVIC pipe 1101 is connected with the grid of IGBT pipe 1126; The emitter-base bandgap grading of IGBT pipe 1124 is connected with the anode of FRD pipe 1114, and as the U phase low reference voltage end UN of Intelligent Power Module 1100; The emitter-base bandgap grading of IGBT pipe 1125 is connected with the anode of FRD pipe 1115, and as the V phase low reference voltage end VN of Intelligent Power Module 1100; The emitter-base bandgap grading of IGBT pipe 1126 is connected with the anode of FRD pipe 1116, and as the W phase low reference voltage end WN of Intelligent Power Module 1100.

VDD is HVIC pipe 1101 power supply anode, and GND is the power supply negative terminal of HVIC pipe 1101; VDD-GND voltage is generally 15V; VB1 and VS1 is respectively positive pole and the negative pole of the power supply of U phase higher-pressure region, and HO1 is the output of U phase higher-pressure region; VB2 and VS2 is respectively positive pole and the negative pole of the power supply of V phase higher-pressure region, and HO2 is the output of V phase higher-pressure region; VB3 and VS3 is respectively positive pole and the negative pole of the power supply of U phase higher-pressure region, and HO3 is the output of W phase higher-pressure region; LO1, LO2, LO3 are respectively the output of U phase, V phase, W phase low-pressure area.

The PFCO end of HVIC pipe 1101 is connected with the grid of IGBT pipe 1127; The emitter-base bandgap grading of IGBT pipe 1127 is connected with the anode of FRD pipe 1117, and as the PFC low reference voltage end-VP of Intelligent Power Module 1100; The collector electrode of IGBT pipe 1127 is connected with the anode of the negative electrode of FRD pipe 1117, FRD pipe 1131, and holds as the PFC of Intelligent Power Module 1100;

The negative electrode of the collector electrode of the collector electrode of the collector electrode of IGBT pipe 1121, the negative electrode of FRD pipe 1111, IGBT pipe 1122, the negative electrode of FRD pipe 1112, IGBT pipe 1123, the negative electrode of FRD pipe 1113, FRD pipe 1131 is connected, and as the high voltage input P of Intelligent Power Module 1100, P generally meets 300V.

The effect of HVIC pipe 1101 is:

When ICON is high level, the logic input signal of 0 of input HIN1, HIN2, HIN3 or 5V is passed to output HO1, HO2, HO3 respectively, the signal of LIN1, LIN2, LIN3 is passed to output LO1, LO2, LO3 respectively, the signal of PFCINP is passed to output PFCO, wherein HO1 be the logic output signal of VS1 or VS1+15V, the HO2 logic output signal that is VS2 or VS2+15V, the HO3 logic output signal that is VS3 or VS3+15V, LO1, LO2, LO3, PFCO are the logic output signals of 0 or 15V;

When ICON is low level, HO1, HO2, HO3, LO1, LO2, LO3, PFCO are all set to low level.

The effect of adaptive circuit 1105 is:

At the rising edge of the PFCINP of HVIC pipe 1101, the signal of adaptive circuit 1105 couples of ITRIP carries out secondary detection, first time, the voltage that detects was higher than a certain particular value, and the voltage of ITRIP that detects of second time higher than first time time, ICON output low level; When first time the voltage that detects lower than a certain particular value, although or first time, the ITRIP voltage that detects higher than a certain particular value second time of the voltage that detects was lower than first time time, ICON keeps enable output, namely exports high level;

After the rising edge of the PFCINP of HVIC pipe 1101, the first input end of adaptive circuit 1105 detects the voltage of an ITRIP in real time, and ICON exports high level or low level according to the voltage swing of ITRIP.

In an embodiment of the present utility model, the particular circuit configurations schematic diagram of adaptive circuit 1105 as shown in Figure 6, is specially:

PFCINP connects the input of not gate 2001, not gate 2003, not gate 2011, not gate 2013; The output of not gate 2001 connects the input of not gate 2002; The output of not gate 2003 connects one end of electric capacity 2008, the input of not gate 2004; The output of not gate 2004 connects one end of electric capacity 2009, the input of not gate 2005; Another termination GND of electric capacity 2008; Another termination GND of electric capacity 2009;

One of them input of the output termination NAND gate 2006 of not gate 2002; Another input of the output termination NAND gate 2006 of not gate 2005; The input of the output NAND gate 2007 of NAND gate 2006 is connected; One of them input of output termination NAND gate 2025 of not gate 2007 and the control end of analog switch 2027;

The output of not gate 2011 connects the input of not gate 2012; The output of not gate 2013 connects the input of not gate 2014; The output of not gate 2014 connects one end of electric capacity 2019, the input of not gate 2015; Another termination GND of electric capacity 2019; One of them input of the output termination NAND gate 2016 of not gate 2012; Another input of the output termination NAND gate 2016 of not gate 2015; The input of the output NAND gate 2017 of NAND gate 2016 is connected; The R end of the output termination rest-set flip-flop 2024 of not gate 2017;

ITRIP holds and is connected with the positive input terminal of voltage comparator 2010, the positive input terminal of voltage comparator 2023, the input of AD converter 2021; The anode of voltage source 2018 is connected with the negative input end of voltage comparator 2010; The negative terminal of voltage source 2018 meets GND; The output of voltage comparator 2010 is connected with 0 selecting side of one of them input of NAND gate 2025, analog switch 2027; The output of AD converter 2021 is connected with the input of D/A converter 2022; The output of D/A converter 2022 is connected with the negative input end of voltage comparator 2023; The output of voltage comparator 2023 is held with the S of rest-set flip-flop 2024 and is connected; The Q end of rest-set flip-flop 2024 is connected with one of them input of NAND gate 2025;

The output of NAND gate 2025 connects the input of not gate 2026; 1 selecting side of the output connecting analog switch 2027 of not gate 2026; The input of the fixing termination not gate 2020 of analog switch 2027; The output termination ICON of not gate 2020.

Operation principle and the key parameter value of above-described embodiment are below described:

Because the time-lag action of electric capacity 2019, at the rising edge of the signal of PFCINP, A point generation burst pulse; Because the time-lag action of electric capacity 2008 and electric capacity 2009, at the rising edge of the signal of PFCINP, the pulse that B point generation one is larger than A point burst pulse;

At B point impulse duration, 1 selecting side of analog switch 2027 is connected with the stiff end of analog switch 2027; Otherwise 0 selecting side of analog switch 2027 is connected with the stiff end of analog switch 2027;

When 0 selecting side of analog switch 2027 is connected with the stiff end of analog switch 2027: ITRIP signal compares with the voltage V1 of voltage source 2018, when ITRIP voltage is higher than V1, ICON output low level, otherwise ICON exports high level;

When 1 selecting side of analog switch 2027 is connected with the stiff end of analog switch 2027: after the R of rest-set flip-flop 2024 holds the high level held by A to reset, NAND gate 2025 exports high level, and after not gate 2026 and not gate 2020, ICON initially exports high level;

ITIRP voltage compares with the voltage V1 of voltage comparator 2018:

When ITRIP voltage is less than V1 voltage, NAND gate 2025 exports high level, and after not gate 2026 and not gate 2020, it is constant that ICON continues to export high level;

When ITRIP voltage is greater than V1 voltage, this flashy voltage of ITRIP is after AD converter 2021 and D/A converter 2022, as the comparative voltage V2 of voltage comparator 2023 negative terminal, the duration of conversion is designated as T, and the voltage V3 of ITRIP after T time and voltage V2 compares:

When V3 is less than V2, showing that the voltage overshoot of ITRIP is in reduction, may be noise, voltage comparator 2023 output low level, then the low level of the Q end of rest-set flip-flop 2024 is constant, and NAND gate 2025 exports high level, after not gate 2026 and not gate 2020, it is constant that ICON continues to export high level;

When V3 is greater than V2, show that the voltage overshoot of ITRIP is in lasting increase, there is having a good chance of overcurrent, voltage comparator 2023 exports high level, the Q end of rest-set flip-flop 2024 is set to high level, then three inputs of NAND gate 2025 are all high level, and the output of NAND gate 2025 is low level, after not gate 2026 and not gate 2020, ICON output low level.

The minimum dimension that not gate 2013 and not gate 2014 can select technique to allow, the value NAND gate 2013 of not gate 2011 is same, the value NAND gate 2014 of not gate 2012 is same, the value of electric capacity 2019 can be 3 ~ 5pF, then the width of the burst pulse of A point is at about 100ns, is enough to rest-set flip-flop 2024 is resetted;

The minimum dimension that not gate 2003 and not gate 2004 can select technique to allow, the value NAND gate 2003 of not gate 2001 is same, the value NAND gate 2004 of not gate 2002 is same, the value of electric capacity 2009 and electric capacity 2019 are together, the value of electric capacity 2008 can be 15 ~ 25pF, then the width of the pulse of B point is at 350ns ~ 550ns, whether this time is the time that noise carries out secondary-confirmation to the voltage of ITRIP just, if this time is too short, then larger to the erroneous judgement probability of ITIRP voltage, if this overlong time, then can be excessively slow to the promptness of ITIRP voltage response;

The voltage of voltage source 2018 can be set to 0.5V, also 0.7V can be set to, the value of milliohm resistance connect according to ITRIP outside and determine, the magnitude of voltage of the value adaptation voltage source 2018 of milliohm resistance that also can be external, usually, the voltage of voltage source 2018 is unsuitable too low, otherwise the probability of false triggering is very high, also unsuitable too high, otherwise the resistance of outside institute connecting resistance can be very large, cause the power requirement of outside milliohm resistance very high, increase system cost;

The total time delay design of AD converter 2021 and D/A converter 2022 is at 200 ~ 300ns, this time is T, then V3 voltage be V2 voltage after the voltage of time point of 200 ~ 300ns, judge that ITRIP voltage is still greater than V1 and continues to increase after 200 ~ 300ns, then the exception of ITRIP voltage increases not because the probability caused the reverse recovery time of the FRD pipe 1131 of PFCINP control is very large, otherwise, if judge that ITRIP voltage is still greater than V1 after 200 ~ 300ns but lasting reduction or ITRIP voltage are less than V1 after 200 ~ 300ns, then the exception of ITRIP voltage increases because the probability caused the reverse recovery time of the FRD pipe 1131 of PFCINP control is very large.

From the technical scheme of above-described embodiment, the Intelligent Power Module that the utility model proposes and existing Intelligent Power Module completely compatible, can directly replace with existing Intelligent Power Module.PFCINP high level moment, if the voltage fluctuation of ITRIP be because circuit noise cause, so ITRIP voltage be one continue reduce process, by secondary detection can filtering because of circuit noise cause misoperation may; If from real overcurrent during the voltage fluctuation of ITRIP, so ITRIP voltage is a process continued to increase, after secondary detection confirms, output low level makes the utility model Intelligent Power Module quit work and forms protection in time.And after PFCINP high level, Intelligent Power Module system of the present utility model enters ITRIP routine and judges detected state, noise suppressed function is cancelled, and can make reaction in time to the change in voltage of pin thus provide timely protection to Intelligent Power Module.

More than be described with reference to the accompanying drawings the technical solution of the utility model, the utility model proposes a kind of new Intelligent Power Module, under guaranteeing that Intelligent Power Module has the prerequisite of high reliability and high-adaptability, can effectively reduce Intelligent Power Module by the probability of false triggering.

The foregoing is only preferred embodiment of the present utility model, be not limited to the utility model, for a person skilled in the art, the utility model can have various modifications and variations.All within spirit of the present utility model and principle, any amendment done, equivalent replacement, improvement etc., all should be included within protection range of the present utility model.

Claims

1. an Intelligent Power Module, is characterized in that, comprising:

Brachium pontis signal input part, three-phase low reference voltage end, current detecting end and PFC control input end under brachium pontis signal input part, three-phase on three-phase;

HVIC manages, described HVIC pipe is provided with the terminals being connected to brachium pontis signal input part under brachium pontis signal input part and described three-phase on described three-phase respectively, and correspond to the first port of described current detecting end and correspond to the second port of described PFC control input end, described first port is connected with described current detecting end by connecting line, and described second port is connected with described PFC control input end by connecting line;

Sampling resistor, described three-phase low reference voltage end and described current detecting end are all connected to the first end of described sampling resistor, and the second end of described sampling resistor is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module;

Adaptive circuit, the power supply positive pole of described adaptive circuit and negative pole are connected to low-pressure area power supply anode and the negative terminal of described Intelligent Power Module respectively, the first input end of described adaptive circuit is connected to described first port, second input of described adaptive circuit is connected to described second port, and the output of described adaptive circuit is as the Enable Pin of described HVIC pipe;

2. Intelligent Power Module according to claim 1, is characterized in that:

Described adaptive circuit is when the input signal of described second input is in rising edge, when the result of the input signal of described first input end being carried out to twice detection is magnitude of voltage higher than predetermined value, export the enable signal of the first level, to forbid the work of described HVIC pipe; Otherwise, export the enable signal of second electrical level, to allow the work of described HVIC pipe;

3. Intelligent Power Module according to claim 1, is characterized in that, described adaptive circuit comprises:

4. Intelligent Power Module according to claim 1, is characterized in that, described HVIC pipe is also provided with the signal output part of PFC drive circuit, described Intelligent Power Module also comprises:

First power switch pipe and the first diode, the anode of described first diode is connected to the emitter of described first power switch pipe, the negative electrode of described first diode is connected to the collector electrode of described first power switch pipe, the collector electrode of described first power switch pipe is connected to the anode of the second diode, the negative electrode of described second diode is connected to the high voltage input of described Intelligent Power Module, the base stage of described first power switch pipe is connected to the signal output part of described PFC drive circuit, the emitter of described first power switch pipe is as the PFC low reference voltage end of described Intelligent Power Module, the collector electrode of described first power switch pipe is held as the PFC of described Intelligent Power Module.

5. Intelligent Power Module according to any one of claim 1 to 4, is characterized in that, also comprises: boostrap circuit, and described boostrap circuit comprises:

First bootstrap diode, the anode of described first bootstrap diode is connected to the low-pressure area power supply anode of described Intelligent Power Module, and the negative electrode of described first bootstrap diode is connected to the U phase higher-pressure region power supply anode of described Intelligent Power Module;

Second bootstrap diode, the anode of described second bootstrap diode is connected to the low-pressure area power supply anode of described Intelligent Power Module, and the negative electrode of described second bootstrap diode is connected to the V phase higher-pressure region power supply anode of described Intelligent Power Module;

3rd bootstrap diode, the anode of described 3rd bootstrap diode is connected to the low-pressure area power supply anode of described Intelligent Power Module, and the negative electrode of described 3rd bootstrap diode is connected to the W phase higher-pressure region power supply anode of described Intelligent Power Module.

6. Intelligent Power Module according to any one of claim 1 to 4, is characterized in that, also comprises:

Bridge arm circuit on three-phase, in each phase on described three-phase in bridge arm circuit, the input of bridge arm circuit is connected to the signal output part of corresponding phase in the three-phase high-voltage district of described HVIC pipe;

Bridge arm circuit under three-phase, under each phase under described three-phase in bridge arm circuit, the input of bridge arm circuit is connected to the signal output part of corresponding phase in the three-phase low-voltage district of described HVIC pipe.

7. Intelligent Power Module according to claim 6, is characterized in that, in each phase described, bridge arm circuit comprises:

Second power switch pipe and the 3rd diode, the anode of described 3rd diode is connected to the emitter of described second power switch pipe, the negative electrode of described 3rd diode is connected to the collector electrode of described second power switch pipe, the collector electrode of described second power switch pipe is connected to the high voltage input of described Intelligent Power Module, the base stage of described second power switch pipe is as the input of bridge arm circuit in each phase described, and the emitter of described second power switch pipe is connected to the higher-pressure region power supply negative terminal of the corresponding phase of described Intelligent Power Module.

8. Intelligent Power Module according to claim 7, is characterized in that, under each phase described, bridge arm circuit comprises:

3rd power switch pipe and the 4th diode, the anode of described 4th diode is connected to the emitter of described 3rd power switch pipe, the negative electrode of described 4th diode is connected to the collector electrode of described 3rd power switch pipe, the collector electrode of described 3rd power switch pipe is connected to the anode of described 3rd diode in corresponding upper bridge arm circuit, the base stage of described 3rd power switch pipe is as the input of bridge arm circuit under each phase described, and the emitter of described 3rd power switch pipe is as the low reference voltage end of the corresponding phase of described Intelligent Power Module.

9. the Intelligent Power Module according to claim 7 or 8, it is characterized in that, the voltage of the high voltage input of described Intelligent Power Module is 300V, is connected with filter capacitor between the anode of each phase higher-pressure region power supply of described Intelligent Power Module and negative terminal.

10. an air conditioner, is characterized in that, comprising: Intelligent Power Module as claimed in any one of claims 1-9 wherein.