CN205141646U - Surge current suppressing circuit - Google Patents
Surge current suppressing circuit Download PDFInfo
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- CN205141646U CN205141646U CN201520840617.4U CN201520840617U CN205141646U CN 205141646 U CN205141646 U CN 205141646U CN 201520840617 U CN201520840617 U CN 201520840617U CN 205141646 U CN205141646 U CN 205141646U
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Abstract
The utility model is suitable for a surge current restraines the field, provides a surge current suppressing circuit, and its current input connects the USB interface of USB interface equipment, and current output terminal connects the back level circuit of USB interface equipment, surge current suppressing circuit includes: the connection is in current input with electronic switch module between the current output terminal, the connection is in current input with the time delay module of charging between the electronic switch module. The utility model discloses an electronic switch module and the surge current suppressing circuit that forms of time delay -Modular that charges can effectively restrain USB interface equipment import's instantaneous surge current, and simple structure, low cost, flexibility are high.
Description
Technical field
The utility model belongs to Inrush current restraining field, particularly relates to a kind of surge current suppression circuit.
Background technology
According to the pertinent regulations of USB association, the USB interface equipment being carried out plug and play by USB interface will by USBIF certification, in the startup moment of its USB interface input power, its surge current can not be greater than 2.5mA, and the moment surge current of the USB interface equipment that part is special can not be greater than 100mA.At present, common on market surging current suppression method is the protection IC using USB interface device-specific.
But special protection IC cost is higher, and circuit design succinct flexibly cannot be carried out according to the actual needs of user.
Utility model content
The object of the utility model embodiment is to provide a kind of surge current suppression circuit; the protection IC cost being intended to solve Inrush current restraining common in the market special is higher, and cannot carry out the problem of circuit design succinct flexibly according to the actual needs of user.
The utility model embodiment realizes like this, a kind of surge current suppression circuit, its current input terminal connects the USB interface of USB interface equipment, and current output terminal connects the late-class circuit of described USB interface equipment, it is characterized in that, described surge current suppression circuit comprises:
Be connected to the electronic switch module between described current input terminal and described current output terminal;
Be connected to the charging time delay module between described current input terminal and described electronic switch module.
Preferably, described electronic switch module comprises P-channel enhancement type field effect transistor Q1, and the drain electrode of described field effect transistor Q1 connects described current input terminal, source electrode connects described current output terminal, grid connects described charging time delay module.
Preferably, described charging time delay module comprises the delay capacitor C1 in order to suppress the transient high-current flowed into through described current input terminal, electronic switch module described in current input terminal, another termination described in described delay capacitor C1 mono-termination.
Preferably, described electronic switch module also comprises the filter capacitor C2 in order to filter out power ripple, and source electrode and the described current output terminal of described filter capacitor C2 one end and described field effect transistor Q1 connect altogether, other end ground connection.
Preferably, described electronic switch module also comprises the filter capacitor C3 in order to filter out power ripple, one end of one end of described filter capacitor C3 and the source electrode of described field effect transistor Q1, described current output terminal and described filter capacitor C2 connects altogether, and the other end of described filter capacitor C3 and the other end of described filter capacitor C2 are connected to ground altogether.
Preferably, described electronic switch module also comprises the filter capacitor C4 in order to filter out power ripple, one end of described filter capacitor C4 and the source electrode of described field effect transistor Q1, described current output terminal, one end of described filter capacitor C2 and one end of described filter capacitor C3 connect altogether, and the other end of the other end of described filter capacitor C4 and the other end of described filter capacitor C2 and described filter capacitor C3 is connected to ground altogether.
Preferably, described charging time delay module also comprises divider resistance R1 and divider resistance R2, one end of one end of described divider resistance R1 and described current input terminal and described delay capacitor C1 connects altogether, the other end of described divider resistance R1 and described electronic switch module, the other end of described delay capacitor C1 and one end of described divider resistance R2 connect altogether, the other end ground connection of described divider resistance R2.
Preferably, described charging time delay module also comprises and is connected in parallel on described divider resistance R1 two ends, filter capacitor C5 in order to filter out power ripple.
Preferably, described charging time delay module also comprises and is connected in parallel on described divider resistance R2 two ends, filter capacitor C6 in order to filter out power ripple.
Preferably, described surge current suppression circuit also comprises current input terminal described in a termination, other end ground connection, filter capacitor C7 in order to filter out power ripple.
The surge current suppression circuit that the utility model provides, its beneficial effect is: the surge current suppression circuit combined by electronic switch module and charging time delay module, effectively can suppress the momentary surges electric current that USB interface equipment inputs; By the break-make using common field effect transistor to carry out control circuit, with low cost, flexibility is high; The time of the transient current suppressing USB interface equipment to input by delay capacitor, make user can select the delay capacitor of respective volume as required, to control the suppression time of electric current flexibly, the flexibility of circuit design is high, and structure is simple, with low cost; By arranging divider resistance in circuit, make user can select the resistance size of described divider resistance as required, to set the size of current by USB interface equipment flexibly; By setting some filter capacitors in circuit, effectively can suppress the power supply ripple in circuit, ensureing the stability of circuit; The field effect transistor that surge current suppression circuit provided by the utility model is only simple by structure, with low cost and some Resistor-Capacitor Units combine, effectively can suppress the moment surge current that USB interface equipment inputs, and can according to the parameter size changing corresponding components and parts, carry out the size of current of Circuit tuning, circuit is simple, flexible design, greatly reduces development and production cost, is suitable for extensive popularization.
Accompanying drawing explanation
Fig. 1 is the basic structure schematic diagram of the surge current suppression circuit that the utility model embodiment provides;
Fig. 2 is the circuit theory diagrams of the surge current suppression circuit that preferred embodiment of the present utility model provides.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
Fig. 1 is the basic structure schematic diagram of the surge current suppression circuit that the utility model embodiment provides.
As shown in Figure 1, the surge current suppression circuit that the utility model embodiment provides, its current input terminal 10 connects the USB interface of USB interface equipment, and current output terminal 20 connects the late-class circuit of described USB interface equipment, and described surge current suppression circuit comprises:
Be connected to the electronic switch module 30 between described current input terminal 10 and described current output terminal 20;
Be connected to the charging time delay module 40 between described current input terminal 10 and described electronic switch module 30.
By the surge current suppression circuit that electronic switch module and charging time delay module combine, the momentary surges electric current that USB interface equipment inputs effectively can be suppressed.
In a particular application, when described surge current suppression circuit dispatches from the factory, between its current input terminal and current output terminal, series connection is pasted with a 0 reserved Ohmic resistance, and when not needing the Surge suppression function using surge current suppression circuit, electric current directly passes through by this 0 Ohmic resistance; When needing the Surge suppression function using described surge restraint circuit, then need 0 Ohmic resistance of attachment to take off.
Fig. 2 is the circuit theory diagrams of the surge current suppression circuit that preferred embodiment of the present utility model provides.
As shown in Figure 2, in a preferred embodiment, described electronic switch module 30 comprises P-channel enhancement type field effect transistor Q1, and the drain electrode of described field effect transistor Q1 connects described current input terminal 10, source electrode connects described current output terminal 20, grid connects described charging time delay module 40;
Described charging time delay module 40 comprises the delay capacitor C1 in order to suppress the transient high-current flowed into through described current input terminal 10, the grid of the field effect transistor Q1 of electronic switch module 30 described in current input terminal 10, another termination described in described delay capacitor C1 mono-termination;
Described electronic switch module 30 also comprises the filter capacitor C2 in order to filter out power ripple, and source electrode and the described current output terminal 20 of described filter capacitor C2 one end and described field effect transistor Q1 connect altogether, other end ground connection;
Described electronic switch module 30 also comprises the filter capacitor C3 in order to filter out power ripple, one end of one end of described filter capacitor C3 and the source electrode of described field effect transistor Q1, described current output terminal 20 and described filter capacitor C2 connects altogether, and the other end of described filter capacitor C3 and the other end of described filter capacitor C2 are connected to ground altogether;
Described electronic switch module 30 also comprises the filter capacitor C4 in order to filter out power ripple, one end of described filter capacitor C4 and the source electrode of described field effect transistor Q1, described current output terminal 20, one end of described filter capacitor C2 and one end of described filter capacitor C3 connect altogether, and the other end of the other end of described filter capacitor C4 and the other end of described filter capacitor C2 and described filter capacitor C3 is connected to ground altogether;
Described charging time delay module 40 also comprises divider resistance R1 and divider resistance R2, one end of one end of described divider resistance R1 and described current input terminal 10 and described delay capacitor C1 connects altogether, one end of the grid of the other end of described divider resistance R1 and the field effect transistor Q1 of described electronic switch module 30, the other end of described delay capacitor C1 and described divider resistance R2 connects altogether, the other end ground connection of described divider resistance R2;
Described charging time delay module 40 also comprises and is connected in parallel on described divider resistance R1 two ends, filter capacitor C5 in order to filter out power ripple;
Described charging time delay module 40 also comprises and is connected in parallel on described divider resistance R2 two ends, filter capacitor C6 in order to filter out power ripple;
Described surge current suppression circuit also comprises current input terminal 10 described in a termination, other end ground connection, filter capacitor C7 in order to filter out power ripple.
In the present embodiment, described field effect transistor Q1 is P channel depletion type field effect transistor.
For the circuit shown in Fig. 2, the operation principle of the surge current suppression circuit that the utility model embodiment provides is:
1, operation principle during Inrush current restraining is not carried out: during USB interface equipment input external power source, electric current flows to through described current input terminal, through drain electrode and the source electrode of field effect transistor Q1, exported to the late-class circuit of USB interface equipment by described current output terminal;
2, carry out operation principle during moment Inrush current restraining: the moment of USB interface equipment input external power source, electric current flows to through described current input terminal, first delay capacitor C1 is charged, the voltage of the power supply that the grid voltage of field effect transistor Q1 is inputted close to USB interface equipment, the grid of field effect transistor Q1 is made to be in high level, the now drain electrode of field effect transistor Q1 and source electrode end not conducting, thus the transient current making USB interface equipment input can not through the drain electrode of field effect transistor Q1 and source electrode, and exported to the late-class circuit of USB interface equipment by current output terminal, along with delay capacitor C1 charge capacity slowly rise, charging current slowly reduces, the grid voltage of field effect transistor Q1 slowly reduces, the drain electrode of field effect transistor Q1 and source voltage are slowly reduced, and the internal channel of field effect transistor Q1 is slowly opened, when delay capacitor C1 is full of electricity, by divider resistance R1 and divider resistance R2, dividing potential drop is carried out to the grid voltage of field effect transistor Q1, the grid voltage of field effect transistor Q1 is made to be stabilized on scheduled voltage, thus the internal channel of field effect transistor Q1 is opened when allowing the maximum scheduled current passed through, allow electric current slowly flow through, when USB interface equipment stops input external power source, delay capacitor C1 is discharged over the ground by divider resistance R2, makes delay capacitor C1 revert to original electroless state.
In a particular application, when the supply voltage of the input of described USB interface equipment is the 5V voltage of Universal USB interface, field effect transistor Q1 should select the maximum field effect transistor being greater than 500mA by electric current of drain-source pole; By arranging divider resistance R1 and the divider resistance R2 of respective resistance values size, adjust the drain-source voltage of field effect transistor Q1, thus the maximum current size of USB interface equipment is flow through in adjustment; By the time delay resistance C1 of setting corresponding capacitance amount size, adjust effective Surge suppression time of described surge current suppression circuit.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all do within spirit of the present utility model and principle any amendment, equivalent to replace and improvement etc., all should be included within protection range of the present utility model.
Claims (10)
1. a surge current suppression circuit, its current input terminal connects the USB interface of USB interface equipment, and current output terminal connects the late-class circuit of described USB interface equipment, it is characterized in that, described surge current suppression circuit comprises:
Be connected to the electronic switch module between described current input terminal and described current output terminal;
Be connected to the charging time delay module between described current input terminal and described electronic switch module.
2. direct current surge restraint circuit as claimed in claim 1, it is characterized in that, described electronic switch module comprises P-channel enhancement type field effect transistor Q1, and the drain electrode of described field effect transistor Q1 connects described current input terminal, source electrode connects described current output terminal, grid connects described charging time delay module.
3. direct current surge restraint circuit as claimed in claim 1 or 2, it is characterized in that, described charging time delay module comprises the delay capacitor C1 in order to suppress the transient high-current flowed into through described current input terminal, electronic switch module described in current input terminal, another termination described in described delay capacitor C1 mono-termination.
4. direct current surge restraint circuit as claimed in claim 2, it is characterized in that, described electronic switch module also comprises the filter capacitor C2 in order to filter out power ripple, and source electrode and the described current output terminal of described filter capacitor C2 one end and described field effect transistor Q1 connect altogether, other end ground connection.
5. direct current surge restraint circuit as claimed in claim 4, it is characterized in that, described electronic switch module also comprises the filter capacitor C3 in order to filter out power ripple, one end of one end of described filter capacitor C3 and the source electrode of described field effect transistor Q1, described current output terminal and described filter capacitor C2 connects altogether, and the other end of described filter capacitor C3 and the other end of described filter capacitor C2 are connected to ground altogether.
6. direct current surge restraint circuit as claimed in claim 5, it is characterized in that, described electronic switch module also comprises the filter capacitor C4 in order to filter out power ripple, one end of described filter capacitor C4 and the source electrode of described field effect transistor Q1, described current output terminal, one end of described filter capacitor C2 and one end of described filter capacitor C3 connect altogether, and the other end of the other end of described filter capacitor C4 and the other end of described filter capacitor C2 and described filter capacitor C3 is connected to ground altogether.
7. direct current surge restraint circuit as claimed in claim 3, it is characterized in that, described charging time delay module also comprises divider resistance R1 and divider resistance R2, one end of one end of described divider resistance R1 and described current input terminal and described delay capacitor C1 connects altogether, the other end of described divider resistance R1 and described electronic switch module, the other end of described delay capacitor C1 and one end of described divider resistance R2 connect altogether, the other end ground connection of described divider resistance R2.
8. direct current surge restraint circuit as claimed in claim 7, is characterized in that, described charging time delay module also comprises and is connected in parallel on described divider resistance R1 two ends, filter capacitor C5 in order to filter out power ripple.
9. as claimed in claim 7 or 8 direct current surge restraint circuit, is characterized in that, described charging time delay module also comprises and is connected in parallel on described divider resistance R2 two ends, filter capacitor C6 in order to filter out power ripple.
10. direct current surge restraint circuit as claimed in claim 1, is characterized in that, described surge current suppression circuit also comprises current input terminal described in a termination, other end ground connection, filter capacitor C7 in order to filter out power ripple.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520840617.4U CN205141646U (en) | 2015-10-27 | 2015-10-27 | Surge current suppressing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520840617.4U CN205141646U (en) | 2015-10-27 | 2015-10-27 | Surge current suppressing circuit |
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| Publication Number | Publication Date |
|---|---|
| CN205141646U true CN205141646U (en) | 2016-04-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520840617.4U Active CN205141646U (en) | 2015-10-27 | 2015-10-27 | Surge current suppressing circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105871188A (en) * | 2016-05-18 | 2016-08-17 | 青岛海信移动通信技术股份有限公司 | Surge protection circuit and mobile terminal |
| CN107565803A (en) * | 2017-09-20 | 2018-01-09 | 中国电子科技集团公司第四十三研究所 | Vast capacity inputs the surge current suppression circuit and suppressing method of storage capacitor |
| CN110460029A (en) * | 2019-09-05 | 2019-11-15 | 中国科学院长春光学精密机械与物理研究所 | A kind of power supply-distribution system |
| CN110676828A (en) * | 2019-11-04 | 2020-01-10 | 中国振华集团永光电子有限公司（国营第八七三厂） | Direct current surge suppression circuit |
-
2015
- 2015-10-27 CN CN201520840617.4U patent/CN205141646U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105871188A (en) * | 2016-05-18 | 2016-08-17 | 青岛海信移动通信技术股份有限公司 | Surge protection circuit and mobile terminal |
| CN107565803A (en) * | 2017-09-20 | 2018-01-09 | 中国电子科技集团公司第四十三研究所 | Vast capacity inputs the surge current suppression circuit and suppressing method of storage capacitor |
| CN110460029A (en) * | 2019-09-05 | 2019-11-15 | 中国科学院长春光学精密机械与物理研究所 | A kind of power supply-distribution system |
| CN110676828A (en) * | 2019-11-04 | 2020-01-10 | 中国振华集团永光电子有限公司（国营第八七三厂） | Direct current surge suppression circuit |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Longgang District of Shenzhen City, Guangdong province 518116 Ping Street Takahashi Industrial Park East Area Patentee after: SHENZHE GUANXU ELECTRONIC CO., LTD. Address before: Longgang District of Shenzhen City, Guangdong province 518116 Ping Street Takahashi Industrial Park East Area Patentee before: Shenzhen Grandsun Electronic Co., Ltd. |