CN204993132U - Control system for switch reluctance motor - Google Patents
Control system for switch reluctance motor Download PDFInfo
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- CN204993132U CN204993132U CN201520598236.XU CN201520598236U CN204993132U CN 204993132 U CN204993132 U CN 204993132U CN 201520598236 U CN201520598236 U CN 201520598236U CN 204993132 U CN204993132 U CN 204993132U
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Abstract
The utility model provides a control system for switch reluctance motor, it relates to motor control system. The utility model discloses a problem low to the calculation speed of electric motor rotor position and rotational speed in order to solve current switched reluctance motor, that system response speed is slow, the structure is complicated. The utility model discloses a position detection circuitry's of FPGA controller output hookup location signal processing module, position sigual processing module's output through cycle average value calculation module respectively with rotational speed calculation module, it establishs the connection to switch on time delay calculation module and open time delay calculation module, the output that switches on time delay calculation module and open time delay calculation module passes through the input that angel position control synthesizes the comprehensive module of module connection control signal, rotational speed calculation module's output is connected respectively to the soft nuclear of NIOSII through the bus, open time delay calculation module's input, time delay calculation module's input and PWM signal modules's input switch on. The utility model discloses corresponding speed is faster, and the control effect is better.
Description
Technical field
The utility model relates to electric machine control system, is specifically related to a kind of control system of switched reluctance machines, belongs to switched Reluctance Motor Control technical field.
Background technology
Switched reluctance motor is the novel controllable AC Variable-speed system of one developing rapidly with power electronics and microelectronics in recent ten years and occur, although adopted single-chip microcomputer and DSP etc. more flexible as the drive system of controller in the past, but switched reluctance machines is operated in synchronous regime, rotor-position signal is the foundation that each phase switching device carries out correct logic switch, adopt which kind of control mode all will process rotor-position signal and calculate in real time angle, and switched reluctance machines is when high-speed cruising, rotor-position signal frequency is high, position signalling process and angle are resolved and are occupied DSP or the most internal resource of single-chip microcomputer, control algolithm in DSP or single-chip microcomputer is caused to be difficult to effective realization, be unfavorable for the steady Effec-tive Function of switched reluctance machines.
Utility model content
The purpose of this utility model is low in order to solve the computational speed of existing switched reluctance machines to motor rotor position and rotating speed, and system response time is slow, the baroque problem of control system.
The technical solution of the utility model is: a kind of control system of switched reluctance machines, comprise FPGA controller, buffer circuit, power conversion circuit, position detecting circuit and switched reluctance machines, the output of described FPGA controller is by the buffer circuit that connects successively and power conversion circuit connecting valve reluctance motor, the input connecting valve reluctance motor of position detecting circuit, the output of position detecting circuit connects FPGA controller
Described FPGA controller comprises the soft core of NIOSII, bus, position signalling processing module, period average computing module, rotating speed computing module, open time delay computing module, conducting time delay computing module, Angle ambiguity integration module, pwm signal module and control signal integration module, the output link position signal processing module of described position detecting circuit, the output of position signalling processing module through period average computing module respectively with rotating speed computing module, conducting time delay computing module and open time delay computing module and connect, conducting time delay computing module and the input of output by Angle ambiguity integration module connection control signal integration module opening time delay computing module, the soft core of described NIOSII connects the output of rotating speed computing module respectively by bus, open the input of time delay computing module, the input of conducting time delay computing module and the input of pwm signal module, the input of the output connection control signal integration module of described pwm signal module, the output of control signal integration module connects buffer circuit.
The control system of described switched reluctance machines comprises phase current sensing circuit, described FPGA controller comprises fault-signal processing module and copped wave time delay generation module, phase current sensing circuit input end connects power conversion circuit, the output of phase current sensing circuit connects the input of bus and fault-signal processing module respectively, the output connection control signal integration module of fault-signal processing module, bus connects the input of copped wave time delay generation module, the output connection control signal integration module of copped wave time delay generation module.
Described power conversion circuit is asymmetrical half-bridge translation circuit mechanism, i.e. biswitch type translation circuit.
The control system of described switched reluctance machines comprises busbar voltage testing circuit and temperature sensing circuit, described busbar voltage testing circuit is connected power conversion circuit with the input of temperature sensing circuit, and busbar voltage testing circuit is connected the fault-signal processing module of FPGA controller with the output of temperature sensing circuit.
Described position detecting circuit comprises position transducer, photoelectric coupled circuit and voltage-regulating circuit, and the output of described position transducer is connected by the photoelectric coupled circuit of series connection and voltage-regulating circuit and FPGA controller.
The utility model compared with prior art has following effect: the utility model adds in fpga chip inside softly to be examined existing control algolithm and avoids exporting the information such as obtained rotor-position, rotating speed to independent digital processing chip as control system in the past and realize control algolithm, again the control information of gained is passed back, realize the comprehensive of pwm signal, control rate improves further.The program that in FPGA, position signalling process and angle are resolved is all executed in parallel, and the program of single-chip microcomputer or DSP is order execution, so fast by FPGA processing speed, be conducive to resolving high-frequency position signalling, owing to realizing control algolithm in the soft core of NIOSII, processor that need not be independent, while obtaining high processing rate, circuit area reduces greatly, and stability improves further.
Accompanying drawing explanation
Fig. 1, overall structure block diagram of the present utility model;
Fig. 2, power conversion circuit circuit diagram of the present utility model;
Fig. 3, the structured flowchart of FPGA controller inside in the utility model.
Embodiment
Accompanying drawings embodiment of the present utility model, the control system of a kind of switched reluctance machines of present embodiment, comprise FPGA controller, buffer circuit, power conversion circuit, position detecting circuit and switched reluctance machines, the output of described FPGA controller is by the buffer circuit that connects successively and power conversion circuit connecting valve reluctance motor, the input connecting valve reluctance motor of position detecting circuit, the output of position detecting circuit connects FPGA controller
Described FPGA controller comprises the soft core of NIOSII, bus, position signalling processing module, period average computing module, rotating speed computing module, open time delay computing module, conducting time delay computing module, Angle ambiguity integration module, pwm signal module and control signal integration module, the output link position signal processing module of described position detecting circuit, the output of position signalling processing module through period average computing module respectively with rotating speed computing module, conducting time delay computing module and open time delay computing module and connect, conducting time delay computing module and the input of output by Angle ambiguity integration module connection control signal integration module opening time delay computing module, the soft core of described NIOSII connects the output of rotating speed computing module respectively by bus, open the input of time delay computing module, the input of conducting time delay computing module and the input of pwm signal module, the input of the output connection control signal integration module of described pwm signal module, the output of control signal integration module connects buffer circuit.
The model of described FPGA controller is EP2C8Q208C8N, and the modules of its inside can adopt existing integrated circuit realize or change accordingly circuit according to actual needs.
The control system of described switched reluctance machines comprises phase current sensing circuit, described FPGA controller comprises fault-signal processing module and copped wave time delay generation module, phase current sensing circuit input end connects power conversion circuit, the output of phase current sensing circuit connects the input of bus and fault-signal processing module respectively, the output connection control signal integration module of fault-signal processing module, bus connects the input of copped wave time delay generation module, the output connection control signal integration module of copped wave time delay generation module.
The topological structure of described power inverter is the asymmetrical half-bridge translation circuit structure for IGBT and the HFA15TB60 type fly-wheel diode of APTGT150DA60T1G type forms.
The control system of described switched reluctance machines comprises busbar voltage testing circuit and temperature sensing circuit, described busbar voltage testing circuit is connected power conversion circuit with the input of temperature sensing circuit, and busbar voltage testing circuit is connected the fault-signal processing module of FPGA controller with the output of temperature sensing circuit.
Described position detecting circuit comprises position transducer, photoelectric coupled circuit and voltage-regulating circuit, described position transducer is placed on switched reluctance machines, and the output of position transducer is connected by the photoelectric coupled circuit of series connection and voltage-regulating circuit and FPGA controller.
Described position transducer sense switch magnetic resistance motor rotor position signalling is through light-coupled isolation, import into after voltage-regulating circuit in FPGA controller, disturbing pulse is filtered by FPGA interior location signal processing module, position signalling after time delay is used for motor position signal on the one hand and directly controls to export, this position signalling exports the break-make controlling each power tube in power conversion circuit through drive circuit, be used on the other hand detecting that position signalling jumps edge, the position signalling detected is as the baseline pulse of cycle rate counter, period average computing module is through calculating average period to the process of position signalling, rotating speed computing module lead to after one minute comprise tooth number of poles and average period product number calculate motor speed, acquired results imports the soft core of inner NIOSII into through bus.
The soft core of NIOSII carries out computing according to the rotor rotating speed imported into, the angle of conducting in the angle opened in power tube one-period in the power conversion circuit determined and power tube one-period, PWM period of wave and duty ratio, the copped wave simultaneously determined according to the current signal of AD sampling is given, copped wave time delay is given, and these signals spread out of through bus jointly.
Turn-on angle and angle of flow calculated value are respectively by opening time delay computing module and conducting time delay computing module calculates the count value opening time delay and conducting time delay, again through Angle ambiguity integration module opening delay count and conducting delay count converts output pulse to, copped wave is given given through copped wave time delay generation CMOS macro cell chopping signal with copped wave time delay, PWM cycle and duty ratio is given through PWM, CMOS macro cell pwm signal occurs, this three roads signal is in the control signal of control signal integration module generating power translation circuit.
Period average computing module is by ten grades of fifo circuits, comparison circuit, adder, trigger forms, the major function of fifo circuit is the periodic quantity of memory location signal, for ensureing the accuracy of computation of Period, fifo circuit reads the count value in nearly ten cycles, comparison circuit is utilized to pass through to compare and remove maximum 2 numerical value and minimum 2 numerical value, utilize the function of adder that remaining 6 are added up and carry out mean value computation, the average period of gained imports rotating speed computing module on the one hand and calculates for rotating speed, is used on the other hand opening time delay calculating and conducting time delay calculating.
Rotating speed computing module lead to after one minute comprise tooth number of poles and average period product number calculate motor speed, formula is as follows:
n＝60f/Z＝60(T*Z)
N is rotating speed, and f is frequency, and T is the cycle, and wherein Z is rotor tooth number of poles.Computer rotating speed imports the soft core of the inner NIOSII of FPGA into by bus.
Opening the function that time delay computing module mainly completes is exactly calculate to change into according to given turn-on angle to open delay count, by turn-on angle compared with rotor cycle angle, is multiplied by average period module and calculates the cycle and namely obtain opening time delay calculated value.In like manner can obtain conducting time delay calculated value, open time delay calculated value and conducting time delay calculated value converts output pulse to after Angle ambiguity output module.
The comprehensive phase current signal of fault-signal processing module, bus voltage signal, IGBT current signal, generate fault-signal and directly import control signal integration module into.
Control signal integration module, comprehensive angle control impuls, current chopping signal, voltage chopping signal and fault-signal generate control signal and export, and open shutoff through buffer circuit rear drive IGBT.
Add in FPGA inside that NIOSII is soft endorses the computing and controlling functions that realize universal cpu, the disposal ability of FPGA executed in parallel framework disposal ability far super general dsp processor serial execution framework in addition.Conventional DSP process chip is substituted using FPGA as control core, by to rotor-position signal fast processing, can realize reacting rapidly switch magnetoresistance motor rotor position, improve real-time control performance, thus further suppress the torque pulsation of switched reluctance machines.The switched reluctance motor controller using fpga chip to utilize SOPC technology to realize not only replaces the version utilizing DSP to serve as the complexity such as coprocessor as controller FPGA as controller or DSP in form, more significantly improve in processing speed, the switched Reluctance Motor Control System therefore utilizing FPGA to adopt SOPC technology to realize will have huge development space.
Claims (5)
1. the control system of a switched reluctance machines, comprise FPGA controller, buffer circuit, power conversion circuit, position detecting circuit and switched reluctance machines, the output of described FPGA controller is by the buffer circuit that connects successively and power conversion circuit connecting valve reluctance motor, the input connecting valve reluctance motor of position detecting circuit, the output of position detecting circuit connects FPGA controller, it is characterized in that:
Described FPGA controller comprises the soft core of NIOSII, bus, position signalling processing module, period average computing module, rotating speed computing module, open time delay computing module, conducting time delay computing module, Angle ambiguity integration module, pwm signal module and control signal integration module, the output link position signal processing module of described position detecting circuit, the output of position signalling processing module through period average computing module respectively with rotating speed computing module, conducting time delay computing module and open time delay computing module and connect, conducting time delay computing module and the input of output by Angle ambiguity integration module connection control signal integration module opening time delay computing module, the soft core of described NIOSII connects the output of rotating speed computing module respectively by bus, open the input of time delay computing module, the input of conducting time delay computing module and the input of pwm signal module, the input of the output connection control signal integration module of described pwm signal module, the output of control signal integration module connects buffer circuit.
2. the control system of a kind of switched reluctance machines according to claim 1, it is characterized in that: the control system of described switched reluctance machines comprises phase current sensing circuit, described FPGA controller comprises fault-signal processing module and copped wave time delay generation module, phase current sensing circuit input end connects power conversion circuit, the output of phase current sensing circuit connects the input of bus and fault-signal processing module respectively, the output connection control signal integration module of fault-signal processing module, bus connects the input of copped wave time delay generation module, the output connection control signal integration module of copped wave time delay generation module.
3. a kind of control system of switched reluctance machines according to claim 1 or claim 2, is characterized in that: described power conversion circuit is biswitch type translation circuit.
4. a kind of control system of switched reluctance machines according to claim 1 or claim 2, it is characterized in that: the control system of described switched reluctance machines comprises busbar voltage testing circuit and temperature sensing circuit, described busbar voltage testing circuit is connected power conversion circuit with the input of temperature sensing circuit, and busbar voltage testing circuit is connected the fault-signal processing module of FPGA controller with the output of temperature sensing circuit.
5. a kind of control system of switched reluctance machines according to claim 1 or claim 2, it is characterized in that: described position detecting circuit comprises position transducer, photoelectric coupled circuit and voltage-regulating circuit, the output of described position transducer is connected by the photoelectric coupled circuit of series connection and voltage-regulating circuit and FPGA controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520598236.XU CN204993132U (en) | 2015-08-10 | 2015-08-10 | Control system for switch reluctance motor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520598236.XU CN204993132U (en) | 2015-08-10 | 2015-08-10 | Control system for switch reluctance motor |
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| CN204993132U true CN204993132U (en) | 2016-01-20 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105515493A (en) * | 2016-01-21 | 2016-04-20 | 南通大学 | Switched reluctance variable speed motor controller for electric pick |
| CN105897073A (en) * | 2016-05-23 | 2016-08-24 | 上海交通大学 | Speed regulation system of switch reluctance machine |
| CN107979308A (en) * | 2016-10-21 | 2018-05-01 | 南京理工大学 | A kind of control system of switched reluctance machines |
| CN111025996A (en) * | 2019-12-27 | 2020-04-17 | 淄博京科电气有限公司 | RTU-based switched reluctance motor speed regulation communication system |
| CN113014179A (en) * | 2021-02-22 | 2021-06-22 | 珠海格力电器股份有限公司 | Motor control method and device, motor, storage medium and processor |
-
2015
- 2015-08-10 CN CN201520598236.XU patent/CN204993132U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105515493A (en) * | 2016-01-21 | 2016-04-20 | 南通大学 | Switched reluctance variable speed motor controller for electric pick |
| CN105515493B (en) * | 2016-01-21 | 2018-01-16 | 南通大学 | Electric pick switched reluctance variable speed machine controller |
| CN105897073A (en) * | 2016-05-23 | 2016-08-24 | 上海交通大学 | Speed regulation system of switch reluctance machine |
| CN107979308A (en) * | 2016-10-21 | 2018-05-01 | 南京理工大学 | A kind of control system of switched reluctance machines |
| CN111025996A (en) * | 2019-12-27 | 2020-04-17 | 淄博京科电气有限公司 | RTU-based switched reluctance motor speed regulation communication system |
| CN113014179A (en) * | 2021-02-22 | 2021-06-22 | 珠海格力电器股份有限公司 | Motor control method and device, motor, storage medium and processor |
| CN113014179B (en) * | 2021-02-22 | 2023-03-21 | 珠海格力电器股份有限公司 | Motor control method and device, motor, storage medium and processor |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160120 Termination date: 20170810 |
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| CF01 | Termination of patent right due to non-payment of annual fee |