CN113014179A

CN113014179A - Motor control method and device, motor, storage medium and processor

Info

Publication number: CN113014179A
Application number: CN202110198106.7A
Authority: CN
Inventors: 谢盛; 陈建清; 吴中建
Original assignee: Gree Electric Appliances Inc of Zhuhai
Current assignee: Gree Electric Appliances Inc of Zhuhai
Priority date: 2021-02-22
Filing date: 2021-02-22
Publication date: 2021-06-22
Anticipated expiration: 2041-02-22
Also published as: CN113014179B

Abstract

The invention discloses a control method and a control device for a motor, the motor, a storage medium and a processor, wherein the method comprises the following steps: sending enable signals, duty ratio signals and frequency signals of PWM waves of all power switching tubes in an inverter bridge of the motor to the FPGA by the microprocessor; under the condition that the microprocessor and the FPGA receive a turn-off signal of the PWM wave after electrification work, the FPGA turns off the PWM wave; when the FPGA receives the enable signal, the duty ratio signal and the frequency signal of the PWM wave, the FPGA controls the PWM wave according to the enable signal, the duty ratio signal and the frequency signal of the received PWM wave and outputs the controlled PWM. According to the scheme, the output of the PWM wave is controlled by adopting the FPGA, and the output capacity of the PWM wave can be improved.

Description

Motor control method and device, motor, storage medium and processor

Technical Field

The invention belongs to the technical field of motors, and particularly relates to a motor control method, a motor control device, a motor, a storage medium and a processor, in particular to a multipath symmetrical variable frequency Pulse Width Modulation (PWM) wave control and output method, a multipath symmetrical variable frequency PWM wave control and output device, a motor, a storage medium and a processor based on a Field Programmable Gate Array (FPGA).

Background

In the field of ultra-high speed motor control, since a control system of an ultra-high speed motor needs to drive the ultra-high speed motor to rotate, the control system of the ultra-high speed motor needs to output a corresponding high-frequency PWM signal, and the high-frequency PWM signal needs to be a symmetrical high-frequency output signal containing dead zones. Meanwhile, the control algorithm of most ultra-high speed motors needs to control the duty ratio range of the output PWM wave to be 0-100%, for example, a three-level algorithm, so that more severe conditions are provided for the output of the PWM wave.

In the related scheme, the adopted single-chip microcomputer for digital signal processing (namely, DSP), ARM, etc. controls the output of the PWM wave, but the output capability of the PWM wave is weak, such as: the high-frequency PWM wave has slow output speed and long response time, and cannot realize PWM output with dead zones at full duty ratio.

The above is only for the purpose of assisting understanding of the technical aspects of the present invention, and does not represent an admission that the above is prior art.

Disclosure of Invention

The invention aims to provide a control method and device of a motor, the motor, a storage medium and a processor, which are used for solving the problem that the output capability of PWM waves is weak due to the fact that a single chip microcomputer such as a DSP (digital signal processor) and an ARM (advanced RISC machine) is used for controlling the output of the PWM waves, and achieving the effect of improving the output capability of the PWM waves by controlling the output of the PWM waves through an FPGA (field programmable gate array).

The invention provides a control method of a motor, wherein a controller of the motor comprises the following steps: a microprocessor and an FPGA; the control method of the motor comprises the following steps: sending enable signals, duty ratio signals and frequency signals of PWM waves of all power switching tubes in an inverter bridge of the motor to the FPGA by the microprocessor; wherein, the enabling signal of the PWM wave comprises: an off signal of the PWM wave, or an on signal of the PWM wave; under the condition that the microprocessor and the FPGA are electrified and work, or under the condition that the FPGA receives a turn-off signal of the PWM wave, the FPGA turns off the PWM wave; and under the condition that the FPGA receives the enabling signal, the duty ratio signal and the frequency signal of the PWM wave, the FPGA controls the PWM wave according to the received enabling signal, the duty ratio signal and the frequency signal of the PWM wave and outputs the controlled PWM.

In some embodiments, the controlling, by the FPGA, the PWM wave according to the received on signal of the PWM wave, and outputting the controlled PWM, includes: and under the condition that the FPGA receives the conduction signal of the PWM wave, the FPGA starts to output the PWM signal.

In some embodiments, the duty cycle signal comprises: a comparison value of the duty cycle given by the microprocessor; controlling, by the FPGA, the PWM wave according to the received duty ratio signal of the PWM wave, and outputting the controlled PWM, further comprising: if the comparison value of the duty ratio given by the microprocessor is larger than or equal to the set dead zone counting period value, controlling the comparison value of the duty ratio of an upper IGBT tube in the inverter bridge to be the comparison value of the duty ratio given by the microprocessor, and controlling the comparison value of the duty ratio of a lower IGBT tube in the inverter bridge to be the difference value of the comparison value of the duty ratio given by the microprocessor and the dead zone counting period value; if the comparison value of the duty ratio given by the microprocessor is equal to the set counting period value, controlling the comparison value of the duty ratio of an upper tube of the IGBT in the inverter bridge to be the sum of the counting period value and the set value, and controlling the comparison value of the duty ratio of a lower tube of the IGBT in the inverter bridge to be the sum of the counting period value and the set value; if the comparison value of the duty ratio given by the microprocessor is increased to 100% of the set duty ratio and the comparison value of the duty ratio given by the microprocessor is smaller than the set dead zone counting period value, controlling the comparison value of the duty ratio of the IGBT lower tube in the inverter bridge to be updated to 0 when the next new counting period starts, and controlling the IGBT upper tube in the inverter bridge to be updated to 0 after delaying for one PWM period; and if the comparison value of the duty ratio given by the microprocessor begins to decline from 100% of the set duty ratio and the comparison value of the duty ratio given by the microprocessor is switched from being smaller than the set dead zone counting period value to being not smaller than the set dead zone counting period value, controlling the comparison value of the duty ratio of an upper tube of the IGBT in the inverter bridge to be updated to the comparison value of the duty ratio given by the microprocessor when the next new counting period begins, controlling the lower tube of the IGBT in the inverter bridge to be delayed for one PWM period and then updating the comparison value of the duty ratio, and controlling the difference value of the comparison value of the duty ratio given by the microprocessor and the dead zone counting period value.

In some embodiments, the frequency signal comprises: setting a PWM frequency; the FPGA controls the PWM wave according to the received frequency signal of the PWM wave and outputs the controlled PWM, and the method further comprises the following steps: under the condition that the FPGA main frequency is greater than the given PWM frequency, determining that a set counting period value is equal to half of the ratio of the FPGA main frequency to the given PWM frequency; the set counting period value is the maximum value of the counting period of the increase and decrease of the counting value of the time base; under the condition that a comparison value of a duty ratio given by the microprocessor is less than or equal to the time base count value, controlling PWM waves on an IGBT (insulated gate bipolar translator) in the inverter bridge to output a low level, otherwise, outputting a high level; and controlling the PWM wave output of the lower tube of the IGBT in the inverter bridge to be opposite to the PWM wave output of the upper tube of the IGBT in the inverter bridge.

In some embodiments, outputting, by the FPGA, the controlled PWM includes: and the FPGA symmetrically outputs the controlled PWM by adopting an up-down counting mode.

In accordance with the above method, in another aspect of the present invention, there is provided a control apparatus for a motor, comprising: a microprocessor and an FPGA; the control device of the motor comprises: a communication unit configured to transmit, by the microprocessor, to the FPGA, enable signals, duty ratio signals, and frequency signals of PWM waves of all power switching tubes in an inverter bridge of the motor; wherein, the enabling signal of the PWM wave comprises: an off signal of the PWM wave, or an on signal of the PWM wave; the control unit is configured to switch off the PWM wave by the FPGA under the condition that the microprocessor and the FPGA are electrified and work or the FPGA receives a switch-off signal of the PWM wave; the control unit is further configured to, when the FPGA receives the enable signal, the duty ratio signal, and the frequency signal of the PWM wave, control, by the FPGA, the PWM wave according to the received enable signal, the duty ratio signal, and the frequency signal of the PWM wave, and output the PWM after the control.

In some embodiments, the controlling unit, which is configured to control the PWM wave according to the received on signal of the PWM wave by the FPGA and output the controlled PWM, includes: and under the condition that the FPGA receives the conduction signal of the PWM wave, the FPGA starts to output the PWM signal.

In some embodiments, the duty cycle signal comprises: a comparison value of the duty cycle given by the microprocessor; the control unit is used for controlling the PWM wave by the FPGA according to the received duty ratio signal of the PWM wave and outputting the controlled PWM, and the control unit further comprises: if the comparison value of the duty ratio given by the microprocessor is larger than or equal to the set dead zone counting period value, controlling the comparison value of the duty ratio of an upper IGBT tube in the inverter bridge to be the comparison value of the duty ratio given by the microprocessor, and controlling the comparison value of the duty ratio of a lower IGBT tube in the inverter bridge to be the difference value of the comparison value of the duty ratio given by the microprocessor and the dead zone counting period value; if the comparison value of the duty ratio given by the microprocessor is equal to the set counting period value, controlling the comparison value of the duty ratio of an upper tube of the IGBT in the inverter bridge to be the sum of the counting period value and the set value, and controlling the comparison value of the duty ratio of a lower tube of the IGBT in the inverter bridge to be the sum of the counting period value and the set value; if the comparison value of the duty ratio given by the microprocessor is increased to 100% of the set duty ratio and the comparison value of the duty ratio given by the microprocessor is smaller than the set dead zone counting period value, controlling the comparison value of the duty ratio of the IGBT lower tube in the inverter bridge to be updated to 0 when the next new counting period starts, and controlling the IGBT upper tube in the inverter bridge to be updated to 0 after delaying for one PWM period; and if the comparison value of the duty ratio given by the microprocessor begins to decline from 100% of the set duty ratio and the comparison value of the duty ratio given by the microprocessor is switched from being smaller than the set dead zone counting period value to being not smaller than the set dead zone counting period value, controlling the comparison value of the duty ratio of an upper tube of the IGBT in the inverter bridge to be updated to the comparison value of the duty ratio given by the microprocessor when the next new counting period begins, controlling the lower tube of the IGBT in the inverter bridge to be delayed for one PWM period and then updating the comparison value of the duty ratio, and controlling the difference value of the comparison value of the duty ratio given by the microprocessor and the dead zone counting period value.

In some embodiments, the frequency signal comprises: setting a PWM frequency; the control unit is controlled by the FPGA according to the received frequency signal of the PWM wave, and outputs the controlled PWM, and further includes: under the condition that the FPGA main frequency is greater than the given PWM frequency, determining that a set counting period value is equal to half of the ratio of the FPGA main frequency to the given PWM frequency; the set counting period value is the maximum value of the counting period of the increase and decrease of the counting value of the time base; under the condition that a comparison value of a duty ratio given by the microprocessor is less than or equal to the time base count value, controlling PWM waves on an IGBT (insulated gate bipolar translator) in the inverter bridge to output a low level, otherwise, outputting a high level; and controlling the PWM wave output of the lower tube of the IGBT in the inverter bridge to be opposite to the PWM wave output of the upper tube of the IGBT in the inverter bridge.

In some embodiments, the controlling unit, which outputs the controlled PWM by the FPGA, includes: and the FPGA symmetrically outputs the controlled PWM by adopting an up-down counting mode.

In accordance with another aspect of the present invention, there is provided a motor including: the control device of the motor is described above.

In accordance with the above method, a further aspect of the present invention provides a storage medium including a stored program, wherein when the program is executed, an apparatus in which the storage medium is located is controlled to execute the above control method of the motor.

In accordance with the above method, a further aspect of the present invention provides a processor for executing a program, wherein the program executes the above control method of the motor.

Therefore, according to the scheme of the invention, the microprocessor (such as a DSP or an ARM) and the FPGA are combined, the microprocessor sends the enabling signal (such as an on signal or an off signal), the given duty ratio and the frequency signal of the PWM wave, the FPGA outputs the corresponding PWM wave under the condition of receiving the enabling signal, the given duty ratio and the frequency signal sent by the microprocessor, and the output capacity of the PWM wave can be improved by adopting the FPGA to control the output of the PWM wave.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Drawings

Fig. 1 is a schematic flow chart of an embodiment of a control method of a motor according to the present invention;

fig. 2 is a schematic structural diagram of an embodiment of a control device of a motor according to the present invention;

fig. 3 is a timing chart when the comparison value of the duty ratio is not less than the dead zone period;

FIG. 4 is a timing diagram when the comparison value of the duty ratio is equal to the count period;

FIG. 5 is a timing diagram of the duty cycle increasing to 100%;

FIG. 6 is a timing diagram of the duty cycle as it decreases from 100%;

fig. 7 is a schematic flowchart of an embodiment of a method for controlling and outputting a multi-path symmetrical variable-frequency PWM wave based on an FPGA according to the present invention.

The reference numbers in the embodiments of the present invention are as follows, in combination with the accompanying drawings:

102-a communication unit; 104-control unit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

According to an embodiment of the present invention, a method for controlling a motor is provided, as shown in fig. 1, which is a schematic flow chart of an embodiment of the method of the present invention. A controller for the motor, comprising: a microprocessor and an FPGA. The microprocessor, comprising: DSP or ARM. The control method of the motor comprises the following steps: step S110 to step S130.

In step S110, the microprocessor sends, to the FPGA, enable signals, duty ratio signals, and frequency signals of PWM waves of all power switching tubes in an inverter bridge of the motor. Wherein, the enabling signal of the PWM wave comprises: an off signal of the PWM wave, or an on signal of the PWM wave. The enable signal, the duty ratio signal and the frequency signal of the PWM wave of the microprocessor are sent to the FPGA together. The enable signal is a flag bit: 1 represents on and 0 represents off.

In step S120, the FPGA turns off the PWM wave when the microprocessor and the FPGA are powered on and operate, or when the FPGA receives a turn-off signal of the PWM wave. And when the FPGA is initialized at power-on or receives a PWM wave signal for turning off the microprocessor, setting all PWM wave ports to be at low level to prevent false conduction.

In step S130, when the FPGA receives the enable signal, the duty signal, and the frequency signal of the PWM wave, the FPGA controls the PWM wave according to the received enable signal, the duty signal, and the frequency signal of the PWM wave, and outputs the controlled PWM. And when the FPGA receives the enable PWM wave signal of the microprocessor, the FPGA controls the multi-channel port to output corresponding PWM waves according to the PWM instruction signal of the microprocessor.

In particular, in an ultra-high speed motor, the FPGA is generally responsible for executing a part having a fast response speed such as an operation current loop, generation of PWM waves, or only generation of PWM waves. The FPGA sends out the control and output method of PWM wave, the current loop is carried out by the microprocessor (such as DSP or ARM), after FPGA receives enable signal or turn-off signal, duty cycle and frequency signal of PWM wave of the microprocessor, begin to control and output the corresponding PWM wave. Therefore, based on the characteristics of FPGA parallel execution logic, a software implementation scheme is designed, the mechanism of FPGA parallel execution is used for realizing real-time symmetrical output of variable high-frequency PWM, and the problems of PWM wave output and low response speed are solved; the frequency is variable, the requirement of actually using a time-varying carrier is met, and the loss of a switching device is reduced; based on the characteristic of high master frequency of the FPGA, the problem of high-frequency output of PWM waves is solved; the FPGA is adopted to output the PWM waves with high frequency, full duty ratio and quick response, so that the problem that the algorithm is easy to be out of order when the frequency conversion is carried out due to the low response speed of the PWM waves of the DSP or the ARM and the like is solved; by adopting a unique time sequence control scheme, the problems of dead zones and full duty ratio when PWM waves are symmetrically output are solved.

In some embodiments, the controlling, by the FPGA, the PWM wave according to the received on signal of the PWM wave in step S130, and outputting the controlled PWM includes: and under the condition that the FPGA receives the conduction signal of the PWM wave, the FPGA starts to output the PWM signal.

Specifically, in the enable PWM signal, the enable signal refers to a start signal, that is, after the microprocessor sends out the enable PWM wave signal, the FPGA starts sending out the PWM wave, and if the enable signal is not sent out by the microprocessor, the FPGA does not send out the PWM wave, and the default is the low level.

In some embodiments, the duty cycle signal comprises: a comparison value of the duty cycle given by the microprocessor (e.g., a comparison value of the duty cycle cmpa calculated by the microprocessor).

In step S130, the FPGA controls the PWM wave according to the received duty ratio signal of the PWM wave, and outputs the controlled PWM, which further includes any one of the following duty ratio control situations:

first duty cycle control scenario: if the comparison value of the duty ratio given by the microprocessor is larger than or equal to a set DEAD zone counting period value (such as a DEAD zone counting period value DEAD _ CLOCK), controlling the comparison value of the duty ratio of an IGBT upper tube in the inverter bridge (such as the comparison value cmpa _ u1 of the duty ratio of the IGBT upper tube in the symmetrical PWM output) to be the comparison value of the duty ratio given by the microprocessor, and controlling the comparison value of the duty ratio of an IGBT lower tube in the inverter bridge (such as the comparison value cmpa _ u3 of the duty ratio of the IGBT lower tube in the symmetrical PWM output) to be the difference value of the comparison value of the duty ratio given by the microprocessor and the DEAD zone counting period value.

Specifically, in the case where the comparison value of the duty ratio calculated by the microprocessor is not less than the dead band period value, that is: when the comparison value cmpa > of the duty ratio calculated by the microprocessor is equal to the DEAD zone counting period value DEAD _ CLOCK, the relationship among the comparison value cmpa of the duty ratio calculated by the microprocessor, the comparison value cmpa _ u1 of the duty ratio of the upper IGBT tube in the symmetrical PWM output and the comparison value cmpa _ u3 of the duty ratio of the lower IGBT tube in the symmetrical PWM output meets the table 1, and before and after the PWM level of the upper IGBT tube changes, the upper and lower IGBT tubes cannot be directly connected due to the existence of the rising edge DEAD zone and the falling edge DEAD zone. Through the dead zone control strategy in the scheme of the invention, the problem of simultaneous conduction of the upper and lower tubes of the Insulated Gate Bipolar Transistor (IGBT) when the PWM wave is conducted or shut off is solved, and the problem that the upper and lower tubes of the IGBT can not be directly connected when the PWM wave can be sent or shut off at any time is realized.

Second duty cycle control scenario: if the comparison value of the duty ratio given by the microprocessor is equal to a set counting PERIOD value (such as the maximum value PERIOD of the counting PERIOD), controlling the comparison value of the duty ratio of the IGBT upper tube in the inverter bridge (such as the comparison value cmpa _ u1 of the duty ratio of the IGBT upper tube in the symmetrical PWM output) to be the sum value of the counting PERIOD value and a set value (such as the maximum value PERIOD +2 of the counting PERIOD), and controlling the comparison value of the duty ratio of the IGBT lower tube in the inverter bridge (such as the comparison value cmpa _ u3 of the duty ratio of the IGBT lower tube in the symmetrical PWM output) to be the sum value of the counting PERIOD value and the set value (such as the maximum value PERIOD +2 of the counting PERIOD).

Specifically, in the case where the comparison value of the duty ratio (e.g., the comparison value cmpa of the duty ratio calculated by the microprocessor) is equal to the count PERIOD value (e.g., the up-down count PERIOD maximum value PERIOD), the second setting strategy is executed. That is, the comparison value at the duty cycle is equal to the count period value, i.e.: when cmpa is the maximum up/down count cycle value PERIOD, the relationship among the comparison value cmpa of the duty ratio calculated by the microprocessor, the comparison value cmpa _ u1 of the duty ratio of the upper IGBT tube in the symmetrical PWM output, and the comparison value cmpa _ u3 of the duty ratio of the lower IGBT tube in the symmetrical PWM output satisfies table 1, and the duty ratio at this time is 0%. When the duty ratio is reduced from more than 0% to 0%, special treatment is not needed when the duty ratio is increased to 100% or reduced from 100%, because the duty ratio is more than 0% before the duty ratio is updated, the upper tube PWM of the IGBT is at a low level, the lower tube PWM of the IGBT is at a high level, and the duty ratio is updated to be 0%, the problem that the upper tube and the lower tube of the IGBT are directly connected is solved.

The third duty cycle control scenario: if the comparison value of the duty ratio given by the microprocessor rises to 100% of the set duty ratio, and the comparison value of the duty ratio given by the microprocessor is smaller than the set DEAD zone counting period value (for example, DEAD zone counting period value DEAD _ CLOCK), the comparison value of the duty ratio of the IGBT lower tube in the inverter bridge is controlled to be updated to 0 at the beginning of the next new counting period, and the comparison value of the updated duty ratio of the IGBT upper tube in the inverter bridge is controlled to be 0 after being delayed for one PWM period than the IGBT lower tube in the inverter bridge, that is, the comparison value of the duty ratio of the IGBT lower tube in the inverter bridge is updated to 0 at the beginning of the next new counting period, and the comparison value of the updated duty ratio of the IGBT upper tube is 0 after being delayed for one PWM period. Wherein, the comparison value of the duty ratio of the IGBT on the IGBT in the inverter bridge, for example, the comparison value cmpa _ u1 of the duty ratio of the IGBT on the symmetrical PWM output; and comparing the duty ratio of the lower IGBT tube in the inverter bridge, such as the duty ratio cmpa _ u3 of the lower IGBT tube in the symmetrical PWM output.

Specifically, in the case where the comparison value of the duty ratio (e.g., the comparison value cmpa of the duty ratio calculated by the microprocessor) rises to 100%, the third setting strategy is executed: the method comprises the steps that an FPGA receives a comparison value cmpa of a given duty ratio of a microprocessor (namely, a comparison value cmpa of the duty ratio calculated by the microprocessor) at any moment, when the comparison value of the given duty ratio of the microprocessor is smaller than a DEAD zone period value, namely, when the comparison value cmpa of the given duty ratio of the microprocessor is smaller than a DEAD zone counting period value DEAD _ CLOCK, the comparison value of the duty ratio of an IGBT lower tube is immediately updated in the next counting period, namely, the comparison value cmpa _ u3 of the duty ratio of the IGBT lower tube in symmetrical PWM output is 0, and the IGBT lower tube immediately and constantly outputs a low level; the IGBT upper tube keeps the comparison value cmpa _ u1 of the original duty ratio (namely the comparison value cmpa _ u1 of the duty ratio of the IGBT upper tube in the symmetrical PWM output) unchanged, the level overturning condition is consistent with the previous period, the comparison value cmpa _ u1 of the duty ratio of the IGBT upper tube in the symmetrical PWM output is updated to be 0 after the whole counting period, the IGBT upper tube starts to output high level, and the duty ratio reaches 100% at the moment.

A fourth duty cycle control scenario: if the comparison value of the duty ratio given by the microprocessor starts to decline from 100% of the set duty ratio and the comparison value of the duty ratio given by the microprocessor switches from being smaller than a set DEAD zone counting period value (such as a DEAD zone counting period value DEAD _ CLOCK) to being not smaller than the set DEAD zone counting period value (such as a DEAD zone counting period value DEAD _ CLOCK), the comparison value of the duty ratio of the upper IGBT tube in the inverter bridge is controlled to be updated to the comparison value of the duty ratio given by the microprocessor when the next new counting period starts, the lower IGBT tube in the inverter bridge is controlled to be delayed for one PWM period and then the comparison value of the duty ratio is updated, the comparison value of the duty ratio given by the microprocessor is the difference value of the DEAD zone counting period value, namely, the comparison value of the duty ratio of the upper IGBT tube in the inverter bridge is controlled to be immediately updated to the comparison value of the duty ratio given by the microprocessor, and delaying the lower tube of the IGBT by one PWM period compared with the upper tube, and then updating the comparison value of the duty ratio, wherein the comparison value of the duty ratio is given to the microprocessor and is the difference value of the dead zone counting period value. Wherein, the comparison value of the duty ratio of the IGBT on the IGBT in the inverter bridge, for example, the comparison value cmpa _ u1 of the duty ratio of the IGBT on the symmetrical PWM output; and comparing the duty ratio of the lower IGBT tube in the inverter bridge, such as the duty ratio cmpa _ u3 of the lower IGBT tube in the symmetrical PWM output.

Specifically, in the case where the comparison value of the duty ratio (e.g., the comparison value cmpa of the duty ratio calculated by the microprocessor) is decreased from 100%, the fourth setting strategy is executed. That is, the FPGA receives the comparison value cmpa of the given duty ratio of the microprocessor (i.e., the comparison value cmpa of the duty ratio calculated by the microprocessor) at any time, and when the comparison value of the given duty ratio of the microprocessor is switched from a value smaller than the DEAD zone period (i.e., DEAD zone count period value DEAD _ CLOCK) to a value not smaller than the DEAD zone period (i.e., DEAD zone count period value DEAD _ CLOCK), the comparison value of the duty ratio of the IGBT upper tube in the IGBT upper tube is immediately updated in the next count period, that is, the comparison value cmpa _ u1 of the duty ratio of the IGBT upper tube in the symmetric PWM output is equal to the comparison value cmpa of the given duty ratio of the microprocessor, and the IGBT upper tube is immediately changed from the high level to the low level to start the normal output level switching; the IGBT lower tube keeps the comparison value cmpa _ u3 of the original duty ratio to be 0 (namely the comparison value cmpa _ u3 of the duty ratio of the IGBT lower tube in the symmetrical PWM output to be 0), keeps the low level and the previous period consistent, after a whole counting period, the comparison value cmpa _ u3 of the duty ratio of the IGBT lower tube in the symmetrical PWM output is updated to the comparison value cmpa-DEAD _ CLOCK (DEAD zone counting period value) of the given duty ratio of the microprocessor, the IGBT lower tube starts to output the high level, and the duty ratio is reduced from 100% at the moment.

By carrying out special time sequence control on the IGBT when the upper and lower tubes output when the duty ratio reaches 100%, the symmetrical output of any PWM wave with 0-100% duty ratio and dead zone is realized, the output of narrow pulse in the process of full duty ratio change is avoided, the continuous change of the PWM wave with 0-100% duty ratio is realized, and the dead zone strategy is well optimized. And, by avoiding the occurrence of narrow pulses in the process of realizing full duty cycle variation, the dead time is changed along with the frequency, reducing the loss of the switching device.

Therefore, multiple paths of PWM waves output based on the FPGA are all output according to the control strategy, each path of PWM wave command signal is controlled by the microprocessor, and normal output of the PWM waves with full duty ratio is realized on the premise of meeting dead zones. Therefore, multi-path symmetrical output of variable high-frequency PWM waves is realized, and meanwhile, the dead time is increased along with the reduction of PWM frequency, so that the loss of a power switch device is reduced; the symmetrical output of PWM waves with any duty ratio of 0-100% is realized, and meanwhile, the generation of narrow pulses is prevented by optimizing the duty ratio of 100%.

In some embodiments, the frequency signal comprises: a given PWM frequency (e.g., a given PWM frequency).

In step S130, the FPGA controls the PWM wave according to the received frequency signal of the PWM wave, and outputs the controlled PWM, and the method further includes: and under the condition that the FPGA main frequency is greater than the given PWM frequency, determining that the set counting period value is equal to half of the ratio of the FPGA main frequency to the given PWM frequency. The set counting period value is the maximum value of the counting period of the increment and decrement of the counting value of the time base.

Under the condition that a comparison value of a given duty ratio (such as a comparison value cmpa of the duty ratio calculated by the microprocessor) of the microprocessor is smaller than or equal to a time base count value (such as a time base count value tb _ count), controlling a PWM wave on an IGBT (insulated gate bipolar translator) in the inverter bridge to output a low level, otherwise, outputting a high level; and controlling the PWM wave output of the lower tube of the IGBT in the inverter bridge to be opposite to the PWM wave output of the upper tube of the IGBT in the inverter bridge.

Specifically, the duty ratio is given by the microprocessor, but in fact, the microprocessor transmits the comparison value cmpa of the duty ratio calculated by the microprocessor to the FPGA, and the FPGA compares the comparison value cmpa of the duty ratio calculated by the microprocessor with the time base count value tb _ count, thereby determining the output high and low level time. That is, in the up-down counting, for the IGBT upper tube, when the comparison value cmpa of the duty ratio calculated by the microprocessor is less than the time base count value tb _ count, the IGBT upper tube PWM output is low, otherwise, the IGBT upper tube PWM output is high, and the IGBT upper tube are symmetrical, so the comparison result is inverted. Since the comparison value cmpa of the duty ratio calculated by the microprocessor at any time is determined as a result of comparing the time base count value tb _ count, the high and low levels of the upper and lower tubes of the IGBT at any time are determined. Implementation of FPGA for a given PWM frequency FREQUENCE: the order of magnitude (e.g., megalevel) of the FPGA master frequency SYSTEM _ CLOCK is usually much larger than a given PWM frequency, so that each rising edge of the FPGA chip master frequency is counted, and after counting several times, a PWM cycle is obtained. The PWM period is 1/PWM frequency, and the count value required by the FPGA when the PWM frequency is given is realized: the FPGA main frequency/given PWM frequency is FPGA main frequency SYSTEM _ CLOCK/given PWM frequency FREQUENCE. Because the up-down counting mode is adopted, the maximum up-down counting PERIOD value PERIOD of the time base counting value tb _ count is equal to: FPGA main frequency SYSTEM _ CLOCK/given PWM frequency FREQUENCE/2.

In some embodiments, the outputting the controlled PWM by the FPGA in step S130 includes: and the FPGA symmetrically outputs the controlled PWM by adopting an up-down counting mode.

Specifically, the FPGA sends PWM waves in three ways, namely count up, count down, and count up and count down. The up-down counting mode is adopted here to realize the symmetrical output of the PWM wave. The up-down count is a time base count value tb _ count, which is increased from 0 to a maximum up-down count PERIOD value PERIOD, and then decreased from the maximum up-down count PERIOD value PERIOD to 0, and the process is repeated.

Through a large number of tests, the technical scheme of the embodiment is adopted, the microprocessor is combined with the microprocessor (such as a DSP or an ARM) and the FPGA to send the enabling signal (such as an on signal or an off signal), the given duty ratio and the frequency signal of the PWM wave, the FPGA outputs the corresponding PWM wave under the condition that the FPGA receives the enabling signal, the given duty ratio and the frequency signal sent by the microprocessor, and the output capacity of the PWM wave can be improved by adopting the FPGA to control the output of the PWM wave.

According to an embodiment of the present invention, there is also provided a control apparatus of a motor corresponding to the control method of the motor. Referring to fig. 2, a schematic diagram of an embodiment of the apparatus of the present invention is shown. A controller for the motor, comprising: a microprocessor and an FPGA. The microprocessor, comprising: DSP or ARM. The control device of the motor comprises: a communication unit 102 and a control unit 104.

The communication unit 102 is configured to send, by the microprocessor, to the FPGA, enable signals, duty ratio signals, and frequency signals of PWM waves of all power switching tubes in an inverter bridge of the motor. Wherein, the enabling signal of the PWM wave comprises: an off signal of the PWM wave, or an on signal of the PWM wave. The enable signal, the duty ratio signal and the frequency signal of the PWM wave of the microprocessor are sent to the FPGA together. The enable signal is a flag bit: 1 represents on and 0 represents off. The specific function and processing of the communication unit 102 are referred to in step S110.

A control unit 104 configured to turn off the PWM wave by the FPGA in a case where the microprocessor and the FPGA are powered on to operate or in a case where the FPGA receives a turn-off signal of the PWM wave. And when the FPGA is initialized at power-on or receives a PWM wave signal for turning off the microprocessor, setting all PWM wave ports to be at low level to prevent false conduction. The specific function and processing of the control unit 104 are referred to in step S120.

The control unit 104 is further configured to, when the FPGA receives the enable signal, the duty signal, and the frequency signal of the PWM wave, control the PWM wave according to the received enable signal, the duty signal, and the frequency signal of the PWM wave by the FPGA, and output the PWM after the control. And when the FPGA receives the enable PWM wave signal of the microprocessor, the FPGA controls the multi-channel port to output corresponding PWM waves according to the PWM instruction signal of the microprocessor. The specific function and processing of the control unit 104 are also referred to in step S130.

In particular, in an ultra-high speed motor, the FPGA is generally responsible for executing a part having a fast response speed such as an operation current loop, generation of PWM waves, or only generation of PWM waves. The FPGA sends out the control and output device of PWM wave, the current loop is carried out by the microprocessor (such as DSP or ARM), after FPGA receives enable signal or turn-off signal, duty cycle and frequency signal of PWM wave of the microprocessor, begin to control and output the corresponding PWM wave. Therefore, based on the characteristics of FPGA parallel execution logic, a software implementation scheme is designed, the mechanism of FPGA parallel execution is used for realizing real-time symmetrical output of variable high-frequency PWM, and the problems of PWM wave output and low response speed are solved; the frequency is variable, the requirement of actually using a time-varying carrier is met, and the loss of a switching device is reduced; based on the characteristic of high master frequency of the FPGA, the problem of high-frequency output of PWM waves is solved; the FPGA is adopted to output the PWM waves with high frequency, full duty ratio and quick response, so that the problem that the algorithm is easy to be out of order when the frequency conversion is carried out due to the low response speed of the PWM waves of the DSP or the ARM and the like is solved; by adopting a unique time sequence control scheme, the problems of dead zones and full duty ratio when PWM waves are symmetrically output are solved.

In some embodiments, the controlling unit 104, which is configured to control the PWM wave according to the received on signal of the PWM wave by the FPGA and output the controlled PWM, includes: the control unit 104 is specifically further configured to start outputting the PWM signal by the FPGA when the FPGA receives the on signal of the PWM wave.

The control unit 104 is configured to control the PWM wave and output the controlled PWM according to the received duty ratio signal of the PWM wave by the FPGA, and further includes any one of the following duty ratio control situations:

first duty cycle control scenario: the control unit 104 is specifically configured to control the comparison value of the duty ratio of the IGBT in the inverter bridge (e.g., the comparison value cmpa _ u1 of the duty ratio of the IGBT on the symmetrical PWM output) to be the comparison value of the duty ratio given by the microprocessor, and control the comparison value of the duty ratio of the IGBT off the inverter bridge (e.g., the comparison value cmpa _ u3 of the duty ratio of the IGBT off the symmetrical PWM output) to be the difference value of the comparison value of the duty ratio given by the microprocessor and the DEAD zone count value, if the comparison value of the duty ratio given by the microprocessor is greater than or equal to the set DEAD zone count period value (e.g., DEAD zone count period value DEAD zone count _ CLOCK).

Second duty cycle control scenario: the control unit 104 is further specifically configured to control the comparison value of the duty ratio of the IGBT upper tube in the inverter bridge (e.g., the comparison value cmpa _ u1 of the duty ratio of the IGBT upper tube in the symmetric PWM output) to be a sum value of the count PERIOD value and a set value (e.g., the maximum up/down count PERIOD value PERIOD +2) and control the comparison value of the duty ratio of the IGBT lower tube in the inverter bridge (e.g., the comparison value cmpa _ u3 of the duty ratio of the IGBT lower tube in the symmetric PWM output) to be a sum value of the count PERIOD value and the set value (e.g., the maximum up/down count PERIOD value PERIOD +2) if the comparison value of the duty ratio given by the microprocessor is equal to the set count PERIOD value (e.g., the maximum up/down count.

The third duty cycle control scenario: the control unit 104 is specifically configured to, if the comparison value of the duty ratio given by the microprocessor rises to 100% of the set duty ratio, and the comparison value of the duty ratio given by the microprocessor is smaller than the set DEAD zone counting period value (for example, DEAD zone counting period value DEAD _ CLOCK), control the comparison value of the duty ratio of the IGBT lower tube in the inverter bridge to update to 0 at the beginning of the next new counting period, and control the IGBT upper tube in the inverter bridge to update the comparison value of the duty ratio after delaying for one PWM period again than the IGBT lower tube in the inverter bridge to update to 0, that is, the comparison value of the IGBT lower tube duty ratio in the inverter bridge to update to 0 at the beginning of the next new counting period, and the comparison value of the duty ratio updated after delaying for one PWM period again after the IGBT upper tube. Wherein, the comparison value of the duty ratio of the IGBT on the IGBT in the inverter bridge, for example, the comparison value cmpa _ u1 of the duty ratio of the IGBT on the symmetrical PWM output; and comparing the duty ratio of the lower IGBT tube in the inverter bridge, such as the duty ratio cmpa _ u3 of the lower IGBT tube in the symmetrical PWM output.

A fourth duty cycle control scenario: the control unit 104 is further configured to, if the comparison value of the duty ratio given by the microprocessor starts to decrease from 100% of the set duty ratio and the comparison value of the duty ratio given by the microprocessor switches from being smaller than a set DEAD zone counting period value (e.g., DEAD zone counting period value DEAD _ CLOCK) to being not smaller than a set DEAD zone counting period value (e.g., DEAD zone counting period value DEAD _ CLOCK), control the comparison value of the duty ratio on the IGBT in the inverter bridge to be updated to the comparison value of the duty ratio given by the microprocessor at the beginning of a next new counting period, control the IGBT on tube in the inverter bridge to be updated after delaying the IGBT on tube for one PWM period again, and control the comparison value of the duty ratio given by the microprocessor to be a difference between the comparison value of the duty ratio given by the microprocessor and the DEAD zone counting period value, that is, control the comparison value of the duty ratio on the IGBT on tube in the inverter bridge to be immediately updated to the comparison value of the duty ratio given by the, and delaying the lower tube of the IGBT by one PWM period compared with the upper tube, and then updating the comparison value of the duty ratio, wherein the comparison value of the duty ratio is given to the microprocessor and is the difference value of the dead zone counting period value. Wherein, the comparison value of the duty ratio of the IGBT on the IGBT in the inverter bridge, for example, the comparison value cmpa _ u1 of the duty ratio of the IGBT on the symmetrical PWM output; and comparing the duty ratio of the lower IGBT tube in the inverter bridge, such as the duty ratio cmpa _ u3 of the lower IGBT tube in the symmetrical PWM output.

Therefore, multiple paths of PWM waves output based on the FPGA are all output according to the control strategy, each path of PWM wave command signal is controlled by the microprocessor, and normal output of the PWM waves with full duty ratio is realized on the premise of meeting dead zones. Therefore, multi-path symmetrical output of the variable high-frequency PWM waves is realized, and meanwhile, the dead time is increased along with the reduction of the PWM frequency, so that the loss of the power switching device is reduced. The symmetrical output of PWM waves with any duty ratio of 0-100% is realized, and meanwhile, the generation of narrow pulses is prevented by optimizing the duty ratio of 100%.

The control unit 104, which is configured to control the PWM wave by the FPGA according to the received frequency signal of the PWM wave, and output the controlled PWM, further includes: the control unit 104 is specifically further configured to determine that the set count period value is equal to half of a ratio of the FPGA dominant frequency to the given PWM frequency, in a case that the FPGA dominant frequency is greater than the given PWM frequency. The set counting period value is the maximum value of the counting period of the increment and decrement of the counting value of the time base.

The control unit 104 is specifically further configured to control the PWM wave on the IGBT in the inverter bridge to output a low level if a comparison value of the duty ratio given by the microprocessor (e.g., a comparison value cmpa of the duty ratio calculated by the microprocessor) is less than or equal to the time-based count value (e.g., a time-based count value tb _ count), and otherwise output a high level; and controlling the PWM wave output of the lower tube of the IGBT in the inverter bridge to be opposite to the PWM wave output of the upper tube of the IGBT in the inverter bridge.

In some embodiments, the outputting, by the FPGA, of the controlled PWM by the control unit 104 includes: the control unit 104 is further configured to perform symmetrical output on the controlled PWM by the FPGA in an up-down counting manner.

Since the processes and functions implemented by the apparatus of this embodiment substantially correspond to the embodiments, principles, and examples of the method shown in fig. 1, reference may be made to the related descriptions in the foregoing embodiments for details which are not described in the description of this embodiment, and further description is not given here.

Through a large number of tests, the technical scheme of the invention is adopted, the microprocessor is combined with the microprocessor (such as a DSP or an ARM) and the FPGA to send the enabling signal (such as an on signal or an off signal), the given duty ratio and the frequency signal of the PWM wave, the FPGA outputs the corresponding PWM wave under the condition of receiving the enabling signal, the given duty ratio and the frequency signal sent by the microprocessor, and the FPGA can use the mechanism of parallel execution of the FPGA to realize the real-time symmetrical output of the variable high-frequency PWM and improve the speed of the output and response of the PWM wave.

According to an embodiment of the present invention, there is also provided a motor corresponding to the control device of the motor. The motor may include: the control device of the motor is described above.

The frequency refers to the number of cycles in the PWM wave 1s, that is, f is 1/T, f represents the PWM wave frequency, T represents the PWM wave period high frequency, which means that the number of cycles in 1s is large, generally speaking, in the field of motor control, the PWM wave frequency is higher than 10kHz and belongs to high frequency, and the PWM wave frequency is designed to be up to 30 kHz.

The control system of the ultra-high speed motor (generally, the motor with the rotating speed exceeding 10000 r/min) has a wide range, and specifically comprises a hardware layer, a software layer and a structural layer, wherein the control algorithm of the ultra-high speed motor is the content of the software layer. The control system of the ultra-high speed motor is a control overall scheme, and the control algorithm of the ultra-high speed motor is due to the design of a software layer; the PWM wave is essentially controlled by a software layer and then realized by a hardware layer.

In the relevant scheme, adopt singlechip control PWM ripples output such as DSP, ARM, have some problems, for example: the PWM wave output speed is low, and the response time is long; the high-frequency PWM wave cannot be output under the influence of the main frequency and the serial execution working mechanism of the singlechip; the control algorithm is easy to be out of order in the frequency conversion regulation; a symmetrical full duty cycle PWM output with dead zones cannot be achieved. Wherein, ARM is a 32-bit Reduced Instruction Set (RISC) processor architecture.

A Delay Locked Loop (DLL), or a Phase Locked Loop (PLL) hardware circuit is integrated in the FPGA and used for completing the functions of frequency multiplication, frequency division, duty ratio adjustment, phase shift and the like of high precision and low jitter of a clock; the FPGA is a parallel execution program, and the running speed and the processing speed of the FPGA are far superior to those of common single-chip microcomputers such as a DSP (digital signal processing) and an ARM (32-bit reduced instruction set processor) and the like, so that a user can simultaneously realize the functions of high-frequency (variable frequency), multi-path symmetry, full duty ratio and PWM wave output with dead zones through design.

The FPGA is a hardware language, the execution of the FPGA is parallel execution logic, namely a plurality of code blocks are executed simultaneously, the DSP or the ARM is serial execution logic, and only one code block can be executed at the same time, so the response speed when the FPGA sends the PWM wave is not in the same order of magnitude as the FPGA. The FPGA main frequency is usually higher than that of the DSP or the ARM, so that the FPGA speed is higher, for example, the PWM wave output in the scheme of the invention is realized by counting the main frequency, and the higher the main frequency is, the smaller the time of each period is, the faster the counting is.

In some schemes of the invention, the invention provides a multi-path symmetrical variable-frequency PWM wave control and output method based on FPGA, which solves the problem that the PWM wave output function with dead zones, such as high frequency (variable frequency), multi-path symmetry, full duty ratio and the like, is required to be realized simultaneously during the control of the ultra-high-speed motor, and improves the output capability of the PWM wave.

According to the scheme, a software implementation scheme is designed based on the characteristics of FPGA parallel execution logic, the mechanism of FPGA parallel execution is used for realizing real-time symmetrical output of variable high-frequency PWM, and the problems of PWM wave output and low response speed are solved; the frequency is variable, the requirement of actually using a time-varying carrier is met, and the loss of a switching device is reduced; based on the characteristic of high master frequency of the FPGA, the problem of high-frequency output of PWM waves is solved; the FPGA is adopted to output the PWM waves with high frequency, full duty ratio and quick response, so that the problem that the algorithm is easy to be out of order when the frequency conversion is carried out due to the low response speed of the PWM waves of the DSP or the ARM and the like is solved; by adopting a unique time sequence control scheme, the problems of dead zones and full duty ratio when PWM waves are symmetrically output are solved.

In some embodiments, in the field of ultra-high speed motor control, FPGAs are generally responsible for executing parts with fast response speed, such as running current loops, sending PWM waves, or only sending PWM waves. In the scheme of the invention, in the control and output method for the FPGA to send the PWM wave, a current loop is executed by a microprocessor (such as a DSP or an ARM), and the FPGA starts to control and output the corresponding PWM wave after receiving an enable signal or a turn-off signal, a duty ratio and a frequency signal of the PWM wave of the microprocessor.

When the FPGA is initialized at power-on or receives a PWM wave signal for turning off the microprocessor, setting all PWM wave ports to be low level to prevent false conduction; and when the FPGA receives the enable PWM wave signal of the microprocessor, the FPGA controls the multi-channel port to output corresponding PWM waves according to the PWM instruction signal of the microprocessor. In the enabling PWM signals, the enabling signals refer to starting signals, namely after the microprocessor sends out enabling PWM wave signals, the FPGA starts sending out PWM waves, the FPGA does not send out waves without the enabling signals sent out by the microprocessor, and the default is low level.

The PWM wave generating mode of the FPGA comprises an up-counting mode, a down-counting mode and an up-down-counting mode. The up-down count is a time base count value tb _ count, which is increased from 0 to a maximum up-down count PERIOD value PERIOD, and then decreased from the maximum up-down count PERIOD value PERIOD to 0, and the process is repeated. The time base count value is a count value of a main frequency period of the FPGA chip, such as the FPGA main frequency displayed at the top in fig. 3, and the time base count value is a count value of the main frequency signal period. For example: the FPGA chip main frequency 50M, the period is 1/50M-20 ns, and the time base count value is used for realizing the timing function for the period count.

The duty ratio is given by the microprocessor, in fact, the microprocessor transmits a comparison value cmpa of the duty ratio calculated by the microprocessor to the FPGA, and the FPGA compares the comparison value cmpa of the duty ratio calculated by the microprocessor with the time base count value tb _ count, so that the output high and low level time is determined.

Wherein, the time base count value tb _ count is a value which changes in a cyclic reciprocating manner and ranges from 0 to PERIOD 0; DEAD _ CLOCK is a numerical value representing the count value of tb _ count at the time of realizing the DEAD time; for example, setting the DEAD time to be 1ms, and increasing tb _ count by 1 represents that the time is increased by 0.1ms, so that the DEAD _ CLOCK is 10 at this time; cmpa is a duty ratio comparison value sent by the microprocessor to the FPGA, and when the duty ratio comparison value relates to high and low levels, cmpa is compared with tb _ count, and when the duty ratio comparison value relates to a DEAD zone, cmpa is mainly compared with DEAD _ CLOCK.

Specifically, in the up-down counting, for the IGBT upper tube, when the comparison value cmpa of the duty ratio calculated by the microprocessor is less than the time base count value tb _ count, the IGBT upper tube PWM output is low, otherwise, a high level is output, and the lower tube and the upper tube are symmetrical, so the comparison result is inverted, see fig. 3. Since the comparison value cmpa of the duty ratio calculated by the microprocessor at any time is determined as a result of comparing the time base count value tb _ count, the high and low levels of the upper and lower tubes of the IGBT at any time are determined.

Implementation of FPGA for a given PWM frequency FREQUENCE: the order of magnitude (e.g., megalevel) of the FPGA master frequency SYSTEM _ CLOCK is usually much larger than a given PWM frequency, so that each rising edge of the FPGA chip master frequency is counted, and after counting several times, a PWM cycle is obtained. The PWM period is 1/PWM frequency, and the count value required by the FPGA when the PWM frequency is given is realized: the FPGA main frequency/given PWM frequency is FPGA main frequency SYSTEM _ CLOCK/given PWM frequency FREQUENCE. Because the up-down counting mode is adopted, the maximum up-down counting PERIOD value PERIOD of the time base counting value tb _ count is equal to:

FPGA main frequency SYSTEM _ CLOCK/given PWM frequency FREQUENCE/2.

Implementation of dynamic dead time: in order to prevent the occurrence of the direct connection between the upper and lower tubes of the power switching device (such as an IGBT), a dead zone is usually added when the switching state of the upper and lower tubes of the IGBT changes (i.e., the high and low levels change), and the purpose of adding the dead zone is to perform a time-delayed switching process on the rising edge and the falling edge. Usually, after the PWM wave is output from a pin of an FPGA chip, the minimum time of the PWM wave finally reaching a power switch device (such as an IGBT) through a hardware PWM wave driving circuit is about 1us, so that the minimum 1us of dead time is reserved when the given PWM wave has the highest frequency; the dead zone cannot be large, and the larger the dead zone is, the larger the distortion of the output current waveform is. The dead time is taken to be 2us when the given PWM wave frequency is small. In the scheme of the invention, when the frequency of the PWM wave is set to be 10kHz, the dead zone is 2us, when the frequency is at most 30kHz, the dead zone is 1us, and the dead zone time is 2.5-0.05 times of the PWM frequency calculated by the frequency of the other PWM waves according to the linear function formula. The DEAD time is also realized by counting each rising edge of the FPGA main frequency, and the required counting period value DEAD _ CLOCK of the DEAD time is the DEAD time of the FPGA main frequency. The dead time increases as the PWM frequency decreases, and this variation slows the switching action of the IGBT reducing the losses of the switching devices.

Wherein, add the dead band when the upper and lower tube switch state of IGBT changes (the change of high-low level), include: referring to the example shown in fig. 3, the rising edge dead zone refers to: before the upper IGBT tube is conducted, the lower IGBT tube is closed in advance by dead time; the falling edge dead zone refers to: before the IGBT lower tube is conducted, the IGBT upper tube is closed in advance by dead time, and the dead time is realized by control logic in the scheme of the invention.

In other words, because the PWM waves are vertically symmetrical, but the IGBT lower tube cannot be immediately turned off when the IGBT upper tube is turned on, because the IGBT upper tube and IGBT lower tube are directly connected at a certain moment in actual use, and the IGBT upper tube and IGBT lower tube direct connection is extremely easy to damage the IGBT and cannot play a role in protection, the dead zone is used for preventing conduction, and the addition of the dead zone is that the FPGA performs the PWM turn-off operation in advance when the IGBT upper tube or the IGBT lower tube is turned on.

Fig. 7 is a schematic flowchart of an embodiment of a method for controlling and outputting a multi-path symmetrical variable-frequency PWM wave based on an FPGA according to the present invention. As shown in fig. 7, the method for controlling and outputting the multi-path symmetrical variable frequency PWM wave based on the FPGA according to the present invention includes:

step 1, a microprocessor (such as a DSP or an ARM processor) and an FPGA are electrified to work.

And 2, turning off all PWM waves by default by the FPGA.

And 3, sending instructions of PWM wave enabling, duty ratio and frequency by a microprocessor (such as a DSP or an ARM processor).

And 4, receiving the content of the instruction by the FPGA, and outputting a PWM wave, which refers to steps 41 to 44.

In step 41, in case that the comparison value of the duty ratio (e.g., the comparison value cmpa of the duty ratio calculated by the microprocessor) is not less than the DEAD-time period value (e.g., the DEAD-time count period value DEAD _ CLOCK), the first set strategy, i.e., the strategy shown in fig. 3, is executed.

Fig. 3 is a timing chart when the comparison value of the duty ratio is not less than the dead zone period. As can be seen from fig. 3, when the comparison value of the duty ratio calculated by the microprocessor is not less than the dead zone period value, that is:

when the comparison value cmpa > of the duty ratio calculated by the microprocessor is equal to the DEAD zone counting period value DEAD _ CLOCK, the relationship among the comparison value cmpa of the duty ratio calculated by the microprocessor, the comparison value cmpa _ u1 of the duty ratio of the upper IGBT tube in the symmetrical PWM output and the comparison value cmpa _ u3 of the duty ratio of the lower IGBT tube in the symmetrical PWM output meets the table 1, and before and after the PWM level of the upper IGBT tube changes, the upper and lower IGBT tubes cannot be directly connected due to the existence of the rising edge DEAD zone and the falling edge DEAD zone. In fig. 3, the time base count value tb _ count continuously changes by circularly counting the rising edge of the main frequency of the FPGA.

The comparison value cmpa of the duty ratio calculated by the microprocessor may be obtained by modulation calculation of a motor control algorithm of the microprocessor.

Table 1: method for calculating comparison value of duty ratio of upper pipe and lower pipe

	Upper tube cmpa _ u1 value	Lower tube cmpa _ u3 value
			cmpa>＝DEAD_CLOCK	cmpa	cmpa-DEAD_CLOCK
cmpa＝PERIOD	PERIOD+2	PERIOD+2
			cmpa<DEAD_CLOCK	0	0

According to the dead zone control strategy in the scheme, the problem that high-power switching devices such as upper and lower tubes of an Insulated Gate Bipolar Transistor (IGBT) are simultaneously conducted when the PWM waves are conducted or turned off is solved, and the problem that the upper and lower tubes of the IGBT are directly connected when the PWM waves can be sent or turned off at any time is solved.

In step 42, a second setting strategy, i.e. the strategy shown in fig. 4, is implemented if the comparison value of the duty cycle (e.g. the comparison value cmpa of the duty cycle calculated by the microprocessor) is equal to the value of the counting cycle (e.g. the maximum value of the counting cycle PERIOD is increased or decreased).

Fig. 4 is a timing chart when the comparison value of the duty ratio is equal to the count period. As can be seen from fig. 4, the comparison value at the duty cycle is equal to the count period value, i.e.: when cmpa is the maximum up/down count cycle value PERIOD, the relationship among the comparison value cmpa of the duty ratio calculated by the microprocessor, the comparison value cmpa _ u1 of the duty ratio of the upper IGBT tube in the symmetrical PWM output, and the comparison value cmpa _ u3 of the duty ratio of the lower IGBT tube in the symmetrical PWM output satisfies table 1, and the duty ratio at this time is 0%. When the duty ratio is reduced from more than 0% to 0%, special treatment is not needed when the duty ratio is increased to 100% or reduced from 100%, because the duty ratio is more than 0% before the duty ratio is updated, the upper tube PWM of the IGBT is at a low level, the lower tube PWM of the IGBT is at a high level, and the duty ratio is updated to be 0%, the problem that the upper tube and the lower tube of the IGBT are directly connected is solved.

In step 43, when the comparison value of the duty ratio (e.g., the comparison value cmpa of the duty ratio calculated by the microprocessor) increases to 100%, the third setting strategy, i.e., the strategy shown in fig. 5, is executed.

Fig. 5 is a timing chart when the duty ratio is increased to 100%. As can be seen from fig. 5, the FPGA receives the comparison value cmpa of the given duty cycle of the microprocessor (i.e. the comparison value cmpa of the duty cycle calculated by the microprocessor) at any time, and the comparison value of the given duty cycle of the microprocessor is smaller than the dead-zone period value, that is:

when the comparison value cmpa of the given duty ratio of the microprocessor is smaller than the DEAD zone counting period value DEAD _ CLOCK, the comparison value of the duty ratio of the IGBT lower tube is immediately updated in the next counting period, namely the comparison value cmpa _ u3 of the duty ratio of the IGBT lower tube in the symmetrical PWM output is 0, and the IGBT lower tube immediately and constantly outputs a low level; the IGBT upper tube keeps the comparison value cmpa _ u1 of the original duty ratio (namely the comparison value cmpa _ u1 of the duty ratio of the IGBT upper tube in the symmetrical PWM output) unchanged, the level overturning condition is consistent with the previous period, the comparison value cmpa _ u1 of the duty ratio of the IGBT upper tube in the symmetrical PWM output is updated to be 0 after the whole counting period, the IGBT upper tube starts to output high level, and the duty ratio reaches 100% at the moment.

In step 44, when the comparison value of the duty ratio (e.g., the comparison value cmpa of the duty ratio calculated by the microprocessor) decreases from 100%, the fourth setting strategy, i.e., the strategy shown in fig. 6, is executed.

Fig. 6 is a timing chart when the duty ratio is decreased from 100%. As can be seen from fig. 6, the FPGA receives the comparison value cmpa of the given duty ratio of the microprocessor (i.e., the comparison value cmpa of the duty ratio calculated by the microprocessor) at any time, and when the comparison value of the given duty ratio of the microprocessor is switched from a value smaller than the DEAD zone period (i.e., the DEAD zone count period value DEAD _ CLOCK) to a value not smaller than the DEAD zone period (i.e., the DEAD zone count period value DEAD _ CLOCK), the comparison value of the duty ratio of the upper tube of the IGBT is immediately updated in the next count period, i.e., the comparison value cmpa _ u1 of the duty ratio of the upper tube of the IGBT in the symmetric PWM output is equal to the comparison value cmpa of the given duty ratio of the microprocessor, and the upper tube of the IGBT immediately changes from the high level to the low level to start normal; the IGBT lower tube keeps the comparison value cmpa _ u3 of the original duty ratio to be 0 (namely the comparison value cmpa _ u3 of the duty ratio of the IGBT lower tube in the symmetrical PWM output to be 0), keeps the low level and the previous period consistent, after a whole counting period, the comparison value cmpa _ u3 of the duty ratio of the IGBT lower tube in the symmetrical PWM output is updated to the comparison value cmpa-DEAD _ CLOCK (DEAD zone counting period value) of the given duty ratio of the microprocessor, the IGBT lower tube starts to output the high level, and the duty ratio is reduced from 100% at the moment.

In the scheme of the invention, on the aspect of processing the comparison value cmpa of the duty ratio calculated by the microprocessor, the dead zone processing is included, so that the comparison value cmpa of the duty ratio calculated by the microprocessor for the upper and lower tubes of the IGBT can be distinguished due to the dead zone, and the specific strategy is shown in table 1.

As can be seen from table 1, when the comparison value cmpa of the duty ratio calculated by the microprocessor is not less than the DEAD time (e.g., DEAD count period value DEAD _ CLOCK), in each complete up-down count period, the value is directly used as the comparison value of the high and low levels by the upper IGBT pipe, and the DEAD zone is added to the lower IGBT pipe to prevent the through connection, so that the comparison value cmpa-DEAD _ CLOCK makes the DEAD time difference when the lower IGBT pipe and the upper IGBT pipe are connected; when cmpa is PERIOD, the duty ratio is 0, so the upper tube cmpa _ u1 value only needs to be larger than PERIOD, and the comparison result is tb _ count +1< cmpa _ u1, so it is always low level, and the tube satisfies the condition of being high level; when cmpa is smaller than the dead time, the duty ratio reaches 100%, namely the upper tube is constantly at a high level, and the lower tube is constantly at a low level.

At this time, the cmpa _ u1 value is taken to be 0, so that the comparison results are tb _ count +1> cmpa _ u1, and therefore, the comparison result is always high level, and the comparison result is basically symmetric and always low level. The reason why tb _ count +1 is used instead of tb _ count is that the D flip-flop used by the FPGA timing circuit needs to be processed one cycle earlier in data processing.

In the scheme of the invention, in the aspect of duty ratio updating, the increase and decrease count value tb _ count starts to change after the FPGA normally works, and the change is always 0-PERIOD-0, because the microprocessor can send the comparison value cmpa of the changed duty ratio to the FPGA (see figure 5 or figure 6) at any time, and the comparison result of tb _ count +1 and cmpa is uniquely determined, if the comparison value of the duty ratios of the upper pipe and the lower pipe is directly calculated and updated according to the table at the moment, the corresponding change of immediate conduction of the upper pipe and the lower pipe occurs, and the upper pipe and the lower pipe simultaneously change without dead zone processing, so that the upper pipe and the lower pipe are directly connected. Aiming at the problem, the processing mode of the invention is as follows: if cmpa changes, the comparison value of the duty ratios of the upper and lower tubes is updated by delaying until the next new count period, that is, tb _ count is equal to 0, and the comparison value of the duty ratios of the upper and lower tubes is calculated according to table 1.

In the embodiment of the present invention, in the dead zone processing problem at the time of the full duty, when cmpa is 0, even if the comparison value of the duty ratios of the upper and lower pipes is updated by calculation in table 1 at a new count period, the upper and lower pipes operate simultaneously, and the upper pipe outputs a high level instantaneously when tb _ count is 0, and the lower pipe outputs a low level instantaneously, so that the dead zone cannot be satisfied. Further analyzing, when the duty ratio is increased to 100%, in order to satisfy the dead zone, the lower pipe immediately updates the comparison value cmpa _ u3 of the duty ratio to 0 (i.e. pull low first), and the upper pipe delays the comparison value cmpa _ u1 of the updated duty ratio to 0 by the next new period (tb _ count to 0), see fig. 5; when the duty ratio is decreased from 100%, that is, the comparison value of the duty ratio is switched from being smaller than the dead zone period value to being not smaller than the dead zone period value, the comparison value is updated when a new count period tb _ count is equal to 0, the upper pipe is instantly changed from the previous high level to the low level, the lower pipe is instantly changed from the previous low level to the high level, and at this time, there is no dead zone, and for this problem, the comparison value of the duty ratio is updated immediately by the upper pipe, and the comparison value of the duty ratio is updated by the lower pipe in a delayed manner until the next new period (tb _ count is equal to 0), as shown in fig. 6. These two special cases delay to the next new cycle rather than directly delaying the DEAD CLOCK cycle (DEAD CLOCK) because the cmpa and DEAD time comparisons may produce narrow pulses. With these two special exceptions, the remaining duty cycle changes satisfy the dead band when updating the upper and lower tube duty cycles in a new count period (tb _ count ═ 0).

In summary, according to the multi-path symmetrical variable frequency PWM wave control and output method based on the FPGA provided by the present invention, the multi-path PWM waves output based on the FPGA are all output according to the above control strategy, and each path of PWM wave command signal is controlled by the microprocessor, so that normal output of full duty ratio PWM waves is realized on the premise of meeting the dead zone. Therefore, multi-path symmetrical output of variable high-frequency PWM waves is realized, and meanwhile, the dead time is increased along with the reduction of PWM frequency, so that the loss of a power switch device is reduced; the symmetrical output of PWM waves with any duty ratio of 0-100% is realized, and meanwhile, the generation of narrow pulses is prevented by optimizing the duty ratio of 100%.

Since the processes and functions implemented by the motor of this embodiment substantially correspond to the embodiments, principles and examples of the apparatus shown in fig. 2, the descriptions of this embodiment are not detailed, and refer to the related descriptions in the embodiments, which are not described herein.

Through a large number of tests, the technical scheme of the invention is adopted, the microprocessor is combined with the microprocessor (such as a DSP or an ARM) and the FPGA to send the enabling signal (such as an on signal or an off signal), the given duty ratio and the frequency signal of the PWM wave, the FPGA outputs the corresponding PWM wave under the condition of receiving the enabling signal, the given duty ratio and the frequency signal sent by the microprocessor, and the requirement of time-varying carrier wave in actual use can be met through frequency variation, and meanwhile, the loss of a switching device is reduced.

According to an embodiment of the present invention, there is also provided a storage medium corresponding to a control method of a motor, the storage medium including a stored program, wherein an apparatus in which the storage medium is controlled when the program is executed performs the above-described control method of a motor.

Since the processing and functions implemented by the storage medium of this embodiment substantially correspond to the embodiments, principles, and examples of the method shown in fig. 1, reference may be made to the related descriptions in the foregoing embodiments for details which are not described in detail in the description of this embodiment, and thus no further description is given here.

Through a large number of tests, by adopting the technical scheme of the invention, the microprocessor (such as a DSP or an ARM) and the FPGA are combined, the microprocessor sends an enabling signal (such as an on signal or an off signal), a given duty ratio and a frequency signal of the PWM wave, and the FPGA outputs the corresponding PWM wave under the condition of receiving the enabling signal, the given duty ratio and the frequency signal sent by the microprocessor.

According to an embodiment of the present invention, there is also provided a processor corresponding to a control method of a motor, the processor being configured to run a program, wherein the program is configured to execute the control method of the motor described above when running.

Since the processing and functions implemented by the processor of this embodiment substantially correspond to the embodiments, principles, and examples of the method shown in fig. 1, reference may be made to the related descriptions in the foregoing embodiments for details which are not described in the description of this embodiment, and thus no further description is given here.

Through a large number of tests, the technical scheme of the invention is adopted, the microprocessor is combined with the microprocessor (such as a DSP or an ARM) and the FPGA to send the enabling signal (such as an on signal or an off signal), the given duty ratio and the frequency signal of the PWM wave, the FPGA outputs the corresponding PWM wave under the condition of receiving the enabling signal, the given duty ratio and the frequency signal sent by the microprocessor, and the unique time sequence control scheme is adopted to realize the dead zone and full duty ratio when the PWM wave is symmetrically output.

In summary, it is readily understood by those skilled in the art that the advantageous modes described above can be freely combined and superimposed without conflict.

The above description is only an example of the present invention, and is not intended to limit the present invention, and it is obvious to those skilled in the art that various modifications and variations can be made in the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A method of controlling a motor, the controller for the motor comprising: a microprocessor and an FPGA; the control method of the motor comprises the following steps:

sending enable signals, duty ratio signals and frequency signals of PWM waves of all power switching tubes in an inverter bridge of the motor to the FPGA by the microprocessor; wherein, the enabling signal of the PWM wave comprises: an off signal of the PWM wave, or an on signal of the PWM wave;

under the condition that the microprocessor and the FPGA are electrified and work, or under the condition that the FPGA receives a turn-off signal of the PWM wave, the FPGA turns off the PWM wave;

and under the condition that the FPGA receives the enabling signal, the duty ratio signal and the frequency signal of the PWM wave, the FPGA controls the PWM wave according to the received enabling signal, the duty ratio signal and the frequency signal of the PWM wave and outputs the controlled PWM.

2. The method of controlling a motor according to claim 1, wherein the controlling the PWM wave and outputting the controlled PWM wave by the FPGA according to the received on signal of the PWM wave includes:

and under the condition that the FPGA receives the conduction signal of the PWM wave, the FPGA starts to output the PWM signal.

3. The method of controlling a motor according to claim 1, wherein the duty signal includes: a comparison value of the duty cycle given by the microprocessor;

controlling, by the FPGA, the PWM wave according to the received duty ratio signal of the PWM wave, and outputting the controlled PWM, further comprising:

if the comparison value of the duty ratio given by the microprocessor is larger than or equal to the set dead zone counting period value, controlling the comparison value of the duty ratio of an upper IGBT tube in the inverter bridge to be the comparison value of the duty ratio given by the microprocessor, and controlling the comparison value of the duty ratio of a lower IGBT tube in the inverter bridge to be the difference value of the comparison value of the duty ratio given by the microprocessor and the dead zone counting period value;

if the comparison value of the duty ratio given by the microprocessor is equal to the set counting period value, controlling the comparison value of the duty ratio of an upper tube of the IGBT in the inverter bridge to be the sum of the counting period value and the set value, and controlling the comparison value of the duty ratio of a lower tube of the IGBT in the inverter bridge to be the sum of the counting period value and the set value;

if the comparison value of the duty ratio given by the microprocessor is increased to 100% of the set duty ratio and the comparison value of the duty ratio given by the microprocessor is smaller than the set dead zone counting period value, controlling the comparison value of the duty ratio of the IGBT lower tube in the inverter bridge to be updated to 0 when the next new counting period starts, and controlling the IGBT upper tube in the inverter bridge to be updated to 0 after delaying for one PWM period;

and if the comparison value of the duty ratio given by the microprocessor begins to decline from 100% of the set duty ratio and the comparison value of the duty ratio given by the microprocessor is switched from being smaller than the set dead zone counting period value to being not smaller than the set dead zone counting period value, controlling the comparison value of the duty ratio of an upper tube of the IGBT in the inverter bridge to be updated to the comparison value of the duty ratio given by the microprocessor when the next new counting period begins, controlling the lower tube of the IGBT in the inverter bridge to be delayed for one PWM period and then updating the comparison value of the duty ratio, and controlling the difference value of the comparison value of the duty ratio given by the microprocessor and the dead zone counting period value.

4. The method of controlling a motor according to claim 3, wherein the frequency signal includes: setting a PWM frequency;

the FPGA controls the PWM wave according to the received frequency signal of the PWM wave and outputs the controlled PWM, and the method further comprises the following steps:

under the condition that the FPGA main frequency is greater than the given PWM frequency, determining that a set counting period value is equal to half of the ratio of the FPGA main frequency to the given PWM frequency; the set counting period value is the maximum value of the counting period of the increase and decrease of the counting value of the time base;

under the condition that a comparison value of a duty ratio given by the microprocessor is less than or equal to the time base count value, controlling PWM waves on an IGBT (insulated gate bipolar translator) in the inverter bridge to output a low level, otherwise, outputting a high level; and controlling the PWM wave output of the lower tube of the IGBT in the inverter bridge to be opposite to the PWM wave output of the upper tube of the IGBT in the inverter bridge.

5. The method according to any one of claims 1 to 4, wherein outputting the controlled PWM by the FPGA includes:

and the FPGA symmetrically outputs the controlled PWM by adopting an up-down counting mode.

6. A control apparatus of a motor, characterized in that a controller of the motor comprises: a microprocessor and an FPGA; the control device of the motor comprises:

a communication unit configured to transmit, by the microprocessor, to the FPGA, enable signals, duty ratio signals, and frequency signals of PWM waves of all power switching tubes in an inverter bridge of the motor; wherein, the enabling signal of the PWM wave comprises: an off signal of the PWM wave, or an on signal of the PWM wave;

the control unit is configured to switch off the PWM wave by the FPGA under the condition that the microprocessor and the FPGA are electrified and work or the FPGA receives a switch-off signal of the PWM wave;

the control unit is further configured to, when the FPGA receives the enable signal, the duty ratio signal, and the frequency signal of the PWM wave, control, by the FPGA, the PWM wave according to the received enable signal, the duty ratio signal, and the frequency signal of the PWM wave, and output the PWM after the control.

7. The motor control device according to claim 6, wherein the control unit controls the PWM wave by the FPGA according to the received ON signal of the PWM wave and outputs the controlled PWM, and includes:

8. The control device of an electric motor according to claim 6, wherein the duty signal includes: a comparison value of the duty cycle given by the microprocessor;

the control unit is used for controlling the PWM wave by the FPGA according to the received duty ratio signal of the PWM wave and outputting the controlled PWM, and the control unit further comprises:

9. The control device of an electric motor according to claim 8, wherein the frequency signal includes: setting a PWM frequency;

the control unit is controlled by the FPGA according to the received frequency signal of the PWM wave, and outputs the controlled PWM, and further includes:

10. The control device of an electric motor according to any one of claims 6 to 9, wherein the control unit outputs the controlled PWM by the FPGA, and includes:

11. An electric machine, comprising: a control device of an electric motor according to any one of claims 6 to 10.

12. A storage medium characterized by comprising a stored program, wherein an apparatus in which the storage medium is controlled when the program is executed performs the control method of the motor according to any one of claims 1 to 5.

13. A processor, characterized in that the processor is configured to run a program, wherein the program is configured to execute the control method of the electric machine according to any one of claims 1 to 5 when running.