CN204904128U - Band gap reference circuit - Google Patents

Abstract

The utility model relates to a band gap reference circuit. This circuit includes the 11 transistor, the 5th transistor, third transistor, fourth transistor, the 6th transistor, operational amplifier. Third transistor, fourth crystal are the diode connected mode. Third transistor, fourth transistor constitute first fortune and put the partly of loop, and third transistor, the work of fourth transistor are distinguished at the sub -threshold to make third transistor, fourth transistor voltage difference be positive temperature coefficient voltage. The 5th transistor of fourth transistor AND gate meets, and the 5th transistor AND gate the 6th transistor meets, and the 5th transistor, the 11 transistor, operational amplifier meet, and the 6th transistor is the diode connected mode. The 6th transistor work is distinguished at the sub -threshold to it is negative temperature coefficient voltage to make the 6th transistor voltage, and then makes zero temperature coefficient's of this circuit output reference voltage. The utility model discloses can be used to in the deep submicron process integration circuit.

Description

A kind of band-gap reference source circuit

Technical field

The utility model relates to integrated circuit fields, particularly relates to the power technique fields in integrated circuit.

Background technology

Along with the high speed development of large scale integrated circuit, the continuous renewal of chip production process processing procedure, chip power supply voltage needs constantly to reduce to realize low consumption circuit design.Therefore chip internal functional module is proposed to the requirement of low-voltage and low-power dissipation.Many chips need to use band gap reference to provide reference voltage to the ADC (analog to digital converter) of inside, DAC (digital to analog converter), SerDes (serializer deserializer) circuit module.The minimum supply voltage of reference circuit is that chip takes the one of single power supply system one of to limit, and the performance of power supply rejection ability to chip of reference circuit also has a certain impact simultaneously.

As shown in Figure 1, this band gap reference comprises resistance R1, R2, R3 to the implementation of traditional low pressure band gap reference, triode Q1, Q2, PMOS M1, M2, M3, amplifier OP1.It is equal with negative terminal voltage that loop feedback effect due to amplifier makes amplifier input anode, can obtain:

V _be2＝V _be1+I1*R1

$I1=\frac{{\mathrm{\ΔV}}_{be}}{R1}+\frac{V_{be2}}{R2}$

Vref＝I1*R3(1)

Wherein, V _be1the base emitter voltage of triode Q1, V _be2the base emitter voltage of triode Q2, △ V _bethat triode Q1 and triode Q2 base emitter voltage are poor, generally in order to produce △ V _beand consider domain matching precision, the area ratio of Q1 and Q2 can be designed to 8:1 or 24:1.

From formula (1), traditional low pressure band gap reference structure passes through V _benegative temperature coefficient feature and △ V _beptc characteristics on resistance, produce the electric current I 1 of zero-temperature coefficient, by PMOS current mirror M1, M2, M3, this current mirror is exported on resistance R3, to produce zero-temperature coefficient voltage.In order to normally work under low voltage condition, reference voltage can be designed to low voltage to alleviate the requirement of this circuit to supply voltage.The minimum supply voltage that this circuit can normally work is:

VDD _min＝V _dsat1,2+V _be2(2)

Wherein, V _dsat1,2the overdrive voltage of PMOS M1, M2, V _be2it is the base emitter voltage of triode Q2.In modern CMOS processes, V _be2voltage is generally 850mV.V _dsat1,2be designed to 150mV to ensure certain matching precision.

In sum, the minimum supply voltage that this traditional circuit can normally work is 1V.This voltage is difficult to meet low-voltage in modern deep sub-micron CMOS technology, low-power consumption requirement.As seen from Figure 1, the reference voltage that band gap exports is that reference current produces on resistance R3, and this reference voltage generating circuit is not placed in the loop of amplifier OP1, and due to the short channel mudulation effect in deep submicron process, the power supply rejection ability of this circuit is limited.Meanwhile, this circuit needs unity gain buffer just can have certain band resistive load ability.

Utility model content

The utility model proposes a kind of band-gap reference source circuit overcome the above problems.

In first aspect, the utility model provides a kind of band-gap reference source circuit.This circuit comprises the 11 transistor, the 5th transistor, third transistor, the 4th transistor, the 6th transistor and operational amplifier.This third transistor, the 4th crystal are diode connected mode, and this third transistor, the 4th transistor form a part for the first amplifier loop, and this third transistor, the 4th transistor are in sub-threshold region.4th transistor AND gate the 5th transistor connects, 5th transistor AND gate the 6th transistor connects, and the 5th transistor, the 11 transistor, this operational amplifier connect, 6th transistor is diode connected mode, and the 6th transistor is in sub-threshold region, thus this circuit is made to export the reference voltage of zero-temperature coefficient.

The utility model is by making transistor in sub-threshold region, utilize the positive negative temperature characteristic of transistor to provide low suppling voltage solution, and by sharing amplifier input pipe and current mirror formation output stage amplifier, reference voltage generating circuit is placed in amplifier loop, improves power supply and suppress and band resistive load ability.The utility model circuit is applicable to deep submicron process Power supply environment, and this circuit can normally be operated in 0.7V supply voltage, and circuit structure is simple, and circuit area is much smaller than traditional structure, and cost is lower.

Accompanying drawing explanation

By being described preferred embodiment referring to accompanying drawing, advantage of the present utility model will become more apparent and easy to understand.

Fig. 1 is the band-gap reference source circuit schematic diagram of prior art;

Fig. 2 is the band-gap reference source circuit schematic diagram of the utility model embodiment;

Fig. 3 is the band-gap reference source circuit reference voltage temperature curve schematic diagram of the utility model embodiment;

Fig. 4 is that the band-gap reference source circuit reference voltage Meng Takanuo of the utility model embodiment emulates schematic diagram;

Fig. 5 is the band-gap reference source circuit output stage carrying load ability schematic diagram of the utility model embodiment.

Embodiment

By reference to the accompanying drawings by the more detailed explanation the purpose of this utility model of embodiment, technical scheme and advantage.The utility model also can be implemented by other various different mode similar to it or be used, each details in this instructions also can based on different viewpoints and use, and those skilled in the art can carry out modification or the change of various ways when not deviating from the utility model object.

It should be noted that, Fig. 2 to Fig. 5 only illustrates basic ideas of the present utility model in a schematic way, built-up circuit number when Fig. 2 to Fig. 5 only shows the built-up circuit relevant with the utility model but not implements according to reality, shape, device arrangement mode, connected mode are drawn, it is actual when implementing, and the kenel of each circuit, quantity, connected mode, device arrangement mode, device parameters can be random change, and its each electrical combination mode also may be very complicated.

Refer to Fig. 2, as shown in the figure, the band-gap reference source circuit of the utility model embodiment, comprising: metal-oxide-semiconductor M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, electric capacity C1, CL, resistance R1, R2, R3.

In Fig. 2, NMOS tube M3, M4, resistance R1 and PMOS M9, M10 constitute positive temperature coefficient (PTC) current generating circuit.This resistance R1 one end ground connection VSS, another termination NMOS tube M3 source electrode.This NMOS tube M3 grid connects its drain electrode, and both this NMOS tube M3 was diode connected mode, and this NMOS tube M3 drain electrode connects PMOS M9 drain electrode.This PMOS M9 source electrode connects PMOS M10 source electrode and meets power vd D, and this PMOS M9 grid connects PMOS M10 grid.This PMOS M10 drain electrode is connected to NMOS tube M4 drain electrode and grid, and both this NMOS tube M4 was diode connected mode, and this NMOS tube M4 source ground VSS.

In this positive temperature coefficient (PTC) current generating circuit, NMOS tube M3, NMOS tube M4, PMOS M9, PMOS M10, resistance R1 constitute an amplifier loop, and NMOS tube M3, M4 constitute diode connecting circuit, NMOS tube M3, PMOS M9 and NMOS tube M4, PMOS M10 constitute active electric current mirror circuit, and this NMOS tube M3, M4 are operated in sub-threshold region.Due to the effect of amplifier loop feedback, make NMOS tube M3, M4 grid voltage equal, can obtain:

V _gs4＝V _gs3+I2*R1

$I2=\frac{{\mathrm{\ΔV}}_{gs}}{R1}---\left(3\right)$

Wherein, V _gs3nMOS tube M3 gate source voltage, V _gs4nMOS tube M4 gate source voltage, △ V _gsv _gs3and V _gs4voltage difference, the pressure drop namely on resistance R1.Due to, when NMOS tube M3, M4 are operated in sub-threshold region, be positive temperature coefficient (PTC) voltage, the pressure drop namely on resistance R1 is positive temperature coefficient (PTC) voltage.Therefore, NMOS tube M3, M4 gate source voltage difference produce positive temperature coefficient (PTC) electric current on resistance R1.

Preferably, this NMOS tube M3 breadth length ratio is greater than this NMOS tube M4 breadth length ratio.Particularly, the ratio designing this NMOS tube M3 breadth length ratio and NMOS tube M4 breadth length ratio is 4:1.

It should be noted that, resistance R1 can have multiple way of realization, such as current source, passive resistance, active device (as nmos pass transistor) etc.In addition, this NMOS tube M3, M4 are not limited to NMOS tube, also can realize said function by PMOS, and this PMOS M9, M10 are also not limited to PMOS simultaneously, also can realize said function by NMOS tube.And NMOS tube of the present utility model, PMOS also can be replaced by other transistors, as triode etc.

To sum up, the utility model is operated in sub-threshold region NMOS tube M3, M4 gate source voltage temperature characterisitic by utilization, and circuit is reduced, under band-gap reference source circuit of the present utility model normally can be operated in 0.7 Ford supply voltage supply voltage demand.Therefore, band-gap reference source circuit of the present utility model is a kind of low voltage reference source circuit.

In Fig. 2, NMOS tube M1, M2 and PMOS M7, M8 constitute operational amplifier.This NMOS tube M1 source electrode connects NMOS tube M3 source electrode and connecting resistance R1, and this NMOS tube M1 grid connects NMOS tube M4 grid, and this NMOS tube M1 drain electrode meets this PMOS M8 and drains.This NMOS tube M2 source electrode connects this NMOS tube M4 source electrode and ground connection VSS, and this NMOS tube M2 grid meets this NMOS tube M3 and drains, and this NMOS tube M2 drain electrode connects PMOS M7 drain electrode.This PMOS M7 drain gate connects, and is connected to PMOS M8 grid, and this PMOS M7 source electrode connects this PMOS M8 source electrode and meets power vd D.This PMOS M8 drain electrode connects PMOS M9 and M10 grid, and drains this PMOS M8 as this operational amplifier output stage.

In this operation amplifier circuit, this NMOS tube M1, M2 are the input stage of this operational amplifier, and this PMOS M8 drains as this operational amplifier output stage.This PMOS M7, M8 constitute the active load of this operational amplifier, and this NMOS tube M1, PMOS M8 and this NMOS tube M2, PMOS M7 constitute current mirroring circuit.

This operational amplifier input stage can have multiple way of realization, and as common-gate input stage, common source input stage etc., the active load of this operational amplifier also can have multiple way of realization, as common-source common-gate current mirror, triode current mirror etc.And this NMOS tube M1, M2 are not limited to NMOS tube, also can realize said function by PMOS, this PMOS M7, M8 are also not limited to PMOS, also can realize said function by NMOS tube.

In addition, this operational amplifier also can have other ways of realization, as common-source amplifier, cathode-input amplifier, differential operational amplifier, two-stage differential operational amplifier etc.; Now, this differential amplifier input stage is connected to NMOS tube M4 grid, and its another input stage is connected to NMOS tube M3 grid, and its output stage is connected to PMOS M9, M10 grid.

In Fig. 2, NMOS tube M5, M6, resistance R2, R3, PMOS M11, M12, electric capacity C1, CL, NMOS tube M2, PMOS M7 constitute negative temperature coefficient voltage and produce and output-stage circuit, and this NMOS tube M2, PMOS M7 are also parts for above-mentioned operational amplifier.

This PMOS M12 source electrode connects PMOS M11 source electrode and connects PMOS M7 source electrode, and is connected to power vd D, and this PMOS M12 grid connects PMOS M11 drain electrode.This PMOS M12 of electric capacity C1 mono-termination drains, and another termination PMOS M11 drains, to provide AC frequency compensation.And this electric capacity C1 can have multiple way of realization, such as variable capacitance, MOM capacitor, MIM capacitor, active device (as nmos pass transistor), resistance and capacitances in series etc.

This PMOS M11 drain electrode connects NMOS tube M5 drain electrode, and this NMOS tube M5 grid connects NMOS tube M4 grid.This NMOS tube M5 source electrode connects NMOS tube M6 source electrode and connecting resistance R2 one end, this resistance R2 other end ground connection VSS, and connects NMOS tube M2 source electrode.This NMOS tube M6 grid drain electrode connects, and is connected to resistance R3 one end, and this resistance R3 other end is connected to electric capacity CL and is connected to output stage Vref, and this electric capacity CL other end is connected to resistance R2 and ground connection VSS.This PMOS M12 breadth length ratio is determined according to required output current ability.Wherein, this electric capacity CL is output load capacitance, plays pressure stabilization function; This electric capacity C1 is miller-compensated electric capacity.

This resistance R2, R3 can have multiple way of realization, such as current source, passive resistance, active device (as nmos pass transistor) etc.This NMOS tube M5, M6 are not limited to NMOS tube, can realize said function by PMOS, and this PMOS M11, M12 are also not limited to PMOS simultaneously, also can realize said function by NMOS tube.And this NMOS tube, PMOS also can realize said function by other transistor, as triode etc.

In the generation of this negative temperature coefficient voltage and output circuit, this NMOS tube M5, PMOS M11, NMOS tube M2, PMOS M7 form new amplifier loop (being called the second operational amplifier at this).In this second operational amplifier, this NMOS tube M5, M2 form input stage amplifier, and this PMOS M7, M11 are active load connected mode, and this PMOS M12, resistance R3, electric capacity C1, NMOS tube M6, resistance R2 form output buffer.Design this NMOS tube M6 and be operated in sub-threshold region, because this NMOS tube M6 is diode connected mode (both M6 grid connect drain electrode), therefore, this NMOS tube M6 gate source voltage is negative temperature coefficient voltage.

In this second operational amplifier, because NMOS tube M5, M2 and PMOS M7, M11 constitute amplifier feedback loop, therefore, this NMOS tube M5 grid voltage is equal with this NMOS tube M2 grid voltage, and NMOS tube M2 grid, M3 grid connect, and then the pressure drop making the pressure drop on resistance R2 equal on resistance R1, that is:

$I3+I4=\frac{{\mathrm{\ΔV}}_{gs}}{R1}$

I2＝I3＝I4

R2＝2*R1

$Vref=\frac{(R1+R3)*{\mathrm{\ΔV}}_{gs}}{R1}+V_{gs6}---\left(4\right)$

Wherein, V _gs6the gate source voltage of NMOS tube M6, △ V _gsv _gs3and V _gs4voltage difference, K1, K2 are constants.Find out from formula (4), electric current I 2, I3, I4 can proportionally design, and by the ratio of adjusting resistance R1, R2, R3, thus make output voltage Vref reach reference voltage value.Because NMOS tube M3, M4, M6 are operated in sub-threshold region, therefore basis ptc characteristics and negative temperature coefficient feature, finally obtain the output voltage Vref of zero-temperature coefficient.

Because this PMOS M12, resistance R3, NMOS tube M6, resistance R2 constitute the output-stage circuit of this band-gap reference source circuit, and this output-stage circuit is positioned at output stage amplifier loop, therefore the utility model provides good power supply rejection ability can also provide certain band resistive load ability simultaneously.

It should be noted that, described metal-oxide-semiconductor produces positive and negative temperaturecoefficient voltage and is not limited only to NMOS tube, also can realize by PMOS, and PMOS current mirroring circuit also can replace improving power supply rejection ability etc. by cascode structure.

In a word, the utility model produces output reference voltage by using the positive and negative temperature characterisitic being operated in the gate source voltage of sub-threshold region metal-oxide-semiconductor, forms output stage amplifier loop improve power supply suppression and band resistive load ability by shared amplifier input pipe and current mirror pipe.The utility model meets the requirement of low voltage power supply and power supply rejection ability under deep submicron process, can very easily be integrated in chip internal, and under this circuit normally can be operated in 0.7 volt of supply voltage, certain power supply can be provided to suppress and band resistive load ability simultaneously.

Fig. 3 is the band-gap reference source circuit reference voltage temperature curve schematic diagram of the utility model embodiment.As shown in the figure, in figure, abscissa axis is temperature, and axis of ordinates is band gap output reference voltage, and this curve shows this circuit temperature coefficient simulation scenarios, further illustrates the utility model result by emulated data.As seen from Figure 3, temperature-50 degree to 100 degree between time, along with the change of temperature, output voltage from 604.5 millivolts to 606.25 millivolts.Therefore, it is little that output voltage varies with temperature change, and the bandgap voltage reference exported is below 700 millivolts.

Fig. 4 is that the band-gap reference source circuit reference voltage Meng Takanuo of the utility model embodiment emulates schematic diagram.As shown in the figure, further illustrate reliability of the present utility model according to Meng Takanuo emulated data: in figure, abscissa axis is band gap output reference voltage, axis of ordinates is number of samples, and this figure can illustrate discreteness and the reliability of the reference voltage of this circuit.

Fig. 5 is the band-gap reference source circuit output stage carrying load ability schematic diagram of the utility model embodiment.As shown in the figure, output stage carrying load ability of the present utility model is further illustrated according to output stage belt current ability.In Fig. 5, abscissa axis is time shaft, and the axis of ordinates of first half component is output reference voltage, and the axis of ordinates of Lower Half component is load current, and this Fig. 5 can illustrate that the output stage of band-gap reference source circuit of the present utility model possesses the current driving ability of 1mA.

Above-described embodiment is the utility model preferred embodiment; but be not used to limit the utility model; as long as any amendment that those skilled in the art do in spirit of the present utility model and principle, equivalent variations and simple change etc., be all classified as within protection domain of the present utility model.

Claims (12)

1. a band-gap reference source circuit, this circuit comprises the 11 transistor, the 5th transistor, third transistor, the 4th transistor, the 6th transistor and operational amplifier;

This third transistor, the 4th crystal are diode connected mode, and this third transistor, the 4th transistor form a part for the first amplifier loop, and this third transistor, the 4th transistor are in sub-threshold region;

4th transistor AND gate the 5th transistor connects, 5th transistor AND gate the 6th transistor connects, 5th transistor, the 11 transistor, this operational amplifier connect, and the 6th transistor is diode connected mode, 6th transistor in sub-threshold region, thus makes this circuit export the reference voltage of zero-temperature coefficient.

2. a kind of band-gap reference source circuit as claimed in claim 1, it is characterized in that, this circuit also comprises the 9th transistor, the tenth transistor, the first resistance, and the 9th transistor AND gate the tenth transistor connects, tenth transistor AND gate the 4th transistor connects, 9th transistor, the first resistance connect with this third transistor, and the 9th transistor, the tenth transistor, the first resistance, the 4th transistor, this third transistor form described first amplifier loop.

3. a kind of band-gap reference source circuit as claimed in claim 2, it is characterized in that, described 9th transistor, the tenth transistor are PMOS, described third transistor, the 4th transistor are NMOS tube, and the 9th transistor gate connects with the tenth transistor gate, tenth transistor drain connects with the 4th transistor drain, and the 9th transistor drain drains with this third transistor and connects.

4. a kind of band-gap reference source circuit as claimed in claim 1, it is characterized in that, described operational amplifier comprises transistor seconds, the 7th transistor, this transistor seconds, the 7th transistor form a part for this operational amplifier, and this transistor seconds connects with the 7th transistor, 7th transistor AND gate the 11 transistor connects, and the 5th transistor, the 11 transistor, the 7th transistor, this transistor seconds form the second amplifier loop.

5. a kind of band-gap reference source circuit as claimed in claim 1, it is characterized in that, described operational amplifier comprises transistor seconds, the 7th transistor, the 8th transistor, the first transistor, and this transistor seconds connects with the 7th transistor, 7th transistor AND gate the 8th transistor connects, and the 8th this first transistor of transistor AND gate connects.

6. a kind of band-gap reference source circuit as claimed in claim 4, it is characterized in that, described transistor seconds, the 5th transistor are NMOS input pipe, described 7th transistor, the 11 transistor are PMOS, and the 7th transistor and the 11 transistor are active load connected mode, 5th transistor drain connects with the 11 transistor drain, and the 11 transistor gate connects with the 7th transistor gate, and the 7th transistor drain drains with this transistor seconds and connects.

7. a kind of band-gap reference source circuit as claimed in claim 5, it is characterized in that, described the first transistor, transistor seconds are NMOS input pipe, described 7th transistor, the 8th transistor are PMOS and are active load, and the drain electrode of this first transistor connects with the 8th transistor drain, 8th transistor gate connects with the 7th transistor gate, and the 7th transistor drain drains with this transistor seconds and connects.

8. a kind of band-gap reference source circuit as claimed in claim 7, is characterized in that, described the first transistor, transistor seconds are one in common-gate input stage, common source input stage; The connected mode of described active load is one in cascade connected mode, triode current mirror connected mode.

9. a kind of band-gap reference source circuit as claimed in claim 4, is characterized in that, this circuit also comprises the tenth two-transistor, and the tenth two-transistor connects with the 11 transistor.

10. a kind of band-gap reference source circuit as claimed in claim 9, it is characterized in that, described tenth two-transistor is PMOS, and the tenth two-transistor grid connects with the 11 transistor drain, and the tenth two-transistor source electrode connects with the 7th transistor source.

11. a kind of band-gap reference source circuits as claimed in claim 2, it is characterized in that, this circuit also comprises the second resistance, the 3rd resistance, and this first resistance first end connects with this third transistor, this the first resistance second end connects with this second resistance first end, this the second resistance second end connects with the 6th transistor second end, and the 6th transistor first end connects with the 3rd resistance first end, and using the output terminal of the 3rd resistance second end as this circuit.

12. a kind of band-gap reference source circuits as claimed in claim 11, it is characterized in that, this circuit also comprises the first electric capacity, the second electric capacity, and this first electric capacity one end connects with the 3rd resistance second end, the other end connects with the 11 transistor, this the second electric capacity one end connects with the 3rd resistance second end, and the other end connects with this second resistance first end.