CN204809212U - Semiconductor encapsulation structure - Google Patents

Semiconductor encapsulation structure Download PDF

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Publication number
CN204809212U
CN204809212U CN201520475374.9U CN201520475374U CN204809212U CN 204809212 U CN204809212 U CN 204809212U CN 201520475374 U CN201520475374 U CN 201520475374U CN 204809212 U CN204809212 U CN 204809212U
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Prior art keywords
chip
metal
metal framework
bonding wire
pin
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CN201520475374.9U
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Inventor
石磊
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Tongfu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The utility model provides a semiconductor encapsulation structure, including metal crate, chip, bonding wire and sheetmetal. The chip is provided with adhesives such as scaling powder or bonding die glue on being located metal crate between the chip back and the metal crate, metal crate's pin and chip are connected to the bonding wire, and the sheetmetal is located on the chip. Metal crate's pin passes through the bonding wire with the positive gate pole of chip to be connected, and the position that the sheetmetal was placed is corresponding with metal crate's position, and the sheetmetal passes through scaling powder metal crate and the chip is connected. The beneficial effects of the utility model are that: this structure has realized using under the different condition of chip size the sheetmetal of same size, reduction in production cost. Chip and pin be through falling the mode welding of routing, top -coat high -dielectric material under the sheetmetal simultaneously, and being connected between the welding method who uses bonding wire welding and sheetmetal bridging to combine, chip and metal crate is more inseparable, improves the yield of product, guarantees reliability of an item, the electrical property of improvement product.

Description

A kind of semiconductor package
Technical field
The utility model relates to a kind of semiconductor package, is specifically a kind of semiconductor package of bridge process.
Background technology
In the encapsulation process of semiconductor, solder technology core is welded by bonding wire or the technique of planting ball the gate pole of chip and garden and metal framework, the connection of forming circuit.Particularly in the packaging part being applied to high-power product, the reliability of welding procedure and electric heating property are particularly important.Accompanying drawing 1 and to Figure 2 illustrate in prior art two kinds of traditional Type of Welding, wherein Fig. 1 is the schematic diagram of bonding wire welding encapsulation in prior art, and accompanying drawing 2 is plant the schematic diagram that ball bonding connects encapsulation in prior art, wherein 1 is metal framework, 3 is chips, and 4 is bonding wires, and 7 is plant ball.Traditional bonding wire welding and plant the realization of ball bonding connection technology to technique and have higher requirements, wherein, in the process of producing product of high-power, high energy consumption, the silk that collapses produced after bonding wire welding, fracture of wire, short circuit phenomenon are more, directly affect the reliability of product.Planting during ball bonding connects, due to the more difficult control of the form of planting ball, plant the rate of finished products that the factors such as the size of ball, height all directly can affect product, wherein, plant ball shape and cross conference and cause short circuit, the too small meeting of shape causes electrical contact bad.
In order to constantly adapt to the demand of market for high-power product, the performance requirement such as reliability, power of packaging part also needs to improve gradually, and the sheet metal bridged encapsulation technology of packaging part more seems particularly important.Sheet metal material is generally copper or aluminium, and top layer is furnished with circuit, connects the pin of chip and metal framework, the connection of forming circuit, and adopting sheet metal to replace bonding wire or planting the technology that ball bonding connects is bridge welding connection technology.Sheet metal bridged encapsulation technology is compared bonding wire welding and is planted ball bonding and connects high-power, the high energy consumption requirement that more can meet product.In addition, use sheet metal bridging technology more effectively can must reduce the thickness of product, reduce small product size, be applicable to the development trend that electronic product is less, thinner.
And existing sheet metal bridging technology, also there is certain defect.Such as, if each weldering gate pole of chip and circle district only use a sheet metal bridge joint, will cause chip power short circuit, chip functions lost efficacy.If use two sheet metal bridge joints, just need the two or more sheet metals making different size and size respectively, the gate pole in a sheet metal welding chip front and the first pin of framework, the round district in another sheet metal welding chip front and other pins of framework.And bridge joint in units of every product, welding procedure difficulty is comparatively large, and life cycle of the product is longer.If use the welding method that bonding wire welding and sheet metal bridge joint combine, because sheet metal position is above bonding wire, and the relative position of sheet metal and metal framework is fixed, and bonding wire is the fine rule having certain radian, the height of bonding wire must maintain a certain distance with sheet metal, and the line style of bonding wire and the more difficult control of camber, if touch with sheet metal, will cause short circuit, chip functions lost efficacy.As shown in Figure 3, Fig. 3 is traditional bonding wire welding procedure schematic diagram, and in traditional bonding wire welding procedure, a solder joint on chip is the first solder joint, and the b solder joint on metal framework is the second solder joint.Traditional welding procedure order be first weld a solder joint, then pulls out line segment and 1. bends afterwards, and 2. pull-out line segment bends afterwards, then pulls out line segment and 3. bend afterwards, welds b point.Bonding wire with the process of bending, is formed with the fairshaped bank shape of a peak in continuous bracing wire.In order to make bank have certain radian, often camber is very high for the camber line that traditional bonding wire welding procedure is formed, and in the operation of sheet metal bridge joint, bonding wire can contact with sheet metal and cause short circuit.And sheet metal must keep certain shape and angle when welding, as shown in Figure 4, Fig. 4 is traditional sheet metal bridging structure profile, and 2 is scaling powders, and 6 is sheet metals.Shape due to sheet metal is special, also just needs to make certain moduli tool and makes sheet metal, also needs the shape and the height that control sheet metal, adds the cost of product, bring difficulty to the volume production of product.
In sum, traditional sheet metal bridging technology can not meet performance requirement that is high-power, high energy consumption product while raising product encapsulation yield, reduction production cost.
Summary of the invention
For overcoming the above-mentioned problems in the prior art, the utility model provides a kind of semiconductor package, comprises metal framework, chip, bonding wire and sheet metal.The adhesive such as scaling powder or bonding die glue is provided with between chip back and metal framework, first pin of metal framework is connected by bonding wire with the gate pole of chip front side, other pins of metal framework are connected by sheet metal with the round district of chip front side, the round district of chip front side and and other pins of metal framework be provided with scaling powder, the position that sheet metal is placed is corresponding with the position of metal framework, also bridge joint with it on other pins covering chip front side and metal framework.
Preferably, high pin metal framework refers to that height of pin is greater than the metal framework of chip height, and metal framework material is copper, aluminium, silver or alloy.
Further, chip is had above metal framework.Arrange back scaling powder or bonding die glue in the middle of metal framework and chip, metal framework and chip are directly by scaling powder with bonding die is gluing connects.
Further again, the gate pole of chip is connected with the first pin of framework, and bonding wire directly connects the gate pole of chip and the first pin of framework.
Further, the below of sheet metal is provided with strong dielectric material.Apply strong dielectric material in the below (one side be namely connected with chip) of sheet metal, need according to sheet metal the position being coated with strong dielectric material, make the mould with figure, the opening on mould is the region needing to be coated with strong dielectric material.By die cover above sheet metal, then brush one deck strong dielectric material, namely form dielectric layer on sheet metal surface, the material of sheet metal is the metal such as copper, aluminium.
Further, sheet metal is connected with the round district of chip and other pins of metal framework, and sheet metal position is on the pin of chip and metal framework.Brush scaling powder on the round district of chip surface and other pins of metal framework, then sheet metal cover on other pins of chip and metal framework, position is corresponding with other Pin locations of chip and metal framework, after Reflow Soldering, namely sheet metal, chip and metal framework form bridging structure.
Preferably, the material of metal framework is the metals such as copper, silver or alloy.The material of bonding wire is the metals such as gold, copper, alloy, and sheet metal material is the metal such as copper, aluminium, and shape is tabular.
Compared with prior art, the beneficial effect of the utility model method is: the metal framework of high pin, chip, bonding wire and flat sheet metal, constitute a kind of more practical semiconductor bridge joint encapsulating structure.Save production cost, simplify production procedure, improve the yield of product, ensure the reliability of product, also reduce the technology difficulty of sheet metal bridge joint, the production cost reducing sheet metal and life cycle of the product further.Also make the connection between chip and metal framework more tight, the heat conduction of product after bridge joint, conduction and reliability significantly improve, the utility model raising product encapsulation yield, reduce production cost while meet performance requirement that is high-power, high energy consumption product.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of bonding wire welding encapsulation in prior art
Fig. 2 plants the schematic diagram that ball bonding connects encapsulation in prior art
Fig. 3 is traditional bonding wire welding procedure schematic diagram
Fig. 4 is traditional sheet metal bridging structure profile
Fig. 5 is the metal framework schematic diagram of high pin
Fig. 6 is chip rear structural representation bonding with metal framework
Fig. 7 is structural representation after gate pole is connected with pin
Fig. 8 is independent pin bonding wire welding portion enlarged drawing in Fig. 4
The independent pin welding sequence figure of Fig. 9 welding procedure of falling routing
Figure 10 is the section of structure after bonded metal sheet
Figure 11 is chip rear structural representation bonding with metal framework
Figure 12 is finished product structure chart
Embodiment
Below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
In the first execution mode of the present utility model, provide a kind of semiconductor package.This structure comprises: metal framework, chip, bonding wire and sheet metal.The adhesive such as scaling powder or bonding die glue is provided with between chip back and metal framework, first pin of metal framework is connected by bonding wire with the gate pole of chip front side, other pins of metal framework are connected by sheet metal with the round district of chip front side, the round district of chip front side and and other pins of metal framework be provided with scaling powder, the position that sheet metal is placed is corresponding with the position of metal framework, also bridge joint with it on other pins covering chip front side and metal framework.
As shown in Figure 5, Fig. 5 is metal framework 1 schematic diagram of high pin.The height of pin of this metal framework 1 is apparently higher than the height of traditional pin, and the height of pin in the present embodiment is greater than chip thickness, and metal framework 1 material is the metals such as copper, aluminium, silver or alloy.High pin metal framework 1 design of the present utility model is not limited to the present embodiment.
The back side of chip 3 is bonding with metal framework 1.As shown in Figure 6, Fig. 6 is chip 3 back side rear structural representation bonding with metal framework 1, and 1 is the metal framework that high pin designs, and 2 is scaling powders, and 3 is chips.Adhering chip 3 on metal framework 1, metal framework 1 is bonding by scaling powder 2 with the back side of chip 3.Particularly, first at metal framework 1 surface brush one deck scaling powder 2, be then placed on metal framework 1 by chip 3, through Reflow Soldering, chip 3 back side is namely bonding with metal framework 1.
The gate pole in chip 3 front welds with the first pin of metal framework 1.The nip of chip surface is divided into gate pole and circle district, and gate pole is power end, and district is other functional areas.In the utility model, bonding wire welding refers to that gate pole is welded with the first pin of metal framework by bonding wire, and welding Zhi Yuan district of circle district is by sheet metal and other pin bridge joints.As shown in Figure 7, Fig. 7 is structural representation after gate pole is connected with pin, and the gate pole (not shown) of chip 3 is welded with the pin of metal framework 1 by bonding wire 4.As shown in Figure 8, Fig. 8 is independent pin bonding wire welding portion enlarged drawing in Fig. 7, and a solder joint is the gate pole of chip, and b solder joint is the solder joint on metal framework 1 pin.The utility model uses the technique of routing to be welded with b solder joint by a solder joint.In the utility model, adopt the mode of routing to weld bonding wire, as shown in Figure 9, Fig. 9 is the independent pin welding sequence figure of the welding procedure of falling routing, in the technique of falling routing, first welds b solder joint, then pull out line segment 1. to bend afterwards, 2. pull-out line segment bends afterwards, then pulls out line segment and 3. bend afterwards, then welds a solder joint.Adopt the technique of routing, compared with traditional routing mode, effectively can reduce the camber of bonding wire, solve bonding wire welding to combine with sheet metal bridge joint the larger process difficulties of product height, after avoiding Product jointing, bonding wire and sheet metal touch the short circuit occurred, the yield of raising product, ensure the reliability of product, also reduce the technology difficulty of sheet metal bridge joint further, ensure that carrying out smoothly of subsequent metal sheet bridge joint operation, the reliability of product is guaranteed.Those skilled in the art should know, and in actual production, the bank line style of bonding wire is not limited to the present embodiment, and the present embodiment is only described the welding sequence of bonding wire.
Other pin bridge joints of chip 3 circle district and metal framework 1.As shown in Figure 10, Figure 10 is the section of structure after bonded metal sheet 6.5 is strong dielectric materials, and 6 is sheet metals.In this step, first below sheet metal, one deck strong dielectric material 5 is coated with.Then on chip 3 and above other pins of metal framework 1, one deck scaling powder 2 is coated with, again sheet metal 6 is covered in the round district in the front of chip 3 and other pins of metal framework 1, the placement location of sheet metal 6 is corresponding with the position of metal framework 1, on other pins covering described chip 3 front and described metal framework 1, do not cover the pin welded with the gate pole of crystal column surface.Carry out Reflow Soldering again, namely sheet metal completes bridge joint with chip 3 and metal framework 1.The connection of the common forming circuit of sheet metal 6, chip 3, bonding wire 4 and metal framework 1.
Carry out the plastic packaging of product subsequently, and the operation such as cutting, as Figure 12, Figure 12 is product structure schematic diagram.
In the second embodiment of the present utility model, the first embodiment is improved.Particularly, in this embodiment, improve the bonding way of the first embodiment chips 3 and metal framework 1, in this embodiment, metal framework 1 is brushed with bonding die glue 7 above; Chip 3 is bonding with metal framework 1; Chip 3 rear baking bonding with metal framework 1.
Figure 11 is chip rear structural representation bonding with metal framework, and 1 is the metal framework that high pin designs, and 7 is bonding die glue, and 3 is chips.Adhering chip 3 on metal framework 1, metal framework 1 is bonding by bonding die glue 7 with chip 3.
Compared with prior art, the beneficial effect of the utility model method is: the metal framework of high pin, chip, bonding wire and flat sheet metal, constitute a kind of more practical semiconductor bridge joint encapsulating structure.Save production cost, simplify production procedure, improve the yield of product, ensure the reliability of product, also reduce the technology difficulty of sheet metal bridge joint, the production cost reducing sheet metal and life cycle of the product further.Also make the connection between chip and metal framework more tight, the heat conduction of product after bridge joint, conduction and reliability significantly improve, the utility model is compared traditional routing and is planted ball welding procedure, while raising product encapsulation yield, reduction production cost, meet performance requirement that is high-power, high energy consumption product.
Above-mentioned explanation illustrate and describes preferred embodiment of the present utility model, as previously mentioned, be to be understood that the utility model is not limited to the form disclosed by this paper, should not regard the eliminating to other embodiments as, and can be used for other combinations various, amendment and environment, and can in invention contemplated scope described herein, changed by the technology of above-mentioned instruction or association area or knowledge.And the change that those skilled in the art carry out and change do not depart from spirit and scope of the present utility model, then all should in the protection range of the utility model claims.

Claims (9)

1. a semiconductor package, comprise metal framework (1), chip (3), bonding wire (4) and sheet metal (6), it is characterized in that: described chip (3) is positioned on metal framework (1), the pin of bonding wire (4) connection metal framework (1) and chip (3), sheet metal (6) is positioned on chip (3).
2. semiconductor package as claimed in claim 1, it is characterized in that, the height of pin of metal framework (1) is greater than the thickness of chip.
3. semiconductor package as claimed in claim 1, is characterized in that, be provided with scaling powder or adhesive between described chip (3) back side and metal framework (1).
4. semiconductor package as claimed in claim 1, is characterized in that, the pin of described metal framework (1) is connected by bonding wire (4) with the gate pole in chip (3) front.
5. semiconductor package as claimed in claim 1, it is characterized in that, the front of described chip (3) and metal framework (1) is provided with scaling powder.
6. semiconductor package as claimed in claim 1, it is characterized in that, the position that described sheet metal (6) is placed is corresponding with the position of metal framework (1), on the pin covering described chip (3) front and described metal framework (1).
7. semiconductor package as claimed in claim 1, it is characterized in that, the below of described sheet metal (6) is provided with strong dielectric material.
8. semiconductor package as claimed in claim 1, it is characterized in that, described sheet metal (6) is connected with chip (3) by scaling powder (2) described metal framework (1).
9. semiconductor package as claimed in claim 1, it is characterized in that, the shape of described sheet metal (6) is tabular.
CN201520475374.9U 2015-06-30 2015-06-30 Semiconductor encapsulation structure Active CN204809212U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039384A (en) * 2017-04-29 2017-08-11 深圳市劲阳电子有限公司 A kind of SMD element
CN109979825A (en) * 2017-12-15 2019-07-05 胡志良 The circuit element production method of array batch potted element crystal grain

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039384A (en) * 2017-04-29 2017-08-11 深圳市劲阳电子有限公司 A kind of SMD element
CN109979825A (en) * 2017-12-15 2019-07-05 胡志良 The circuit element production method of array batch potted element crystal grain

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