JP2007300088A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2007300088A5 JP2007300088A5 JP2007104458A JP2007104458A JP2007300088A5 JP 2007300088 A5 JP2007300088 A5 JP 2007300088A5 JP 2007104458 A JP2007104458 A JP 2007104458A JP 2007104458 A JP2007104458 A JP 2007104458A JP 2007300088 A5 JP2007300088 A5 JP 2007300088A5
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- lead frame
- planar
- raised features
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Claims (13)
リードフレームを画定する第一の金属層を設ける工程;
リードフレームの複数の***した形体を画定する平面の第二の金属層を設ける工程;および
該第一の金属層を該第二の金属層に接合する工程、
ここで、該平面の第二の金属層をパターン付けして、パッケージ中の二つのダイを接続するトレースとしての該複数の***した形体を形成し、かつ該複数の***した形体は相互に分離されかつパッケージ中の二つのダイの両方に接触している***した形体は一つもない、前記方法。 A method for producing a lead frame for a semiconductor device package, comprising the following steps:
Providing a first metal layer defining a lead frame;
Providing a planar second metal layer defining a plurality of raised features of a lead frame; and joining the first metal layer to the second metal layer ;
Here, the planar second metal layer is patterned to form the plurality of raised features as traces connecting two dies in the package, and the plurality of raised features are separated from one another. The method as described above, wherein no raised features are in contact with both of the two dies in the package .
該第一の金属層に接合され、該リードフレームの複数の***した形体を画定する平面の第二の金属層とを含み、
該複数の***した形態は、パッケージ中の二つのダイを接続する導電トレースを含み、かつ該複数の***した形体は相互に分離されかつパッケージ中の二つのダイの両方に接触している***した形体は一つもない、
半導体素子パッケージのためのリードフレーム。 A first metal layer defining a lead frame;
A planar second metal layer bonded to the first metal layer and defining a plurality of raised features of the lead frame;
The plurality of raised features includes conductive traces connecting two dies in the package, and the plurality of raised features are separated from each other and are in contact with both of the two dies in the package There is no form,
Lead frame for semiconductor device package.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/416,994 US20070130759A1 (en) | 2005-06-15 | 2006-05-02 | Semiconductor device package leadframe formed from multiple metal layers |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007300088A JP2007300088A (en) | 2007-11-15 |
JP2007300088A5 true JP2007300088A5 (en) | 2011-06-23 |
Family
ID=38769289
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007104458A Pending JP2007300088A (en) | 2006-05-02 | 2007-04-12 | Semiconductor device package lead frame formed with a plurality of metal layers |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2007300088A (en) |
CN (1) | CN101068005B (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101521164B (en) * | 2008-02-26 | 2011-01-05 | 上海凯虹科技电子有限公司 | Lead-bonding chip-scale packaging method |
US8309400B2 (en) * | 2010-10-15 | 2012-11-13 | Advanced Semiconductor Engineering, Inc. | Leadframe package structure and manufacturing method thereof |
CN103928431B (en) * | 2012-10-31 | 2017-03-01 | 矽力杰半导体技术(杭州)有限公司 | A kind of flip-chip packaged device |
CN102915988A (en) * | 2012-10-31 | 2013-02-06 | 矽力杰半导体技术(杭州)有限公司 | Lead frame and flip chip packaging device using same |
CN103594448A (en) * | 2013-11-15 | 2014-02-19 | 杰群电子科技(东莞)有限公司 | Lead frame |
CN110524891A (en) * | 2018-05-24 | 2019-12-03 | 本田技研工业株式会社 | Continuous ultrasonic increasing material manufacturing |
US11298775B2 (en) | 2018-05-24 | 2022-04-12 | Honda Motor Co., Ltd. | Continuous ultrasonic additive manufacturing |
JP7071631B2 (en) | 2018-06-25 | 2022-05-19 | 日亜化学工業株式会社 | Package, light emitting device and each manufacturing method |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2582013B2 (en) * | 1991-02-08 | 1997-02-19 | 株式会社東芝 | Resin-sealed semiconductor device and method of manufacturing the same |
CN1449583A (en) * | 2000-07-25 | 2003-10-15 | Ssi株式会社 | Plastic package base, air cavity type package and their manufacturing methods |
JP2004281887A (en) * | 2003-03-18 | 2004-10-07 | Himeji Toshiba Ep Corp | Lead frame and electronic parts using the same |
-
2007
- 2007-04-09 CN CN 200710090879 patent/CN101068005B/en active Active
- 2007-04-12 JP JP2007104458A patent/JP2007300088A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2007300088A5 (en) | ||
JP4294161B2 (en) | Stack package and manufacturing method thereof | |
JP2005191240A (en) | Semiconductor device and method for manufacturing the same | |
JP2007507108A5 (en) | ||
JP2009534869A (en) | Semiconductor die package including multiple die and common node structure | |
JP2007005800A5 (en) | ||
TWM382576U (en) | Leadless integrated circuit package having high density contacts | |
JP2014220439A5 (en) | ||
JP2006261485A5 (en) | ||
JP2014515187A5 (en) | ||
US20070130759A1 (en) | Semiconductor device package leadframe formed from multiple metal layers | |
CN106783792A (en) | There is a kind of plastic-sealed body lateral leads side to climb the encapsulating structure of tin performance | |
KR20170086828A (en) | Clip -bonded semiconductor chip package using metal bump and the manufacturing method thereof | |
JP2010171181A5 (en) | ||
JP2008277751A5 (en) | ||
TWI506753B (en) | Coreless package structure and method for manufacturing same | |
JP2007300088A (en) | Semiconductor device package lead frame formed with a plurality of metal layers | |
JP2004363365A (en) | Semiconductor device and manufacturing method thereof | |
CN105140205A (en) | Double-side heat dissipation semiconductor POP (Package on Package) packaging structure | |
JP2010118577A (en) | Resin encapsulated semiconductor device and method of manufacturing the same | |
JP2006279088A (en) | Method for manufacturing semiconductor device | |
JP2010040955A5 (en) | ||
JP4732138B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2007134585A5 (en) | ||
JP2010050288A (en) | Resin-sealed semiconductor device and method of manufacturing the same |