JP2007300088A5 - - Google Patents

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Publication number
JP2007300088A5
JP2007300088A5 JP2007104458A JP2007104458A JP2007300088A5 JP 2007300088 A5 JP2007300088 A5 JP 2007300088A5 JP 2007104458 A JP2007104458 A JP 2007104458A JP 2007104458 A JP2007104458 A JP 2007104458A JP 2007300088 A5 JP2007300088 A5 JP 2007300088A5
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JP
Japan
Prior art keywords
metal layer
lead frame
planar
raised features
package
Prior art date
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Pending
Application number
JP2007104458A
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Japanese (ja)
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JP2007300088A (en
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Publication date
Priority claimed from US11/416,994 external-priority patent/US20070130759A1/en
Application filed filed Critical
Publication of JP2007300088A publication Critical patent/JP2007300088A/en
Publication of JP2007300088A5 publication Critical patent/JP2007300088A5/ja
Pending legal-status Critical Current

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Claims (13)

以下の工程を含む、半導体素子パッケージのためのリードフレームを作製する方法であって:
リードフレームを画定する第一の金属層を設ける工程;
リードフレームの複数の***した形体を画定する平面の第二の金属層を設ける工程;および
該第一の金属層を該第二の金属層に接合する工程
ここで、該平面の第二の金属層をパターン付けして、パッケージ中の二つのダイを接続するトレースとしての該複数の***した形体を形成し、かつ該複数の***した形体は相互に分離されかつパッケージ中の二つのダイの両方に接触している***した形体は一つもない、前記方法
A method for producing a lead frame for a semiconductor device package, comprising the following steps:
Providing a first metal layer defining a lead frame;
Providing a planar second metal layer defining a plurality of raised features of a lead frame; and joining the first metal layer to the second metal layer ;
Here, the planar second metal layer is patterned to form the plurality of raised features as traces connecting two dies in the package, and the plurality of raised features are separated from one another. The method as described above, wherein no raised features are in contact with both of the two dies in the package .
超音波溶接によって第一の金属層を平面の第二の金属層に接合する、請求項1記載の方法。 2. The method of claim 1, wherein the first metal layer is joined to the planar second metal layer by ultrasonic welding. エポキシ樹脂によって第一の金属層を平面の第二の金属層に接合する、請求項1記載の方法。 2. The method of claim 1, wherein the first metal layer is joined to the planar second metal layer by an epoxy resin. はんだによって第一の金属層を平面の第二の金属層に接合する、請求項1記載の方法。 The method of claim 1, wherein the first metal layer is joined to the planar second metal layer by solder. 平面の第二の金属層をパターン付けして、DPAK、D2PAK、TO-220、TO-247、SOT-223、TSSOP-x、SO-x、SSOP-x、TQFP、SE70-8、TSOP-8およびTSOP12からなる群より選択されるパワータイプパッケージのダイパッド上に***した形体を形成する、請求項1記載の方法。 Pattern flat second metal layer, DPAK, D2PAK, TO-220, TO-247, SOT-223, TSSOP-x, SO-x, SSOP-x, TQFP, SE70-8, TSOP-8 The method of claim 1, wherein the raised features are formed on a die pad of a power type package selected from the group consisting of: and TSOP12. 平面の第二の金属層をパターン付けして、リードをプラスチックの本体内に固着するための段としての***した形体を形成する、請求項1記載の方法。 The method of claim 1, wherein the planar second metal layer is patterned to form a raised feature as a step for securing the lead within the plastic body. 第二の金属層をパターン付けして、パッケージの周囲にダイ接点を接続分布させるトレースとしての***した形体を形成する、請求項1記載の方法。   The method of claim 1, wherein the second metal layer is patterned to form raised features as traces that connect and distribute the die contacts around the package. リードフレームを画定する第一の金属層と、
該第一の金属層に接合され、該リードフレームの複数の***した形体を画定する平面の第二の金属層とを含み、
該複数の***した形態は、パッケージ中の二つのダイを接続する導電トレースを含み、かつ該複数の***した形体は相互に分離されかつパッケージ中の二つのダイの両方に接触している***した形体は一つもない、
半導体素子パッケージのためのリードフレーム。
A first metal layer defining a lead frame;
A planar second metal layer bonded to the first metal layer and defining a plurality of raised features of the lead frame;
The plurality of raised features includes conductive traces connecting two dies in the package, and the plurality of raised features are separated from each other and are in contact with both of the two dies in the package There is no form,
Lead frame for semiconductor device package.
平面の第二の金属層が第一の金属層に溶接されている、請求項8記載のリードフレーム。 9. The lead frame of claim 8 , wherein the planar second metal layer is welded to the first metal layer. 第一の金属層と平面の第二の金属層との間にエポキシ樹脂をさらに含む、請求項8記載のリードフレーム。 9. The lead frame according to claim 8 , further comprising an epoxy resin between the first metal layer and the planar second metal layer. 第一の金属層と平面の第二の金属層との間にはんだをさらに含む、請求項8記載のリードフレーム。 9. The lead frame of claim 8 , further comprising solder between the first metal layer and the planar second metal layer. ***した形体が、リードをプラスチックのパッケージ本体内に固着する段を含む、請求項8記載のリードフレーム。 9. The lead frame of claim 8 , wherein the raised features include steps for securing the leads within the plastic package body. ***した形体が、パッケージの周囲にダイ接点を分布させる導電トレースを含む、請求項8記載のリードフレーム。 9. The lead frame of claim 8 , wherein the raised features include conductive traces that distribute die contacts around the package.
JP2007104458A 2006-05-02 2007-04-12 Semiconductor device package lead frame formed with a plurality of metal layers Pending JP2007300088A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/416,994 US20070130759A1 (en) 2005-06-15 2006-05-02 Semiconductor device package leadframe formed from multiple metal layers

Publications (2)

Publication Number Publication Date
JP2007300088A JP2007300088A (en) 2007-11-15
JP2007300088A5 true JP2007300088A5 (en) 2011-06-23

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Family Applications (1)

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JP2007104458A Pending JP2007300088A (en) 2006-05-02 2007-04-12 Semiconductor device package lead frame formed with a plurality of metal layers

Country Status (2)

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JP (1) JP2007300088A (en)
CN (1) CN101068005B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101521164B (en) * 2008-02-26 2011-01-05 上海凯虹科技电子有限公司 Lead-bonding chip-scale packaging method
US8309400B2 (en) * 2010-10-15 2012-11-13 Advanced Semiconductor Engineering, Inc. Leadframe package structure and manufacturing method thereof
CN103928431B (en) * 2012-10-31 2017-03-01 矽力杰半导体技术(杭州)有限公司 A kind of flip-chip packaged device
CN102915988A (en) * 2012-10-31 2013-02-06 矽力杰半导体技术(杭州)有限公司 Lead frame and flip chip packaging device using same
CN103594448A (en) * 2013-11-15 2014-02-19 杰群电子科技(东莞)有限公司 Lead frame
CN110524891A (en) * 2018-05-24 2019-12-03 本田技研工业株式会社 Continuous ultrasonic increasing material manufacturing
US11298775B2 (en) 2018-05-24 2022-04-12 Honda Motor Co., Ltd. Continuous ultrasonic additive manufacturing
JP7071631B2 (en) 2018-06-25 2022-05-19 日亜化学工業株式会社 Package, light emitting device and each manufacturing method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2582013B2 (en) * 1991-02-08 1997-02-19 株式会社東芝 Resin-sealed semiconductor device and method of manufacturing the same
CN1449583A (en) * 2000-07-25 2003-10-15 Ssi株式会社 Plastic package base, air cavity type package and their manufacturing methods
JP2004281887A (en) * 2003-03-18 2004-10-07 Himeji Toshiba Ep Corp Lead frame and electronic parts using the same

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