CN204731339U - The phase error proving installation of analog input formula merge cells - Google Patents

Abstract

The utility model discloses a kind of phase error proving installation of analog input formula merge cells, comprise: power source, network interface card, fpga chip, SAR? ADC and CPU, does described power source connect merge cells to be measured, described SAR respectively? ADC and described CPU, described network interface card connects described merge cells to be measured and described fpga chip respectively, does described fpga chip also connect described CPU and described SAR respectively? ADC, described SAR? ADC also connects described CPU.The utility model can complete test under the mode not changing field wiring structure, and do not need the test that has a power failure, test structure is reliable and stable.

Description

The phase error proving installation of analog input formula merge cells

Technical field

The utility model relates to intelligent substation technical field, particularly relates to a kind of phase error proving installation of analog input formula merge cells.

Background technology

Merge cells, as the intelligent apparatus in process layer, is the data source header of whole digital transformer substation, and its precision, reliability, the operation of stability to digital transformer substation serve very important effect.Original merge cells on-the-spot test method needs to disconnect analog input and synchronizing signal, pick-up unit is accessed formation test loop, and change on-the-spot wiring construction, must have a power failure test, had a strong impact on carrying out of test job.

Utility model content

Technical problem to be solved in the utility model is, a kind of phase error proving installation and method of analog input formula merge cells are provided, can complete test under the mode not changing field wiring structure, do not need the test that has a power failure, test structure is reliable and stable.

In order to solve the problems of the technologies described above, the utility model provides a kind of phase error proving installation of analog input formula merge cells, comprising:

Power source, network interface card, fpga chip, SAR ADC and CPU, described power source connects merge cells to be measured, described SAR ADC and described CPU respectively, described network interface card connects described merge cells to be measured and described fpga chip respectively, described fpga chip also connects described CPU and described SAR ADC respectively, and described SAR ADC also connects described CPU.

Implement the utility model, there is following beneficial effect: the test being achieved analog input merge cells phase error under asynchronous condition by the utility model, test can be completed under the mode not changing field wiring structure, do not need the test that has a power failure, test structure is reliable and stable, the phase value jitter error caused by hardware, within 2 points, improves intelligent substation required level of service.

Accompanying drawing explanation

In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the structural representation of an embodiment of the phase error proving installation of the analog input formula merge cells that the utility model provides.

Embodiment

Below in conjunction with the accompanying drawing in the utility model embodiment, be clearly and completely described the technical scheme in the utility model embodiment, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.

Fig. 1 is the structural representation of an embodiment of the phase error proving installation of the analog input formula merge cells that the utility model provides, comprise: power source, network interface card, fpga chip, SAR ADC (gradually-appoximant analog-digital converter) and CPU, power source connects merge cells to be measured, SAR ADC and CPU respectively, network interface card connects merge cells to be measured and fpga chip respectively, fpga chip also connects CPU and SARADC, SAR ADC respectively and also connects CPU.

Principle of work of the present utility model is:

Power source sends analog quantity to merge cells to be measured and SAR ADC.Wherein, power source also can be scene is really load, and the accuracy of precision on whole test of power source does not affect, and analog quantity is voltage, current analog signal specifically.

The analog quantity received is converted to digital message by merge cells to be measured, and is forwarded to CPU by network interface card, fpga chip.Wherein, datagram literary composition specifically IEC61850-9-2 numeral message.Merge cells to be measured sends IEC61850-9-2 numeral message p.s. (with the clock of merge cells inside for benchmark) and sends 4000, and test serial number is from 0 to 3999.Comprise digital message transmission time in message to differ with the analog quantity actual samples moment and be called specified time delay, this time delay is a constant, is worth for N sampling interval duration (N=1,2,3 doubly ...).Generally, this constant is 500, and representative digit amount transmission time differs 500us with the analog quantity actual samples moment.

Fpga chip to the digital message decoding received, and sends sampling pulse signal to SAR ADC, thus realizes synchronized sampling.Therefore, merge cells to be measured with do not need between the present invention to be connected synchronizing signal.Concrete, the fpga chip course of work is: decode to digital message, judge front top guide, the sequence number field of digital message, and according to chip section clock in FPGA, when the sequence number finding previous bag is 3999, after next bag detects front top guide, namely sequence number is the digital message of 0, it is the first digit message that merge cells to be measured sends within a second, obtains the markers of Contemporary Digital message; To SAR ADC transmit band target first sampling pulse signal sometimes, and send follow-up sampling pulse using the sampling interval mean value of digital message as A/D sampling interval, thus realize synchronized sampling.Generally, the sampling interval mean value of digital message is 250us.

SAR ADC samples and analog to digital conversion to analog quantity according to sampling pulse signal, obtains A/D message, and is sent to CPU.

The digital message that CPU sends according to fpga chip and the A/D message that SAR ADC sends calculate the phase error of merge cells to be measured.

Concrete, CPU comprises: Fourier transform module, carries out Fourier transform for the digital message sent fpga chip, obtains digital message phase value; Fourier transform is carried out to the A/D message that SAR ADC sends, obtains A/D message phase value;

Total delay time computing module, for calculating the total delay time of A/D sampling time than the analog output time, wherein, total delay time=specified time delay+transmission delay+A/D samples time delay, in formula, specified time delay represents the moment of merge cells transmission of digital message to be measured and the difference in analog quantity actual samples moment, transmission delay represents from merge cells to be measured and sends digital message, (this delay is fixed constant in delay when obtaining first digit message to fpga chip decoding, can from design verification value at about 0.5us), A/D sample time delay represent SAR ADC sampling time delay (A/D sample time delay be fixed constant, can consult on A/D handbook, for about 10us),

Normalized phase difference modular converter, for total delay time is converted to normalized phase difference, wherein, normalized phase difference=total delay time * (A/D calculated rate)/1000000*360;

Phase error computation module, for obtaining merge cells phase error to be measured according to digital message phase value, A/D message phase value and normalized phase mathematic interpolation, wherein, merge cells phase error to be measured=A/D message phase value-normalized phase difference-digital message phase value.

Implement the utility model, there is following beneficial effect: the test being achieved analog input merge cells phase error under asynchronous condition by the utility model, test can be completed under the mode not changing field wiring structure, do not need the test that has a power failure, test structure is reliable and stable, the phase value jitter error caused by hardware, within 2 points, improves intelligent substation required level of service

It should be noted that, in this article, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or device and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or device.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the device comprising this key element and also there is other identical element.

To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the utility model.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein when not departing from spirit or scope of the present utility model, can realize in other embodiments.Therefore, the utility model can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.

Claims (1)

1. the phase error proving installation of an analog input formula merge cells, it is characterized in that, comprise power source, network interface card, fpga chip, SAR ADC and CPU, described power source connects merge cells to be measured, described SAR ADC and described CPU respectively, described network interface card connects described merge cells to be measured and described fpga chip respectively, described fpga chip also connects described CPU and described SAR ADC respectively, and described SARADC also connects described CPU.