CN204697009U - Adaptive bias circuit in a kind of CMOS linear power amplifier - Google Patents
Adaptive bias circuit in a kind of CMOS linear power amplifier Download PDFInfo
- Publication number
- CN204697009U CN204697009U CN201520489655.XU CN201520489655U CN204697009U CN 204697009 U CN204697009 U CN 204697009U CN 201520489655 U CN201520489655 U CN 201520489655U CN 204697009 U CN204697009 U CN 204697009U
- Authority
- CN
- China
- Prior art keywords
- field effect
- effect transistor
- circuit
- output
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Amplifiers (AREA)
Abstract
The utility model discloses the adaptive bias circuit in a kind of CMOS linear power amplifier, comprise inverter amplifying circuit, distortion amplifying circuit, see-saw circuit and voltage-current converter circuit; The input of described inverter amplifying circuit is the input of described biasing circuit, the output of described inverter amplifying circuit connects the input of described distortion amplifying circuit, the output of described distortion amplifying circuit connects the input of described see-saw circuit, and the output of described see-saw circuit connects described voltage-current converter circuit.Under adaptive-biased technology of the present utility model well solves unlike signal input, to the compromise of power amplifier between stand-by power consumption and the linearity, different offset signals is produced under different input range, promote to be biased under large-signal and improve the linear of power amplifier, reduce biased under small-signal, when ensureing linear, reduce DC power as far as possible.
Description
Technical field
The utility model relates to power amplifier, is specifically related to the adaptive bias circuit in a kind of CMOS linear power amplifier.
Background technology
Current CMOS technology is obtained for and applies widely in digital circuit, mixed signal even radio circuit, and integrated power amplifier becomes the biggest obstacle that CMOS IC faces.Reason is, first the characteristic of cmos device, and especially robustness will be substantially weaker than the GaAs that main flow power amplifier of cell phone adopts, the techniques such as SiGe, and along with the reduction of size, this defect becomes outstanding all the more.Comprising the factors such as grid oxygen breakdown potential is forced down, Punchthrough voltage is little, hot carrier's effect is obvious, to cause cmos device Performance And Reliability when tackling big current, large voltage poor.
Traditional CMOS power amplifier (CMOS PA) is relating in Robustness Design, usual employing superposes multiple Cascode and even adopts the modes such as Stacked to increase the reliability of circuit, but when load mismatch is comparatively serious, still there is risk in these methods.Secondly, also comparatively traditional handicraft device is poor in linear characteristic for cmos device, therefore often needs to rely on linearization technique to correct.
Utility model content
In order to solve problems of the prior art, the utility model discloses the adaptive bias circuit in a kind of CMOS linear power amplifier.
The technical solution of the utility model is as follows:
An adaptive bias circuit in CMOS linear power amplifier, comprises inverter amplifying circuit, distortion amplifying circuit, see-saw circuit and voltage-current converter circuit; The input of described inverter amplifying circuit is the input of described biasing circuit, the output of described inverter amplifying circuit connects the input of described distortion amplifying circuit, the output of described distortion amplifying circuit connects the input of described see-saw circuit, and the output of described see-saw circuit connects described voltage-current converter circuit; Also comprise the 7th field effect transistor, described 7th field effect transistor is P channel-type, and the output of described voltage-current converter circuit connects the gate leve of described 7th field effect transistor, and the drain electrode of described 7th field effect transistor is as the output of described offset signal.
Its further technical scheme is: described inverter amplifying circuit comprises the first field effect transistor, the second field effect transistor, variable resistor; Described first field effect transistor is N channel-type, described second field effect transistor is P channel-type, the drain electrode of described first field effect transistor is connected with the drain electrode of the second field effect transistor, the gate leve of described first field effect transistor is connected with the gate leve of the second field effect transistor, described variable resistor one end connects the gate leve of described first field effect transistor, and the other end connects the drain electrode of the first field effect transistor; The gate leve of described first field effect transistor is the input of inverter amplifying circuit, drains as the output of inverter amplifying circuit (1).
Its further technical scheme is: described distortion amplifying circuit comprises the 3rd field effect transistor for N channel-type and the 4th field effect transistor; The gate leve of described 3rd field effect transistor connects the output of described inverter amplifying circuit; The drain electrode of described 3rd field effect transistor connects the source electrode of the 4th field effect transistor, and its common port is as the output of described distortion amplifying circuit.
Its further technical scheme is: described see-saw circuit comprises the 5th field effect transistor of P channel-type, the first resistance and the first electric capacity, described first resistance and the first Capacitance parallel connection, and one end of described first resistance connects the drain electrode of described 5th field effect transistor; The common port of described first resistance and described 5th field effect transistor is the output of described see-saw circuit.
Its further technical scheme is: described voltage-current converter circuit comprises error amplifier, the second resistance, the second electric capacity and the 6th field effect transistor; The drain electrode of described 6th field effect transistor connects one end of the second resistance, the other end ground connection of the second resistance; The positive input of described error amplifier connects the common port of described 6th field effect transistor and the second resistance, and the output of described see-saw circuit connects the negative sense output of described error amplifier; The output of described error amplifier connects the gate leve of described 7th field effect transistor.
Advantageous Effects of the present utility model is:
1, the utility model adopts and dynamically follows the tracks of output voltage signal amplitude, and extracts relevant information and adjust biasing circuit dynamically, makes it can the situation of self-adapting load mismatch.
2, the utility model adopts the dynamic change following the tracks of output current simultaneously, in real time the operating current of adjustment power amplifier, thus can fundamentally improve the reliability of CMOS power amplifier under each mal-condition.
3, the utility model adopts dynamic tracking signal amplitude, and then adjust biasing circuit accordingly to adapt to current signal amplitude demand, secondary analog linearization device or harmonic suppression network, improve the linearity and the efficiency of power amplifier simultaneously simultaneously.
To sum up, under adaptive-biased technology of the present utility model well solves unlike signal input, to the compromise of power amplifier between stand-by power consumption and the linearity, different offset signals is produced under different input range, promote to be biased under large-signal and improve the linear of power amplifier, reduce biased under small-signal, when ensureing linear, reduce DC power as far as possible.
Accompanying drawing explanation
Fig. 1 is the utility model schematic diagram.
Fig. 2 shows the impact on power amplifier gain under different inverter gain.
Fig. 3 shows the operating current for power amplifier corresponding under varying input signal amplitude.
Fig. 4 shows band adaptive bias circuit and the change in gain not with adaptive bias circuit
Embodiment
Fig. 1 is the utility model schematic diagram.The input that the utility model comprises inverter amplifying circuit 1, distortion amplifying circuit 2, see-saw circuit 3 and voltage-current converter circuit 4. inverter amplifying circuit 1 is the input of biasing circuit, the output of inverter amplifying circuit 1 connects the input of distortion amplifying circuit 2, the output of distortion amplifying circuit 2 connects the input of see-saw circuit 3, and the output of see-saw circuit 3 connects voltage-current converter circuit 4.Also comprise field effect transistor M7, field effect transistor M7 is P channel-type, and the output of voltage-current converter circuit 4 connects the gate leve of field effect transistor M7, and the drain electrode of field effect transistor M7 is as the output of biasing circuit.
Inverter amplifying circuit 1 comprises field effect transistor M1, field effect transistor M2, variable resistor R0.Field effect transistor M1 is N channel-type, field effect transistor M2 is P channel-type, the drain electrode of field effect transistor M1 is connected with the drain electrode of field effect transistor M2, the gate leve of field effect transistor M1 is connected with the gate leve of field effect transistor M2, variable resistor R0 one end connects the gate leve of field effect transistor M1, and the other end connects the drain electrode of field effect transistor M1.The gate leve of field effect transistor M1 is the input of inverter amplifying circuit 1, drains as the output of inverter amplifying circuit 1.By regulating the size of variable resistor R0, changing the gain of amplifier, just can regulate the starting point of adaptive bias circuit.
Distortion amplifying circuit 2 comprises field effect transistor M3 for N channel-type and field effect transistor M4.The gate leve of field effect transistor M3 connects the output of inverter amplifying circuit 1, and the drain electrode of field effect transistor M3 connects the source electrode of field effect transistor M4, and its common port is as the output of distortion amplifying circuit 2.Field effect transistor M3 and field effect transistor M4 constitutes the fixing distortion amplifying circuit 2 of a gain, namely under small signal model, the average voltage of circuit node b is relatively fixing, and under large-signal, the distortion that circuit node b produces declines causing the average voltage of circuit node B point.
See-saw circuit 3 comprises field effect transistor M5, resistance R1 and the electric capacity C1 of P channel-type.Resistance R1 and electric capacity C1 is in parallel, and one end of resistance R1 connects the drain electrode of field effect transistor M5, and the common port of resistance R1 and field effect transistor M5 is the output of see-saw circuit 3.The see-saw circuit 3 of field effect transistor M5 and resistance R1, electric capacity C1 composition has filter action, after distortion amplifying circuit, the average level of circuit node 2 increases along with signal and reduces, thus the average level of circuit node c can become large thereupon, and after passing through the network formed as resistance R1 and the electric capacity C1 of filter action, radiofrequency signal can be filtered into an approximate DC signal.
Voltage-current converter circuit 4 comprises error amplifier A1, resistance R2, electric capacity C2 and field effect transistor M6.One end of the drain electrode contact resistance R2 of field effect transistor M6, the other end ground connection of resistance R2, the positive input of error amplifier A1 connects the common port of field effect transistor M6 and resistance R2, the output of see-saw circuit 3 connects the negative sense output of error amplifier A1, and the output of error amplifier A1 connects the gate leve of field effect transistor M7.The change in voltage of the voltage meeting follow circuit node c of the circuit node d in voltage-current converter circuit 4, and convert corresponding electric current to by resistance R2, this electric current is supplied to biasing circuit by being replicated out as the field effect transistor M7 of mirror image pipe.Wherein electric capacity C2 is the building-out capacitor of voltage-current converter circuit 4.
Fig. 2 affects schematic diagram on power amplifier gain under different inverter gain, if inverter gain is high, so the startup scope of adaptive bias circuit just early, is embodied in the gain of power amplifier, be exactly gain lifting ahead of time, as shown in gain1 curve; If inverter gain reduction, it is more late that the curve that so gain promotes occurs, as shown in gain3 curve.Come institute for power amplifier, in advance and to delay be not best selection, the interval that therefore gain promotes needs to carry out adjustable, as being adjusted to gain2 curve place.
Fig. 3 and Fig. 4 compares the contrast adding biasing circuit described in the utility model and do not use biasing circuit described in the utility model.
Fig. 3 is the operating current schematic diagram of power amplifier corresponding in small-signal situation, wherein w/i adaptivebias curve is the use of the situation of biasing circuit described in the utility model, and w/o adaptive bias curve is the situation not using biasing circuit described in the utility model.In small-signal situation, the operating current of power amplifier is approximately quiescent current, visible, and do not have the current curve of adaptive-biased technology to be far longer than the electric current adopting adaptive bias circuit, like this under small signal model, power amplifier electric current is intangibly wasted.
Fig. 4 is the change in gain schematic diagram of circuit, and wherein w/i adaptive bias curve is the use of the situation of biasing circuit described in the utility model, and w/o adaptive bias curve is the situation not using biasing circuit described in the utility model.W/o adaptive bias curve is more oblique curve, thus the important parameter of power amplifier exports 1dB compression point deviation, and adopt the gain curve of adaptive-biased technology can become very level and smooth, thus obtain well output 1dB compression curve, that is to say that AM-AM distortion can improve, the AM-PM curve simultaneously obtained actually by adaptive technique also can improve thereupon, thus also can improve significantly to the linearity of power amplifier under large-signal.
Above-described is only preferred implementation of the present utility model, and the utility model is not limited to above embodiment.Be appreciated that the oher improvements and changes that those skilled in the art directly derive or associate under the prerequisite not departing from spirit of the present utility model and design, all should think and be included within protection range of the present utility model.
Claims (5)
1. the adaptive bias circuit in CMOS linear power amplifier, is characterized in that: comprise inverter amplifying circuit (1), distortion amplifying circuit (2), see-saw circuit (3) and voltage-current converter circuit (4); The input of described inverter amplifying circuit (1) is the input of described biasing circuit, the output of described inverter amplifying circuit (1) connects the input of described distortion amplifying circuit (2), the output of described distortion amplifying circuit (2) connects the input of described see-saw circuit (3), and the output of described see-saw circuit (3) connects described voltage-current converter circuit (4); Also comprise the 7th field effect transistor (M7), described 7th field effect transistor (M7) is P channel-type, the output of described voltage-current converter circuit (4) connects the gate leve of described 7th field effect transistor (M7), and the drain electrode of described 7th field effect transistor (M7) is as the output of described biasing circuit.
2. the adaptive bias circuit in CMOS linear power amplifier as claimed in claim 1, is characterized in that: described inverter amplifying circuit (1) comprises the first field effect transistor (M1), the second field effect transistor (M2), variable resistor (R0); Described first field effect transistor (M1) is N channel-type, described second field effect transistor (M2) is P channel-type, the drain electrode of described first field effect transistor (M1) is connected with the drain electrode of the second field effect transistor (M2), the gate leve of described first field effect transistor (M1) is connected with the gate leve of the second field effect transistor (M2), described variable resistor (R0) one end connects the gate leve of described first field effect transistor (M1), and the other end connects the drain electrode of the first field effect transistor (M1); The gate leve of described first field effect transistor (M1) is the input of inverter amplifying circuit (1), drains as the output of inverter amplifying circuit (1).
3. the adaptive bias circuit in CMOS linear power amplifier as claimed in claim 1, is characterized in that: described distortion amplifying circuit (2) comprises the 3rd field effect transistor (M3) for N channel-type and the 4th field effect transistor (M4); The gate leve of described 3rd field effect transistor (M3) connects the output of described inverter amplifying circuit (1); The drain electrode of described 3rd field effect transistor (M3) connects the source electrode of the 4th field effect transistor (M4), and its common port is as the output of described distortion amplifying circuit (2).
4. the adaptive bias circuit in CMOS linear power amplifier as claimed in claim 1, it is characterized in that: described see-saw circuit (3) comprises the 5th field effect transistor (M5) of P channel-type, the first resistance (R1) and the first electric capacity (C1), described first resistance (R1) and the first electric capacity (C1) parallel connection, one end of described first resistance (R1) connects the drain electrode of described 5th field effect transistor (M5); The common port of described first resistance (R1) and described 5th field effect transistor (M5) is the output of described see-saw circuit (3).
5. the adaptive bias circuit in CMOS linear power amplifier as claimed in claim 1, is characterized in that: described voltage-current converter circuit (4) comprises error amplifier (A1), the second resistance (R2), the second electric capacity (C2) and the 6th field effect transistor (M6); The drain electrode of described 6th field effect transistor (M6) connects one end of the second resistance (R2), the other end ground connection of the second resistance (R2); The positive input of described error amplifier (A1) connects the common port of described 6th field effect transistor (M6) and the second resistance (R2), and the output of described see-saw circuit (3) connects the negative sense output of described error amplifier (A1); The output of described error amplifier (A1) connects the gate leve of described 7th field effect transistor (M7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520489655.XU CN204697009U (en) | 2015-07-08 | 2015-07-08 | Adaptive bias circuit in a kind of CMOS linear power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520489655.XU CN204697009U (en) | 2015-07-08 | 2015-07-08 | Adaptive bias circuit in a kind of CMOS linear power amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204697009U true CN204697009U (en) | 2015-10-07 |
Family
ID=54237258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520489655.XU Expired - Fee Related CN204697009U (en) | 2015-07-08 | 2015-07-08 | Adaptive bias circuit in a kind of CMOS linear power amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204697009U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108155875A (en) * | 2016-12-02 | 2018-06-12 | 瑞昱半导体股份有限公司 | Power amplifier |
-
2015
- 2015-07-08 CN CN201520489655.XU patent/CN204697009U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108155875A (en) * | 2016-12-02 | 2018-06-12 | 瑞昱半导体股份有限公司 | Power amplifier |
| CN108155875B (en) * | 2016-12-02 | 2021-05-25 | 瑞昱半导体股份有限公司 | Power amplifier |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106571780B (en) | A kind of adaptive-biased radio-frequency power amplifier | |
| CN106452377B (en) | A kind of radio-frequency power amplifier of adaptive equalization | |
| US20150188500A1 (en) | Power amplifier | |
| CN104158496B (en) | Passive frequency mixer at duty ratio of 25% with positive feedback transimpedance amplification stage as load | |
| CN104167994A (en) | Amplitude and phase tunable type pre-distortion linearizer | |
| CN103780212A (en) | Operational amplifiers, level switching circuit and programmable gain amplifier | |
| CN104242830B (en) | Reconfigurable ultra-wideband low-noise amplifier based on active inductance | |
| CN103956920A (en) | Static threshold eliminating and dynamic threshold eliminating combined type voltage-doubler rectifier | |
| CN114285378B (en) | Power amplification circuit based on envelope tracking technology and Doherty framework and design method thereof | |
| Kang et al. | Study on dynamic body bias controls of RF CMOS cascode power amplifier | |
| CN104184460A (en) | Radio frequency load driving circuit | |
| CN204697009U (en) | Adaptive bias circuit in a kind of CMOS linear power amplifier | |
| CN105048971B (en) | High efficiency Doherty power amplifier implementation method based on switched resonance structure | |
| US11777454B1 (en) | Bias circuit for radio frequency power amplifier | |
| CN103107791B (en) | Gain linear variable gain amplifier with constant bandwidth | |
| CN204361999U (en) | A kind of wide-band amplifier circuit of darlington structure | |
| US9837964B2 (en) | Amplifier system and device | |
| CN108599730B (en) | High-efficiency F-type stacked power amplifier based on compact resonator | |
| Kim et al. | A feedback technique to compensate for AM-PM distortion in linear CMOS class-F power amplifier | |
| CN202374224U (en) | Variable gain self-adaption bias power amplifier based on common-mode feedback | |
| CN106559050B (en) | A kind of differential amplifier circuit of self-adapting load | |
| CN104539247A (en) | Wideband amplifier circuit of Darlington structure | |
| CN110829984B (en) | High-linearity power amplifier | |
| CN211791445U (en) | Self-adaptive bias circuit for power amplifier chip | |
| CN110768630B (en) | Compensation circuit for amplitude modulation to amplitude modulation of radio frequency power amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151007 Termination date: 20200708 |