CN204652316U - Low voltage difference amplifier, error amplifier and amplifying circuit - Google Patents
Low voltage difference amplifier, error amplifier and amplifying circuit Download PDFInfo
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- CN204652316U CN204652316U CN201420852824.7U CN201420852824U CN204652316U CN 204652316 U CN204652316 U CN 204652316U CN 201420852824 U CN201420852824 U CN 201420852824U CN 204652316 U CN204652316 U CN 204652316U
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Abstract
Disclose a kind of low voltage difference amplifier, error amplifier and amplifying circuit.Low voltage difference amplifier can comprise the error amplifier with first and second inputs of being coupled to reference signal and feedback signal respectively.Error amplifier can be configured to generate the first and second error signals respectively in the first and second outputs, and wherein the first and second error signals are based on the difference between reference signal and feedback signal.Fill with level can be coupled to the first output and be configured to generate based on the first error signal fill with electric current.Draw level can be coupled to the second output and be configured to generate based on the second error signal draw electric current.Output node can be coupled fill with electric current and draw electric current.
Description
Technical field
The disclosure relates to amplifier region, and, more especially, relate to the low voltage difference amplifier region comprising error amplifier.
Background technology
In the last few years, the hand-held battery powered electronic device of such as panel computer and smart mobile phone and so on was widely used, and its utilization rate continues soaring, and regularly adds additional function.
The voltage regulator of a kind of common type used in this electronic equipment is called as low voltage difference (LDO) adjuster, and it with little input operation with output difference component voltage, and can provide high-grade efficiency and heat radiation.Typical ldo regulator comprises error amplifier, this error amplifier controlling filed effect transistor (FET) with cause FET to fill with or draw (sinkor source) from or go to the electric current of output node.An input receiving feedback signals of error amplifier, and another input receives reference voltage.Error amplifier controls power fet to keep constant output voltage.
This voltage regulator may be used for for the various parts of electronic device such as SOC (system on a chip) and analog to digital converter and so on are powered.For some this parts, expect that the electric current of output node can both be filled with and draw from or go to ldo regulator to produce the signal outputting to the pinpoint accuracy of output node.In addition, anticipation error amplifier has low-power to be needed and low biased DC characteristic, and has the AC characteristic of high-gain.Therefore, be desirably in this scope and have further raising.
Utility model content
There is provided the utility model content for introducing the design picked out will further described in embodiment hereafter.The utility model content does not really want key or the substantive characteristics of the purport required by identification, neither be used for the scope of the purport helped required by restriction.
An aspect is for low voltage difference amplifier.Low voltage difference amplifier can comprise error amplifier, and this error amplifier has first and second inputs of being coupled to reference signal and feedback signal respectively.Error amplifier can be configured to generate the first and second error signals respectively in the first and second outputs, and wherein the first and second error signals are based on the difference between reference signal and feedback signal.Fill with level can be coupled to the first output and be configured to generate based on the first error signal fill with electric current.Draw level can be coupled to the second output and be configured to generate based on the second error signal draw electric current.Output node can be coupled to receive and fills with electric current and draw electric current.
In an embodiment of the invention, low voltage difference amplifier also comprises the load of being coupled to described output node; Wherein said filling level is configured in zero threshold value, export described filling electric current through the electric current of described load based on described feedback signal instruction; And wherein said draw level be configured to generate in zero threshold value through the electric current of overload based on the instruction of described feedback signal described in draw electric current.
In an embodiment of the invention, low voltage difference amplifier also comprises the load of being coupled to described output node; And it is negative and generate described filling electric current that wherein said filling level to be configured to based on the instruction of described feedback signal through the electric current of described load.
In an embodiment of the invention, low voltage difference amplifier also comprises the load of being coupled to described output node; And wherein said level of drawing is configured to indicate the electric current through described load to be positive based on described feedback signal and draw electric current described in generation.
In an embodiment of the invention, described filling level comprises: transistor, have and be coupled to described first output to receive the control terminal of described first error signal, the first conducting terminal being coupled to the first power supply node and the second conducting terminal, described transistor is configured to generate electric current based on described first error signal from its second conducting terminal; Fill with current mirror, be coupled to described second conducting terminal of described transistor and described output node, and be configured to be the described filling electric current being applied to described output node by described current mirror.
In an embodiment of the invention, described level of drawing comprises: transistor, have and be coupled to described second output to receive the control terminal of described second error signal, the first conducting terminal being coupled to second source node and the second conducting terminal, described transistor is configured to generate electric current based on described second error signal from its second conducting terminal; Draw current mirror, be coupled to described second conducting terminal of described transistor and described output node, and be configured to described current mirror to draw electric current to described output node as described.
In an embodiment of the invention, low voltage difference amplifier also comprise be coupling in described first export with described second input between the first feedback network, be coupling in described second export with described second input between the second feedback network and be coupling in described output node and described second input between the 3rd feedback network.
In an embodiment of the invention, described error amplifier comprises: differential input stage, comprise described first input and described second to input, described differential input stage is configured to based on the difference between the described reference signal of described first input and the described feedback signal of described second input and generates comparison signal; At least one gain stage, is coupled to the input of described differential input stage and is configured to amplify described comparison signal; Differential output stage, is coupled at least one gain stage described and is configured to based on described comparison signal and exports described first error signal and described second error signal.
In an embodiment of the invention, at least one gain stage described comprises the first gain stage of the described input of being coupled to described differential input stage, and is coupled to the second gain stage of described first gain stage; Wherein said differential input stage has afterbody; And wherein said differential output stage is coupling between described afterbody and described second gain stage.
In an embodiment of the invention, described differential input stage has afterbody; And wherein said differential output stage comprises: the first voltage drop circuit and the second voltage drop circuit; First output stage transistor, has and is coupled to described afterbody and the described first the first conducting terminal exported, is coupled at least one gain stage described and the described second the second conducting terminal exported and is coupled to the control terminal of described first voltage drop circuit; And second output stage transistor, have and be coupled to described afterbody and the described first the first conducting terminal exported, be coupled at least one gain stage described and the described second the second conducting terminal exported and be coupled to the control terminal of described second voltage drop circuit.
In an embodiment of the invention, at least one in described first voltage drop circuit and described second voltage drop circuit comprises the transistor of the diode-coupled that be coupled source-series with fixed current.
On the other hand for error amplifier.Error amplifier can comprise differential input stage, and this differential input stage comprises coupling to receive the first input of the first signal, to be coupled to receive the second input and afterbody of secondary signal.Difference between differential input stage can be configured to based on the first and second signals generates comparison signal.At least one gain stage can be coupled to differential input stage and can be configured to amplify comparison signal.Differential output stage can have the first and second outputs, and can be configured to based on the comparison signal first export and the second output generate the first and second error signals.Differential output stage can have the first and second voltage drop circuits.Differential output stage can also have the first output stage transistor, and it contains and is coupled to afterbody and the first the first conducting terminal exported, is coupled at least one gain stage and the second the second conducting terminal exported and is coupled to the control terminal of the first voltage drop circuit.Differential output stage may further include the second output stage transistor, and this second output stage transistor has and is coupled to afterbody and the first the first conducting terminal exported, is coupled at least one gain stage and the second the second conducting terminal exported and is coupled to the control terminal of the second voltage drop circuit.
In an embodiment of the invention, at least one gain stage described comprises the first gain stage being coupled to described differential input stage, and is coupled to the second gain stage of described first gain stage; Wherein said differential input stage has afterbody; And wherein said differential output stage is coupling between described afterbody and described second gain stage.
In an embodiment of the invention, at least one in described first voltage drop circuit and described second voltage drop circuit comprises the transistor of the diode-coupled that be coupled source-series with fixed current.
Also an aspect is for amplifying circuit, comprising: error amplifier, has the first input and the second input and the first output and second and exports; Fill with level, be coupled to described first to export, described filling level comprises: fill with transistor, have and be coupled to the described first control terminal exported, the first conducting terminal being coupled to the first power supply node and the second conducting terminal, and filling current mirror, be coupled to described second conducting terminal of output node and described filling transistor; Draw level, be coupled to described second to export, described level of drawing comprises: pull transistor, have and be coupled to the described second control terminal exported, the first conducting terminal being coupled to second source node and the second conducting terminal, and draw current mirror, be coupled to described second conducting terminal of described output node and described pull transistor.
In an embodiment of the invention, described amplifying circuit also comprises the first feedback network be coupling between described first output with described second input, is coupling in the second feedback network between described second output with described second input.
In an embodiment of the invention, described amplifying circuit also comprises the 3rd feedback network be coupling between described output node and described second input.
Another aspect, for amplifying circuit, comprising: differential input stage, comprise coupling with receives reference signal first input, be coupled with second of receiving feedback signals input and afterbody, at least one gain stage, is coupled to described differential input stage, differential output stage, there is the first output and second export and comprise: the first voltage drop circuit and the second voltage drop circuit, first output stage transistor, have and be coupled to described afterbody and the described first the first conducting terminal exported, be coupled at least one gain stage described and the described second the second conducting terminal exported, and be coupled to the control terminal of described first voltage drop circuit, and second output stage transistor, have and be coupled to described afterbody and the described first the first conducting terminal exported, be coupled at least one gain stage described and the described second the second conducting terminal exported, and be coupled to the control terminal of described second voltage drop circuit.
In an embodiment of the invention, at least one gain stage described comprises the first gain stage being coupled to described differential input stage, and is coupled to the second gain stage of described first gain stage; Wherein said differential input stage has afterbody; And wherein said differential output stage is coupling between described afterbody and described second gain stage.
In an embodiment of the invention, at least one in described first voltage drop circuit and described second voltage drop circuit comprises the transistor of the diode-coupled that be coupled source-series with fixed current.
Accompanying drawing explanation
Fig. 1 is the schematic block diagram according to low voltage difference amplifier of the present disclosure.
Fig. 2 is the schematic block diagram of the error amplifier in Fig. 1.
To be low voltage difference amplifier in Fig. 1 filling with and pull transistor and filling and draw the schematic block diagram of the improvement including amplifier stage between current mirror Fig. 3.
Embodiment
Will be described below one or more embodiment of the present disclosure.Embodiment described by these is only the example of current public technology.In addition, in order to provide simple and clear description, all features of actual execution mode may not described in the description.It is to be appreciated that, in the exploitation of all this actual execution modes (as in any engineering or design object), the distinctive decision of numerous execution mode can be made to realize the specific objective of developer, such as can differently because of execution mode be correlated with the constraint relevant with business to meet system.In addition, it is to be appreciated that this development may be complicated and time-consuming, but for the those of ordinary skill in the art wanting to benefit from the disclosure, will be design, production and the routine mission in manufacturing.
When introducing the element of each embodiment of the present disclosure, article " ", " one " and " being somebody's turn to do " are intended to mean one or more element.When relating to transistor, it should be noted, term " the first conducting terminal " and " the second conducting terminal " do not relate to structure or bias voltage, and are only mark on the contrary." the first conducting terminal " is for representing the conducting terminal at the top on the page that transistor occurs near accompanying drawing, and " the second conducting terminal " is for representing the conducting terminal of the bottom on the page that transistor occurs near accompanying drawing.Term " the first conducting terminal " and " the second conducting terminal " can be called source electrode and drain electrode, and this does not need to be consistent between transistor.Such as, " first conducting terminal " of a transistor can be source electrode, and " first conducting terminal " of another transistor can be drain electrode.
First with reference to Fig. 1, the voltage regulator 100 being used for electronic equipment is described now.Electronic equipment can be panel computer, smart mobile phone, intelligent watch or any suitable equipment, and can be powered by battery (not shown) in some applications.Voltage regulator 100 can be configured to low dropout regulator, and the ability of existing filling electric current has again the ability of drawing electric current.
Voltage regulator 100 comprises the error amplifier 200 be coupling between the first power Vcc and ground GND.Error amplifier 200 has first and second inputs of being coupled to reference signal Vref and feedback signal FBK respectively.Reference signal Vref is temperature influence not, and can be generated by such as band gap maker (not shown).Feedback signal FBK provides self feed back node 105, and wherein first, second, and third feedback network 106,108 and 110 is coupled to this feedback node.
Error amplifier 200 exports first and second respectively, and EA_out_p, EA_out_n place generation first and second differential error signal Verr1, Verr2 and these error signals are based on the difference between reference signal Vref and feedback signal FBK.First feedback network 106 is coupling in first of error amplifier 200 and exports between feedback node 105, and comprises computer desk Cz2 and the resistor Rz2 of series connection.Similarly, the second feedback network 108 is coupling in second of error amplifier 200 and exports between feedback circuit node 105, and comprises capacitor Cz1 and the resistor Rz1 of series connection.3rd feedback network 110 is coupling between output node Vout and feedback node 105.Feedback signal BNK is coupled to the top node TP of network 110.
The load represented by Rload, is coupling between output node Vout and ground GND.3rd feedback network 110 (as mentioned above) is coupling between output node Vout and feedback node 105, and in parallel with load Rload.3rd feedback network 110 comprises first and second resistor R1, R2 of series connection.Load capacitor Cload and represent the resistor ESR of its equivalent series resistance and coupled in series with one another, and with load Rload and the 3rd feedback network 110 parallel coupled.
Voltage regulator 100 comprises the first transistor M14 and transistor seconds M10.The first transistor M14 is controlled by the first error signal Verr1, and generates the first electric current.Fill with level 104 and be coupled to the first transistor M14 to receive the first electric current and mirror image first electric current is applied to the filling electric current of output node Vout to generate.Transistor seconds M10 is controlled by the second error signal Verr2, and generates the second electric current.Draw level 102 be coupled to transistor seconds M10 with receive the second electric current and mirror image second electric current with generate be applied to output node Vout draw electric current.
Draw level 102 based on instruction through the electric current of overload Rload threshold value zero in or be greater than zero feedback signal FBK, and export and draw electric current, and if feedback signal FBK indicates the electric current through overload Rload to be less than zero, then draw level 102 to turn off.Fill with level 104 based on instruction through the electric current of overload Rload in threshold value zero or be greater than zero feedback signal FBK, and draw filling electric current.Similarly, if feedback signal FBK instruction is greater than zero through the electric current of overload Rload, then fills with level 104 and turn off.
The first transistor M14 has the first conducting terminal of being all coupled to the first power source Vcc and body terminal, be coupled to fill with level 104 the second conducting terminal, be coupled to first of error amplifier 200 and export with the control terminal receiving the first error signal Verr1.
Fill with level 104 and comprise transistor M17, M18 of being configured to current mirror, this current mirror by second conducting terminal of the first current delivery to the first transistor M14, and draws the first electric current from output node Vout.Current-limiting resistor Rlim1 (limiting the first electric current) is coupled in series between second conducting terminal of the first transistor M14 and the current mirror formed by transistor M17, M18.
Transistor M17 has the first conducting terminal being coupled to current-limiting resistor Rlim1, the second conducting terminal being all coupling to ground GND and body terminal and is coupled to the control terminal of the first conducting terminal.Transistor M18 has the first conducting terminal being coupled to output node Vout, the second conducting terminal being all coupling to ground GND and body terminal and is coupled to the control terminal of control terminal of transistor M17.
In more detail, transistor seconds M10 have be coupled to draw the first conducting terminal of level 102, the second conducting terminal being all coupling to ground GND and body terminal and be coupled to error amplifier 200 second export with the control terminal receiving the second error signal Verr2.
Draw level 102 to comprise to be configured to transistor M15, M16 of current mirror, this current mirror will receive the second electric current from first conducting terminal of transistor seconds M10, and by the second current mirror to output node Vout.Current-limiting resistor Rlim2 (limiting the second electric current) is coupled in series between first conducting terminal of transistor seconds M10 and the current mirror formed by transistor M15, M16.
Transistor M15 have all be coupled to the second power source Vbatt the first conducting terminal and body terminal, be coupled to current-limiting resistor Rlim2 to receive the second conducting terminal of the second electric current and to be coupled to the control terminal of the second conducting terminal.Transistor M16 has the first conducting terminal of being all coupled to the second power source Vbatt and body terminal, be coupled to second conducting terminal of output node Vout and be coupled to the control terminal of control terminal of transistor M15.
With reference to Fig. 2, provide now the details of error amplifier 200.Error amplifier 200 comprises differential input stage 202, and this differential input stage comprises the first and second inputs (as mentioned above) receiving reference voltage Vref and feedback signal FBK respectively.Differential input stage 202 generates comparison signal based on the difference between reference voltage Vref and feedback signal FBK.Afterbody 204 is coupled to differential input stage 202, and constant current is mirrored to differential input stage 202 from current source CS1, and is mirrored to the differential output stage 210 that hereafter will describe.First gain stage 206 or active pull-up circuit are coupled to differential input stage 202, and amplify comparison signal.Second gain stage 208 is coupled to the first gain stage 206, and amplifies comparison signal further.
Differential output stage 210 is coupled to the second gain stage 208, and exports generation and output the first and second error signal Verr1, Verr2 on EA_out_p, EA_out_n based on the comparison signal amplified first and second.Compensated stage 212 is coupling between the second gain stage 208 and differential output stage 210, and compensates exaggerated comparison signal as understood by those skilled in the art.
In more detail, differential input stage 202 comprises transistor M1, M2, and the first conducting terminal and its body terminal of these transistors are coupled to each other.The body terminal of transistor M1, M2 is also coupled to the first power source Vcc.Second conducting terminal of transistor M1, M2 is coupled to first conducting terminal (as will be explained later) of transistor M3, M4 of composition first gain stage 206 respectively.The control terminal of transistor M1, M2 is coupled to reference voltage Vref and feedback signal FBK respectively.
First gain stage 206 or active load level comprise transistor M3, M4, and the first conducting terminal of these transistors is coupled to second conducting terminal of transistor M1, M2 respectively.Transistor M3, M4 also have the second conducting terminal and body terminal that are all coupling to ground GND, and coupled to each other and be coupled to the control terminal of first conducting terminal of transistor M4.
Second gain stage 208 comprises transistor M8.Transistor M8 has the first conducting terminal being coupled to differential output stage 210, the second conducting terminal being all coupling to ground GND and body terminal and is coupled to the control terminal of the first conducting terminal of transistor M3.
Afterbody 204 comprises transistor M5, M6, and these transistors have the first conducting terminal and body terminal that are all coupling to ground the first power source Vcc, and control terminal coupled to each other.Transistor M5 has second conducting terminal of control terminal and the current source CS1 being coupled to transistor M5, M6.Transistor M6 has the second conducting terminal of the first conducting terminal being coupled to transistor M1, M2.Transistor M7 has the first conducting terminal of being coupled to the first power source Vcc and body terminal, be coupled to the second conducting terminal of differential output stage 210 and be coupled to the control terminal of control terminal of transistor M5, M6.
Differential output stage 210 comprises transistor M12, M16, and these transistors have the second conducting terminal of being coupled to transistor M7 to receive the first conducting terminal of constant current from it, and is coupled to second conducting terminal of the first conducting terminal of transistor M8.First and second conducting terminals of transistor M12, M16 are also coupled to compensating network 212.The body terminal of transistor M12 is coupling to ground GND, and the body terminal of transistor M16 is coupled to the first power source Vcc.The control terminal of transistor M12 is coupled to voltage drop circuit 216, and the control terminal of transistor M16 is coupled to the first voltage drop circuit 214.
First voltage drop circuit 214 comprises with the second current source CS2 series coupled to pull constant current from pair of transistor M13, the M15 of the diode-coupled of its process.Second voltage drop circuit 216 comprises with the 3rd current source CS3 series coupled to receive pair of transistor M11, the M9 of the diode-coupled of constant current from it.
Differential output stage 210 comprises first of output first error signal Verr1 and exports, and first conducting terminal of transistor M12, M16 is coupled in this first output.Differential output stage 210 also comprises second of output second error signal Verr2 and exports, and second conducting terminal of transistor M12, M16 is coupled in this second output.
Described by referring now to Fig. 3, in some applications, amplifier stage 300 can be coupling in first and second transistor M14, M10 and the filling formed by transistor M17, M18 and M15, M16 and draw between current mirror.This amplifier stage 300 can help to reduce the breakdown current through transistor M16, M18.As shown in Figure 3, it will be understood by those skilled in the art that amplifier stage is class ab ammplifier.
Herein, a pair resistor R3, R4 are coupled in series between second conducting terminal of the first transistor M14 and first conducting terminal of transistor seconds M10.Amplifier stage 300 comprises a pair resistor R5, R6 being coupled in series between the first power source Vcc and ground GND.Transistor M20 have the first conducting terminal being coupled to the 4th current source CS4, the first conducting terminal being coupled to transistor M22 the second conducting terminal, be coupled to the control terminal of the control terminal of himself the first conducting terminal and transistor M21 and be coupled to the body terminal of himself the second conducting terminal.
Transistor M22 have the second conducting terminal being coupled to transistor M20 the first conducting terminal, be coupled to the 5th current source CS5 the second conducting terminal, be coupled to the control terminal of the control terminal of himself the second conducting terminal and transistor M23 and be coupled to the body terminal of the first power source Vcc.Transistor M21 have the second conducting terminal being coupled to transistor M19 the first conducting terminal (by explaining hereinafter), be coupled to first conducting terminal of transistor M23 the second conducting terminal, be coupled to the control terminal of the control terminal of transistor M20 and be coupled to the body terminal of himself the second conducting terminal.Transistor 23 have the second conducting terminal being coupled to transistor M21 the first conducting terminal, be coupled to fill with level 104 the second conducting terminal, be coupled to the control terminal of the control terminal of transistor M22 and be coupled to the body terminal of the first power source Vcc.
Second conducting terminal of transistor M20 and first conducting terminal of transistor M22 are coupled to the node between resistor R5, R6.Second conducting terminal of transistor M21 and first conducting terminal of transistor M23 are coupled to the node between resistor R3, R4.
Refer again to Fig. 1 and Fig. 2, describe now the calculating of the alternating-current parameter of electronic equipment 100.Open when drawing level 102 and fill with level 104 and turn off, loop gain can be calculated as follows:
A
EA(EA_out_n)≈g
M1(r
M1||r
M3)g
M8r
M8(1)
When drawing level 102 and filling both levels 104 are opened, loop gain can be calculated as follows:
A
EA(EA_out_n)＝g
M1(r
M1||r
M3)g
M8r
EA_out_n(4)
i
M12＝i
M16(5)
g
M16v
EA_out_p＝g
M12v
EA_out_n(6)
(8)
When filling with level 104 and opening and draw level 102 to turn off, loop gain can be calculated as follows:
A
EA(EA_out_p)≈g
M1(r
M1||r
M3)g
M8r
M7(9)
Although describe the disclosure with reference to a limited number of embodiment, the those skilled in the art be benefited from the disclosure will understand, and it is contemplated that other embodiment of the scope not deviating from content disclosed herein.Therefore, the scope of the present disclosure should only be limited by the appended claims.
Claims (20)
1. a low voltage difference amplifier, is characterized in that, comprising:
Error amplifier, there is first input and the second input of being coupled to reference signal and feedback signal respectively, and be configured to export and the second output generation first error signal and the second error signal first respectively, described first error signal and described second error signal are based on the difference between described reference signal and described feedback signal;
Fill with level, be coupled to described first and export and be configured to based on described first error signal and generate filling electric current;
Draw level, be coupled to described second and export and be configured to generate based on described second error signal draw electric current; And
Output node, is coupled to receive described filling electric current and describedly draws electric current.
2. low voltage difference amplifier according to claim 1, is characterized in that, comprises the load of being coupled to described output node further; Wherein said filling level is configured in zero threshold value, export described filling electric current through the electric current of described load based on described feedback signal instruction; And wherein said draw level be configured to generate in zero threshold value through the electric current of overload based on the instruction of described feedback signal described in draw electric current.
3. low voltage difference amplifier according to claim 1, is characterized in that, comprises the load of being coupled to described output node further; And it is negative and generate described filling electric current that wherein said filling level to be configured to based on the instruction of described feedback signal through the electric current of described load.
4. low voltage difference amplifier according to claim 1, is characterized in that, comprises the load of being coupled to described output node further; And wherein said level of drawing is configured to indicate the electric current through described load to be positive based on described feedback signal and draw electric current described in generation.
5. low voltage difference amplifier according to claim 1, is characterized in that, described filling level comprises:
Transistor, have and be coupled to described first output to receive the control terminal of described first error signal, the first conducting terminal being coupled to the first power supply node and the second conducting terminal, described transistor is configured to generate electric current based on described first error signal from its second conducting terminal;
Fill with current mirror, be coupled to described second conducting terminal of described transistor and described output node, and be configured to be the described filling electric current being applied to described output node by described current mirror.
6. low voltage difference amplifier according to claim 1, is characterized in that, described in draw level to comprise:
Transistor, have and be coupled to described second output to receive the control terminal of described second error signal, the first conducting terminal being coupled to second source node and the second conducting terminal, described transistor is configured to generate electric current based on described second error signal from its second conducting terminal;
Draw current mirror, be coupled to described second conducting terminal of described transistor and described output node, and be configured to described current mirror to draw electric current to described output node as described.
7. low voltage difference amplifier according to claim 1, it is characterized in that, comprise further be coupling in described first export with described second input between the first feedback network, be coupling in described second export with described second input between the second feedback network and be coupling in described output node and described second input between the 3rd feedback network.
8. low voltage difference amplifier according to claim 1, is characterized in that, described error amplifier comprises:
Differential input stage, comprise described first input and described second and input, described differential input stage is configured to based on the difference between the described reference signal of described first input and the described feedback signal of described second input and generates comparison signal;
At least one gain stage, is coupled to the input of described differential input stage and is configured to amplify described comparison signal;
Differential output stage, is coupled at least one gain stage described and is configured to based on described comparison signal and exports described first error signal and described second error signal.
9. low voltage difference amplifier according to claim 8, is characterized in that, at least one gain stage described comprises the first gain stage of the described input of being coupled to described differential input stage, and is coupled to the second gain stage of described first gain stage; Wherein said differential input stage has afterbody; And wherein said differential output stage is coupling between described afterbody and described second gain stage.
10. low voltage difference amplifier according to claim 8, is characterized in that, described differential input stage has afterbody; And wherein said differential output stage comprises:
First voltage drop circuit and the second voltage drop circuit;
First output stage transistor, has and is coupled to described afterbody and the described first the first conducting terminal exported, is coupled at least one gain stage described and the described second the second conducting terminal exported and is coupled to the control terminal of described first voltage drop circuit; And
Second output stage transistor, has and is coupled to described afterbody and the described first the first conducting terminal exported, is coupled at least one gain stage described and the described second the second conducting terminal exported and is coupled to the control terminal of described second voltage drop circuit.
11. low voltage difference amplifiers according to claim 10, is characterized in that, at least one in described first voltage drop circuit and described second voltage drop circuit comprises the transistor of the diode-coupled that be coupled source-series with fixed current.
12. 1 kinds of error amplifiers, is characterized in that, comprising:
Differential input stage, comprise coupling to receive the first input of the first signal, to be coupled to receive the second input and afterbody of secondary signal, described differential input stage is configured to based on the difference between described first signal and described secondary signal and generates comparison signal;
At least one gain stage, is coupled to described differential input stage and is configured to amplify described comparison signal;
Differential output stage, has the first output and second and exports, and be configured to generate the first error signal and the second error signal based on described comparison signal in described first output and described second output, and comprise:
First voltage drop circuit and the second voltage drop circuit,
First output stage transistor, have and be coupled to described afterbody and the described first the first conducting terminal exported, be coupled at least one gain stage described and the described second the second conducting terminal exported and be coupled to the control terminal of described first voltage drop circuit, and
Second output stage transistor, has and is coupled to described afterbody and the described first the first conducting terminal exported, is coupled at least one gain stage described and the described second the second conducting terminal exported and is coupled to the control terminal of described second voltage drop circuit.
13. error amplifiers according to claim 12, is characterized in that, at least one gain stage described comprises the first gain stage being coupled to described differential input stage, and are coupled to the second gain stage of described first gain stage; Wherein said differential input stage has afterbody; And wherein said differential output stage is coupling between described afterbody and described second gain stage.
14. error amplifiers according to claim 12, is characterized in that, at least one in described first voltage drop circuit and described second voltage drop circuit comprises the transistor of the diode-coupled that be coupled source-series with fixed current.
15. 1 kinds of amplifying circuits, is characterized in that, comprising:
Error amplifier, has the first input and the second input and first exports and the second output;
Fill with level, be coupled to described first and export, described filling level comprises:
Fill with transistor, have and be coupled to the described first control terminal exported, the first conducting terminal being coupled to the first power supply node and the second conducting terminal, and
Fill with current mirror, be coupled to described second conducting terminal of output node and described filling transistor;
Draw level, be coupled to described second export, described in draw level to comprise:
Pull transistor, has and is coupled to the described second control terminal exported, the first conducting terminal being coupled to second source node and the second conducting terminal, and
Draw current mirror, be coupled to described second conducting terminal of described output node and described pull transistor.
16. amplifying circuits according to claim 15, is characterized in that, comprise the first feedback network be coupling between described first output with described second input further, are coupling in the second feedback network between described second output with described second input.
17. amplifying circuits according to claim 16, is characterized in that, comprise the 3rd feedback network be coupling between described output node and described second input further.
18. 1 kinds of amplifying circuits, is characterized in that, comprising:
Differential input stage, comprise coupling with receives reference signal first input, be coupled with second of receiving feedback signals input and afterbody;
At least one gain stage, is coupled to described differential input stage;
Differential output stage, has the first output and second and exports and comprise:
First voltage drop circuit and the second voltage drop circuit,
First output stage transistor, have and be coupled to described afterbody and the described first the first conducting terminal exported, be coupled at least one gain stage described and the described second the second conducting terminal exported and be coupled to the control terminal of described first voltage drop circuit, and
Second output stage transistor, has and is coupled to described afterbody and the described first the first conducting terminal exported, is coupled at least one gain stage described and the described second the second conducting terminal exported and is coupled to the control terminal of described second voltage drop circuit.
19. amplifying circuits according to claim 18, is characterized in that, at least one gain stage described comprises the first gain stage being coupled to described differential input stage, and are coupled to the second gain stage of described first gain stage; Wherein said differential input stage has afterbody; And wherein said differential output stage is coupling between described afterbody and described second gain stage.
20. amplifying circuits according to claim 18, is characterized in that, at least one in described first voltage drop circuit and described second voltage drop circuit comprises the transistor of the diode-coupled that be coupled source-series with fixed current.
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| CN201420852824.7U CN204652316U (en) | 2014-12-29 | 2014-12-29 | Low voltage difference amplifier, error amplifier and amplifying circuit |
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| CN201420852824.7U CN204652316U (en) | 2014-12-29 | 2014-12-29 | Low voltage difference amplifier, error amplifier and amplifying circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105811905A (en) * | 2014-12-29 | 2016-07-27 | 意法半导体研发(深圳)有限公司 | Low-dropout amplifier |
| CN113411058A (en) * | 2020-03-16 | 2021-09-17 | 万国半导体国际有限合伙公司 | Digital programmable fully differential error amplifier |
| CN113885626A (en) * | 2017-01-07 | 2022-01-04 | 德克萨斯仪器股份有限公司 | Method and circuit system for compensating low dropout linear regulator |
-
2014
- 2014-12-29 CN CN201420852824.7U patent/CN204652316U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105811905A (en) * | 2014-12-29 | 2016-07-27 | 意法半导体研发(深圳)有限公司 | Low-dropout amplifier |
| CN105811905B (en) * | 2014-12-29 | 2019-05-03 | 意法半导体研发(深圳)有限公司 | Low voltage difference amplifier |
| CN113885626A (en) * | 2017-01-07 | 2022-01-04 | 德克萨斯仪器股份有限公司 | Method and circuit system for compensating low dropout linear regulator |
| CN113885626B (en) * | 2017-01-07 | 2023-03-10 | 德克萨斯仪器股份有限公司 | Method and circuit system for compensating low dropout linear regulator |
| CN113411058A (en) * | 2020-03-16 | 2021-09-17 | 万国半导体国际有限合伙公司 | Digital programmable fully differential error amplifier |
| CN113411058B (en) * | 2020-03-16 | 2024-03-26 | 万国半导体国际有限合伙公司 | Digital programmable full differential error amplifier |
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