CN204633588U - For the soft starting circuit of power conversion system - Google Patents
For the soft starting circuit of power conversion system Download PDFInfo
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- CN204633588U CN204633588U CN201520042114.2U CN201520042114U CN204633588U CN 204633588 U CN204633588 U CN 204633588U CN 201520042114 U CN201520042114 U CN 201520042114U CN 204633588 U CN204633588 U CN 204633588U
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- termination
- resistance
- comparator
- flop
- rest
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Abstract
The utility model discloses a kind of soft starting circuit for power conversion system.Soft starting circuit for power conversion system comprises the 3rd resistance, the 4th resistance, the 5th resistance, the first PNP pipe, the second NMOS tube, the first comparator, the first rest-set flip-flop, the second rest-set flip-flop, the second comparator and the second electric capacity.The soft starting circuit for power conversion system utilizing the utility model to provide can make output voltage slowly rise to be unlikely to cause damage to power tube and lock-in tube.
Description
Technical field
The utility model relates to soft starting circuit, refers more particularly to the soft starting circuit for power conversion system.
Background technology
In power conversion system, in order to prevent larger overshoot current from making system injury, being provided with soft starting circuit, output voltage can be made slowly to increase.
Summary of the invention
The utility model aims to provide a kind of soft starting circuit for power conversion system that output voltage can be made slowly to increase be unlikely to cause power tube and lock-in tube damage.
Power conversion system, comprises error amplifier, pulse-width modulation circuit, power tube, lock-in tube, energy storage inductor, filter capacitor, the first resistance, the second resistance and soft starting circuit:
Described error amplifier amplifies the difference of the feedback voltage produced through described first resistance and described second electric resistance partial pressure and reference voltage V REF2;
Described pulse-width modulation circuit is the opening time carrying out regulating described power tube and described lock-in tube according to the height of the output of described error amplifier;
Described power tube carries out energy storage to described energy storage inductor, and output current;
Described lock-in tube is in order to described energy storage inductor afterflow;
Described energy storage inductor carries out energy storage to the electric current that described power tube flows through, and carries out afterflow to the electric current that described lock-in tube flows through;
Described filter capacitor carries out filtering to the voltage that described energy storage inductor exports and produces direct voltage;
Described first resistance becomes dividing potential drop feedback resistance to be carry out dividing potential drop to output voltage to feed back to described error amplifier with described second resistor group;
Described soft starting circuit produces soft-start signal to make reference voltage V REF2 slowly rise to make output voltage and electric current slowly increase.
One end of first resistance described in the negative input termination of described error amplifier and one end of described second resistance, positive input termination reference voltage V REF2 and described soft starting circuit, export the input of pulse-width modulation circuit described in termination;
The output of error amplifier described in the input termination of described pulse-width modulation circuit, the grid of power tube described in an output termination, another exports the grid of lock-in tube described in termination;
The grid of described power tube connects an output of described pulse-width modulation circuit, and source electrode meets supply voltage VCC, and drain electrode connects one end of described energy storage inductor and the drain electrode of described lock-in tube;
The grid of described lock-in tube connects another output of described pulse-width modulation circuit, source ground, and drain electrode connects the drain electrode of described power tube and one end of described energy storage inductor;
The drain electrode of power tube described in one termination of described energy storage inductor and the drain electrode of described lock-in tube, the other end is one end of device output and described filter capacitor and one end of described first resistance, the other end ground connection of described filter capacitor;
The output of one terminating set of described first resistance and one end of described energy storage inductor, one end of the second resistance described in another termination and the negative input end of described error amplifier, the other end ground connection of described second resistance;
Described soft starting circuit comprises the 3rd resistance, the 4th resistance, the 5th resistance, the first PNP pipe, the second NMOS tube, the first comparator, the first rest-set flip-flop, the second rest-set flip-flop, the second comparator and the second electric capacity:
One termination reference voltage V REF1 of described 3rd resistance, one end of the 4th resistance described in another termination and the positive input terminal of described first comparator;
One end of 3rd resistance described in one termination of described 4th resistance and the positive input terminal of described first comparator, one end of the 5th resistance described in another termination and the base stage of described first PNP pipe;
One end of 4th resistance described in one termination of described 5th resistance and the base stage of described first PNP pipe, other end ground connection;
The base stage of described first PNP pipe connects one end of described 4th resistance and one end of described 5th resistance, collector electrode connects grid and the drain electrode of described second NMOS tube, and emitter meets output and the reference voltage V REF2 of the negative input end of described first comparator and one end of described second electric capacity and described second comparator;
The grid of described second NMOS tube connects the collector electrode of drain electrode and described first PNP pipe, source ground;
One end of 3rd resistance described in the positive input termination of described first comparator and one end of described 4th resistance, the output of the emitter of the first PNP pipe described in negative input termination and one end of described second electric capacity and described second comparator, exports the R end of the first rest-set flip-flop described in termination and the R end of described second rest-set flip-flop;
The output of the first comparator described in the R termination of described first rest-set flip-flop and the R end of described second rest-set flip-flop, S holds ground connection, the S end of the second rest-set flip-flop described in Q termination;
The output of the first comparator described in the R termination of described second rest-set flip-flop and the R end of described first rest-set flip-flop, the Q end of the first rest-set flip-flop described in S termination, the positive input terminal of the second comparator described in Q termination, the negative input end of the second comparator described in the anti-phase termination of Q;
The Q end of the second rest-set flip-flop described in the positive input termination of described second comparator, the Q end of oppisite phase of the second rest-set flip-flop described in negative input termination, exports one end of termination second electric capacity and the negative input end of described first comparator and the emitter of described first PNP pipe and the positive input terminal of described error amplifier;
The output of the second comparator described in one termination of described second electric capacity and the negative input end of described first comparator and the emitter of described first PNP pipe and the positive input terminal of described error amplifier, other end ground connection.
When in supply voltage uphill process, reference voltage V REF1 also slowly rises, through described 3rd resistance, described 4th resistance and described 5th electric resistance partial pressure obtain positive input terminal comparative voltage and the indirectly negative terminal input comparative voltage of described first comparator, the output of described first comparator is high level, the Q end of described first rest-set flip-flop and described second rest-set flip-flop is high level, Q end of oppisite phase is low level, described like this second comparator is high level and makes VREF2 voltage slowly increase for described second capacitor charging, when VREF2 voltage rise is to when making described first PNP pipe conducting, VREF2 voltage is just by pincers voltage between the BE that described 5th ohmically voltage adds described first PNP pipe.
In power conversion system, output current maximum is determined by comparison point VREF2; By controlling comparison point VREF2, just can control the current value exported, comparison point VREF2 meets the output VREF2 of described second capacitor charge and discharge circuit and is determined by internal circuit, in power up, because VREF2 slowly rises, so output voltage VO UT is also slow increase, thus control the current value of output, reduce the impact to described power tube and described lock-in tube in power up, prevent described power tube and described lock-in tube from damaging.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the power conversion system with soft starting circuit of the present utility model.
Fig. 2 is power conversion system soft start uphill process figure.
Embodiment
Below in conjunction with accompanying drawing, the utility model content is further illustrated.
Power conversion system, as shown in Figure 1, comprises error amplifier 101, pulse-width modulation circuit 102, power tube 103, lock-in tube 104, energy storage inductor 105, filter capacitor 106, first resistance 107, second resistance 108 and soft starting circuit 200:
Described error amplifier 101 amplifies the difference of the feedback voltage produced through described first resistance 107 and described second resistance 108 dividing potential drop and reference voltage V REF2;
Described pulse-width modulation circuit 102 is the opening times carrying out regulating described power tube 103 and described lock-in tube 104 according to the height of the output of described error amplifier 101;
Described power tube 103 carries out energy storage to described energy storage inductor 105, and output current;
Described lock-in tube 104 is in order to the afterflow of described energy storage inductor 105;
Described energy storage inductor 105 carries out energy storage to the electric current that described power tube 103 flows through, and carries out afterflow to the electric current that described lock-in tube 104 flows through;
Described filter capacitor 106 carries out filtering to the voltage that described energy storage inductor 105 exports and produces direct voltage;
It is carry out dividing potential drop to output voltage to feed back to described error amplifier 101 that described first resistance 107 and described second resistance 108 form dividing potential drop feedback resistance;
Described soft starting circuit 200 produces soft-start signal to make reference voltage V REF2 slowly rise to make output voltage and electric current slowly increase.
One end of first resistance 107 described in the negative input termination of described error amplifier 101 and one end of described second resistance 108, positive input termination reference voltage V REF2 and described soft starting circuit 200, export the input of pulse-width modulation circuit 102 described in termination;
The output of error amplifier 101 described in the input termination of described pulse-width modulation circuit 102, the grid of power tube 103 described in an output termination, another exports the grid of lock-in tube 104 described in termination;
The grid of described power tube 103 connects an output of described pulse-width modulation circuit 102, and source electrode meets supply voltage VCC, and drain electrode connects one end of described energy storage inductor 105 and the drain electrode of described lock-in tube 104;
The grid of described lock-in tube 104 connects another output of described pulse-width modulation circuit 102, source ground, and drain electrode connects the drain electrode of described power tube 103 and one end of described energy storage inductor 105;
The drain electrode of power tube 103 described in one termination of described energy storage inductor 105 and the drain electrode of described lock-in tube 104, the other end is one end of device output and described filter capacitor 106 and one end of described first resistance 107, the other end ground connection of described filter capacitor 106;
The output of one terminating set of described first resistance 107 and one end of described energy storage inductor 105, one end of the second resistance 108 described in another termination and the negative input end of described error amplifier 101, the other end ground connection of described second resistance 108;
Described soft starting circuit comprises the 3rd resistance 201, the 4th resistance 202, the 5th resistance 203, first PNP pipe 204, second NMOS tube 205, first comparator 206, first rest-set flip-flop 207, second rest-set flip-flop 208, second comparator 209 and the second electric capacity 210:
One termination reference voltage V REF1 of described 3rd resistance 201, one end of the 4th resistance 202 described in another termination and the positive input terminal of described first comparator 206;
One end of 3rd resistance 201 described in one termination of described 4th resistance 202 and the positive input terminal of described first comparator 206, one end of the 5th resistance 203 described in another termination and the base stage of described first PNP pipe 204;
One end of 4th resistance 202 described in one termination of described 5th resistance 203 and the base stage of described first PNP pipe 204, other end ground connection;
The base stage of described first PNP pipe 204 connects one end of described 4th resistance 202 and one end of described 5th resistance 203, collector electrode connects grid and the drain electrode of described second NMOS tube 205, and emitter meets output and the reference voltage V REF2 of the negative input end of described first comparator 206 and one end of described second electric capacity 210 and described second comparator 209;
The grid of described second NMOS tube 205 connects the collector electrode of drain electrode and described first PNP pipe 204, source ground;
One end of 3rd resistance 201 described in the positive input termination of described first comparator 206 and one end of described 4th resistance 202, the output of the emitter of the first PNP pipe 204 described in negative input termination and one end of described second electric capacity 210 and described second comparator 209, exports the R end of the first rest-set flip-flop 207 described in termination and the R end of described second rest-set flip-flop 208;
The output of the first comparator 206 described in the R termination of described first rest-set flip-flop 207 and described second rest-set flip-flop
The R end of 208, S holds ground connection, the S end of the second rest-set flip-flop 208 described in Q termination;
The output of the first comparator 206 described in the R termination of described second rest-set flip-flop 208 and described first rest-set flip-flop
The R end of 207, the Q end of the first rest-set flip-flop 207 described in S termination, the positive input terminal of the second comparator 209 described in Q termination, the negative input end of the second comparator 209 described in the anti-phase termination of Q;
The Q end of the second rest-set flip-flop 208 described in the positive input termination of described second comparator 209, the Q end of oppisite phase of the second rest-set flip-flop 208 described in negative input termination, exports one end of termination second electric capacity 210 and the negative input end of described first comparator 206 and the described emitter of the first PNP pipe 204 and the positive input terminal of described error amplifier 101;
The output of the second comparator 209 described in one termination of described second electric capacity 210 and the negative input end of described first comparator 206 and the described emitter of the first PNP pipe 204 and the positive input terminal of described error amplifier 101, other end ground connection.
When in supply voltage uphill process, reference voltage V REF1 also slowly rises, through described 3rd resistance 201, described 4th resistance 202 and described 5th resistance 203 dividing potential drop obtain positive input terminal comparative voltage and the indirectly negative terminal input comparative voltage of described first comparator 206, the output of described first comparator 206 is high level, the Q end of described first rest-set flip-flop 207 and described second rest-set flip-flop 208 is high level, Q end of oppisite phase is low level, described like this second comparator 209 is for high level is also for described second electric capacity 210 charging makes VREF2 voltage slowly rise, when VREF2 voltage rise is to when making described first PNP pipe 204 conducting, voltage between VREF2 voltage is just added described first PNP pipe 204 BE by the voltage of pincers on described 5th resistance 203.
In power conversion system, output current maximum is determined by comparison point VREF2; By controlling comparison point VREF2, just can control the current value exported, comparison point VREF2 meets the output VREF2 of described second electric capacity 210 charge-discharge circuit and is determined by internal circuit, in power up, because VREF2 slowly rises, be illustrated in figure 2 power conversion system soft start uphill process figure, so output voltage VO UT is also slow increase, thus control the current value of output, reduce the impact to described power tube 103 and described lock-in tube 104 in power up, prevent described power tube 103 and described lock-in tube 104 from damaging.
Claims (1)
1. for the soft starting circuit of power conversion system, it is characterized in that, comprise the 3rd resistance, the 4th resistance, the 5th resistance, the first PNP pipe, the second NMOS tube, the first comparator, the first rest-set flip-flop, the second rest-set flip-flop, the second comparator and the second electric capacity:
One termination reference voltage V REF1 of described 3rd resistance, one end of the 4th resistance described in another termination and the positive input terminal of described first comparator;
One end of 3rd resistance described in one termination of described 4th resistance and the positive input terminal of described first comparator, one end of the 5th resistance described in another termination and the base stage of described first PNP pipe;
One end of 4th resistance described in one termination of described 5th resistance and the base stage of described first PNP pipe, other end ground connection;
The base stage of described first PNP pipe connects one end of described 4th resistance and one end of described 5th resistance, collector electrode connects grid and the drain electrode of described second NMOS tube, and emitter meets output and the reference voltage V REF2 of the negative input end of described first comparator and one end of described second electric capacity and described second comparator;
The grid of described second NMOS tube connects the collector electrode of drain electrode and described first PNP pipe, source ground;
One end of 3rd resistance described in the positive input termination of described first comparator and one end of described 4th resistance, the output of the emitter of the first PNP pipe described in negative input termination and one end of described second electric capacity and described second comparator, exports the R end of the first rest-set flip-flop described in termination and the R end of described second rest-set flip-flop;
The output of the first comparator described in the R termination of described first rest-set flip-flop and the R end of described second rest-set flip-flop, S holds ground connection, the S end of the second rest-set flip-flop described in Q termination;
The output of the first comparator described in the R termination of described second rest-set flip-flop and the R end of described first rest-set flip-flop, the Q end of the first rest-set flip-flop described in S termination, the positive input terminal of the second comparator described in Q termination, the negative input end of the second comparator described in the anti-phase termination of Q;
The Q end of the second rest-set flip-flop described in the positive input termination of described second comparator, the Q end of oppisite phase of the second rest-set flip-flop described in negative input termination, exports one end of termination second electric capacity and the negative input end of described first comparator and the described emitter of the first PNP pipe and the positive input terminal of error amplifier;
The output of the second comparator described in one termination of described second electric capacity and the negative input end of described first comparator and the described emitter of the first PNP pipe and the positive input terminal of error amplifier, other end ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520042114.2U CN204633588U (en) | 2015-01-20 | 2015-01-20 | For the soft starting circuit of power conversion system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520042114.2U CN204633588U (en) | 2015-01-20 | 2015-01-20 | For the soft starting circuit of power conversion system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204633588U true CN204633588U (en) | 2015-09-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520042114.2U Expired - Fee Related CN204633588U (en) | 2015-01-20 | 2015-01-20 | For the soft starting circuit of power conversion system |
Country Status (1)
| Country | Link |
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| CN (1) | CN204633588U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111555603A (en) * | 2020-06-22 | 2020-08-18 | 无锡英迪芯微电子科技股份有限公司 | Self-calibration soft start circuit of buck converter |
-
2015
- 2015-01-20 CN CN201520042114.2U patent/CN204633588U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111555603A (en) * | 2020-06-22 | 2020-08-18 | 无锡英迪芯微电子科技股份有限公司 | Self-calibration soft start circuit of buck converter |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150909 Termination date: 20160120 |
|
| EXPY | Termination of patent right or utility model |