CN204258612U - Reduce switch overshoot voltage device - Google Patents

Abstract

The utility model discloses a kind of reduction switch overshoot voltage device.Reduce switch overshoot voltage device and comprise error amplifier, pulse-width modulation circuit, the first PMOS, the first NMOS tube, the first electric capacity, the second PMOS, the second NMOS tube, the second electric capacity, power tube, lock-in tube, energy storage inductor, filter capacitor, the first resistance and the second resistance.The device utilizing the utility model to provide can reduce power tube and the overshoot voltage of lock-in tube when on off state.

Description

Reduce switch overshoot voltage device

Technical field

The utility model relates to overshoot voltage reduction technology, and the overshoot voltage referred more particularly to when on off state reduces.

Background technology

In switch power supply system, high-tension overshoot voltage can be caused during the conducting of power tube and lock-in tube, make the damage of power tube and lock-in tube, be provided with for this reason and reduce switch overshoot voltage device.

Summary of the invention

The utility model is intended to solve the deficiencies in the prior art, provides a kind of and reduces power tube and the overshoot voltage of lock-in tube when on off state.

Reduce switch overshoot voltage device, comprise error amplifier, pulse-width modulation circuit, the first PMOS, the first NMOS tube, the first electric capacity, the second PMOS, the second NMOS tube, the second electric capacity, power tube, lock-in tube, energy storage inductor, filter capacitor, the first resistance and the second resistance:

Described error amplifier amplifies the difference of the feedback voltage produced through described first resistance and described second electric resistance partial pressure and reference voltage V REF;

Described pulse-width modulation circuit is that the size of the voltage produced according to described error amplifier produces pulse-width signal;

Described first PMOS and described first NMOS tube are connected into power tube described in inverter drive;

Described second PMOS and described second NMOS tube are connected into lock-in tube described in inverter drive;

Described first electric capacity is to reduce when described first PMOS conducting power supply VCC by the impact to described power tube grid between the source and drain of described first PMOS, there is the existence of described first electric capacity, the grid voltage of described power tube can be made slowly to increase, damage would not be caused to the grid of described power tube like this;

Described second electric capacity is to reduce when described second PMOS conducting power supply VCC by the impact to described lock-in tube grid between the source and drain of described second PMOS, there is the existence of described second electric capacity, the grid voltage of described lock-in tube can be made slowly to increase, would not damage the grid of described lock-in tube like this;

Described power tube carries out energy storage to described energy storage inductor, and output current;

Described lock-in tube is in order to described energy storage inductor afterflow;

Described energy storage inductor carries out energy storage to the electric current that described power tube flows through, and carries out afterflow to the electric current that described lock-in tube flows through;

Described filter capacitor carries out filtering to the voltage that described energy storage inductor exports and produces direct voltage;

Described first resistance becomes dividing potential drop feedback resistance to be carry out dividing potential drop to output voltage to feed back to described error amplifier with described second resistor group;

One end of first resistance described in the negative input termination of described error amplifier and one end of described second resistance, positive input termination reference voltage V REF, exports pulse-width modulation circuit described in termination;

The output of error amplifier described in described pulse-width modulation circuit input termination, one exports the grid of the first PMOS and the grid of described first NMOS tube described in termination, and another exports the grid of the second PMOS and the grid of described second NMOS tube described in termination;

Described in the input termination that described first PMOS and described first NMOS tube are connected into inverter, an output of pulse-width modulation circuit, exports one end of the first electric capacity and the grid of described power tube described in termination;

Described in the input termination that described second PMOS and described second NMOS tube are connected into inverter, another output of pulse-width modulation circuit, exports one end of the second electric capacity and the grid of described lock-in tube described in termination;

The grid of described power tube connects described first PMOS and described first NMOS tube is connected into the output of inverter and one end of described first electric capacity, and source electrode meets input power VCC, and drain electrode connects one end of described energy storage inductor and the drain electrode of described lock-in tube;

The grid of described lock-in tube connects described second PMOS and described second NMOS tube is connected into the output of inverter and one end of described second electric capacity, and drain electrode connects the drain electrode of described power tube and one end of described energy storage inductor, source ground;

The drain electrode of power tube described in one termination of described energy storage inductor and the drain electrode of described lock-in tube, the other end is the other end ground connection of one end of the output of device and one end of described filter capacitor and described first resistance, described filter capacitor;

One end of the output of one terminating set of described first resistance and one end of described energy storage inductor and described filter capacitor, one end of the second resistance described in another termination and the negative input end of described error amplifier, the other end ground connection of described second resistance.

After powering on, input power VCC passes through described power tube to described energy storage inductor output current, the feedback voltage that output voltage VO UT obtains through described first resistance and described second electric resistance partial pressure and reference voltage V REF amplify through described error amplifier the duty ratio that the error voltage signal obtained determines the pulse that described pulse-width modulation circuit exports, thus determine inductive current; The change of feedback voltage will cause the change driving described power tube signal dutyfactor by described error amplifier, thus controls the conducting of described power tube and deadline to reach the object of voltage stabilizing.

When the grid of described first PMOS is low level, power supply VCC is by driving described power tube grid between the source and drain of described first PMOS, when described first PMOS conducting, first described first electric capacity is charged, because capacitance voltage can not suddenly change, the grid voltage of described power tube would not have catastrophe, namely can not impact the grid of described power tube, can protect the grid of described power tube; In like manner; when the grid of described second PMOS is low level; power supply VCC is by driving described lock-in tube grid between the source and drain of described second PMOS; when described second PMOS conducting; first charge to described second electric capacity, because capacitance voltage can not suddenly change, the grid voltage of described lock-in tube would not have catastrophe; namely can not impact the grid of described lock-in tube, can protect the grid of described lock-in tube.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of reduction switch overshoot voltage device of the present utility model.

Embodiment

Below in conjunction with accompanying drawing, the utility model content is further illustrated.

Reduce switch overshoot voltage device, as shown in Figure 1, error amplifier 101, pulse-width modulation circuit 102, first PMOS 103, first NMOS tube 104, first electric capacity 105, second PMOS 106, second NMOS tube 107, second electric capacity 108, power tube 109, lock-in tube 110, energy storage inductor 111, filter capacitor 112, first resistance 113 and the second resistance 114 is comprised:

Described error amplifier 101 amplifies the difference of the feedback voltage produced through described first resistance 113 and described second resistance 114 dividing potential drop and reference voltage V REF;

Described pulse-width modulation circuit 102 is that the size of the voltage produced according to described error amplifier 101 produces pulse-width signal;

Described first PMOS 103 and described first NMOS tube 104 are connected into power tube 109 described in inverter drive;

Described second PMOS 106 and described second NMOS tube 107 are connected into lock-in tube 110 described in inverter drive;

Described first electric capacity 105 is to reduce when described first PMOS 103 conducting power supply VCC by the impact to described power tube 109 grid between the source and drain of described first PMOS 103, there is the existence of described first electric capacity 105, the grid voltage of described power tube 109 can be made slowly to increase, damage would not be caused to the grid of described power tube 109 like this;

Described second electric capacity 108 is to reduce when described second PMOS 106 conducting power supply VCC by the impact to described lock-in tube 110 grid between the source and drain of described second PMOS 106, there is the existence of described second electric capacity 108, the grid voltage of described lock-in tube 110 can be made slowly to increase, would not damage the grid of described lock-in tube 110 like this;

Described power tube 109 carries out energy storage to described energy storage inductor 111, and output current;

Described lock-in tube 110 is in order to the afterflow of described energy storage inductor 111;

Described energy storage inductor 111 carries out energy storage to the electric current that described power tube 109 flows through, and carries out afterflow to the electric current that described lock-in tube 110 flows through;

Described filter capacitor 112 carries out filtering to the voltage that described energy storage inductor 111 exports and produces direct voltage;

It is carry out dividing potential drop to output voltage to feed back to described error amplifier 101 that described first resistance 113 and described second resistance 114 form dividing potential drop feedback resistance;

One end of first resistance 113 described in the negative input termination of described error amplifier 101 and one end of described second resistance 114, positive input termination reference voltage V REF, exports pulse-width modulation circuit 102 described in termination;

Described pulse-width modulation circuit 102 inputs the output of error amplifier 101 described in termination, one exports the grid of the first PMOS 103 and the grid of described first NMOS tube 104 described in termination, and another exports the grid of the second PMOS 106 and the grid of described second NMOS tube 107 described in termination;

Described in the input termination that described first PMOS 103 and described first NMOS tube 104 are connected into inverter, an output of pulse-width modulation circuit 102, exports one end of the first electric capacity 105 and the grid of described power tube 109 described in termination;

Described in the input termination that described second PMOS 106 and described second NMOS tube 107 are connected into inverter, another output of pulse-width modulation circuit 102, exports one end of the second electric capacity 108 and the grid of described lock-in tube 110 described in termination;

The grid of described power tube 109 connects described first PMOS 103 and described first NMOS tube 104 is connected into the output of inverter and one end of described first electric capacity 105, source electrode meets input power VCC, and drain electrode connects one end of described energy storage inductor 111 and the drain electrode of described lock-in tube 110;

The grid of described lock-in tube 110 connects described second PMOS 106 and described second NMOS tube 107 is connected into the output of inverter and one end of described second electric capacity 108, and drain electrode connects the drain electrode of described power tube 109 and one end of described energy storage inductor 111, source ground;

The drain electrode of power tube 109 described in one termination of described energy storage inductor 111 and the drain electrode of described lock-in tube 110, the other end is one end of the output of device and one end of described filter capacitor 112 and described first resistance 113, the other end ground connection of described filter capacitor 116;

The output of one terminating set of described first resistance 113 and one end of one end of described energy storage inductor 111 and described filter capacitor 112, one end of second resistance 114 described in another termination and the negative input end of described error amplifier 101, the other end ground connection of described second resistance 114.

After powering on, input power VCC passes through described power tube 109 to described energy storage inductor 111 output current, the feedback voltage that output voltage VO UT obtains through described first resistance 113 and described second resistance 114 dividing potential drop and reference voltage V REF amplify through described error amplifier 101 duty ratio that the error voltage signal obtained determines the pulse that described pulse-width modulation circuit 102 exports, thus determine inductive current; The change of feedback voltage will cause the change driving described power tube 109 signal dutyfactor by described error amplifier 101, thus controls the conducting of described power tube 109 and deadline to reach the object of voltage stabilizing.

When the grid of described first PMOS 103 is low level, power supply VCC is by driving described power tube 109 grid between the source and drain of described first PMOS 103, when described first PMOS 103 conducting, first described first electric capacity 105 is charged, because capacitance voltage can not suddenly change, the grid voltage of described power tube 109 would not have catastrophe, namely can not impact the grid of described power tube 109, can protect the grid of described power tube 109; In like manner; when the grid of described second PMOS 106 is low level; power supply VCC is by driving described lock-in tube 110 grid between the source and drain of described second PMOS 106; when described second PMOS 106 conducting; first charge to described second electric capacity 108, because capacitance voltage can not suddenly change, the grid voltage of described lock-in tube 110 would not have catastrophe; namely can not impact the grid of described lock-in tube 110, can protect the grid of described lock-in tube 110.

Claims (1)

1. reduce switch overshoot voltage device, it is characterized in that comprising error amplifier, pulse-width modulation circuit, the first PMOS, the first NMOS tube, the first electric capacity, the second PMOS, the second NMOS tube, the second electric capacity, power tube, lock-in tube, energy storage inductor, filter capacitor, the first resistance and the second resistance:

One end of first resistance described in the negative input termination of described error amplifier and one end of described second resistance, positive input termination reference voltage V REF, exports pulse-width modulation circuit described in termination;

The output of error amplifier described in described pulse-width modulation circuit input termination, one exports the grid of the first PMOS and the grid of described first NMOS tube described in termination, and another exports the grid of the second PMOS and the grid of described second NMOS tube described in termination;

Described in the input termination that described first PMOS and described first NMOS tube are connected into inverter, an output of pulse-width modulation circuit, exports one end of the first electric capacity and the grid of described power tube described in termination;

Described in the input termination that described second PMOS and described second NMOS tube are connected into inverter, another output of pulse-width modulation circuit, exports one end of the second electric capacity and the grid of described lock-in tube described in termination;

The grid of described power tube connects described first PMOS and described first NMOS tube is connected into the output of inverter and one end of described first electric capacity, and source electrode meets input power VCC, and drain electrode connects one end of described energy storage inductor and the drain electrode of described lock-in tube;

The grid of described lock-in tube connects described second PMOS and described second NMOS tube is connected into the output of inverter and one end of described second electric capacity, and drain electrode connects the drain electrode of described power tube and one end of described energy storage inductor, source ground;

The drain electrode of power tube described in one termination of described energy storage inductor and the drain electrode of described lock-in tube, the other end is the other end ground connection of one end of the output of device and one end of described filter capacitor and described first resistance, described filter capacitor;

One end of the output of one terminating set of described first resistance and one end of described energy storage inductor and described filter capacitor, one end of the second resistance described in another termination and the negative input end of described error amplifier, the other end ground connection of described second resistance.