CN204615855U

CN204615855U - A kind of circuit of the 6 road code device signal transmission based on MAC layer

Info

Publication number: CN204615855U
Application number: CN201520382994.8U
Authority: CN
Inventors: 周文彪; 张彦钦; 孔民秀
Original assignee: HARBIN BOQIANG ROBOT TECHNOLOGY Co Ltd
Current assignee: HARBIN BOQIANG ROBOT TECHNOLOGY Co Ltd
Priority date: 2015-06-05
Filing date: 2015-06-05
Publication date: 2015-09-02
Anticipated expiration: 2025-06-05

Abstract

Based on a circuit for 6 road code device signal transmission of MAC layer, it belongs to the technical field of the data communication protocol conversion of robot.The MII digital signal I/O of FPGA chip circuit is connected with the MII digital signal input/output terminal of PHY chip circuit U 1; The difference MAC data frame I/O of PHY chip circuit U 1 is connected on the RJ45 socket J1 of band isolating transformer, the first via of FPGA chip circuit is connected with the digital signal I/O of 485 transceiver U8 ~ U13 to the 6th tunnel 485 digital signal input/output terminal respectively by digital light electric coupling U2 ~ U7, and the serial date transfer output of FPGA chip circuit is connected with the serial data I/O of EPCS configuring chip circuit.The utility model can be stable the RS485 signal of absolute value encoder be converted into MAC data frame transmit.Add transmission range and the stability of encoder data.The basis of MAC layer Frame is revised, increases the utilization rate that data use frame, ensure that the real-time of data input and data output.

Description

A kind of circuit of the 6 road code device signal transmission based on MAC layer

Technical field

The utility model belongs to the technical field of the data communication protocol conversion of robot.

Background technology

In industrial robot system, inevitably will use encoder miscellaneous, because how poor the operational environment of most industrial robot is, electromagnetic interference is serious.Make the encoder of RS485, Modbus of traditional type or common digital signal type cannot carry out the transmission of longer distance in the environment that noise is serious.In addition encoder data transmission (encoder as RS485 agreement, Mdobus or pulse interface) each encoder of traditional type interface needs to take 4 even more holding wires.When electrical control cubicles distance basic machine is far away, corresponding cable expense can increase, and adds cost.And Industrial Ethernet Internet Transmission distance is longer, speed can well solve the problem.Therefore in actual robot application, this kind of circuit is proposed to meet long range propagation stablized by industrial robot under complicated electric circumstance to encoder data requirement.

Summary of the invention

The purpose of this utility model is to provide a kind of circuit of the 6 road code device signal transmission based on MAC layer, is make the encoder of RS485, Modbus of traditional type or common digital signal type cannot carry out the transmission of longer distance and the problem of data cable high cost in the environment that noise is serious to solve existing robot.

Described object is realized by following scheme: the circuit of described a kind of 6 road code device signal transmission based on MAC layer, and it comprises RJ45 socket J1,232 transceivers 1, EPCS configuring chip circuit 2, Jtag interface 3, FPGA chip circuit 4, the SM-6P-PCB socket J2 ~ J7 of PHY chip circuit U 1, digital light electric coupling U2 ~ U7,485 transceiver U8 ~ U13, band isolating transformer;

The MII digital signal I/O of FPGA chip circuit 4 is connected with the MII digital signal input/output terminal of PHY chip circuit U 1; The difference MAC data frame I/O of PHY chip circuit U 1 is connected on the RJ45 socket J1 of band isolating transformer; the first via 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U8 by digital light electric coupling U2, second tunnel 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U9 by digital light electric coupling U3,3rd tunnel 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U10 by digital light electric coupling U4,4th tunnel 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U11 by digital light electric coupling U5,5th tunnel 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U12 by digital light electric coupling U6,6th tunnel 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U13 by digital light electric coupling U7, the serial date transfer output of FPGA chip circuit 4 is connected with the serial data I/O of EPCS configuring chip circuit 2,232 data-signal input/output bus ends of FPGA chip circuit 4 export input bus end with the data of 232 transceivers 1 and are connected, the Jtag test data I/O of FPGA chip circuit 4 is connected on Jtag interface 3, the 485 communication data I/Os of 485 transceiver U8 ~ U13 connect SM-6P-PCB socket J2 ~ J7 respectively, 485 transceiver U8 ~ U13 adopt insulating power supply independently-powered.

The utility model can be stable the RS485 signal of absolute value encoder be converted into MAC data frame transmit.Add transmission range and the stability of encoder data.The basis of MAC layer Frame is revised, increases the utilization rate that data use frame, ensure that the real-time of data input and data output.

Accompanying drawing explanation

Fig. 1 is integrated circuit structural representation of the present utility model.

Embodiment

Embodiment one: shown in composition graphs 1, it comprises RJ45 socket J1,232 transceivers 1, EPCS configuring chip circuit 2, Jtag interface 3, FPGA chip circuit 4, the SM-6P-PCB socket J2 ~ J7 of PHY chip circuit U 1, digital light electric coupling U2 ~ U7,485 transceiver U8 ~ U13, band isolating transformer;

The model that described PHY chip circuit U 1 is selected is 88E1111, and the model that digital light electric coupling U2 ~ U7 selects is the digital CMOS photoelectrical coupler of ACPL-064L/K64L low-power consumption 10MBd; The model that 485 transceiver U8 ~ U13 select is ADM485; The model selected with the RJ45 socket J1 of isolating transformer is HR911102A, and the model that 232 transceivers 1 are selected is MAX3232CUE; The model that EPCS configuring chip circuit 2 is selected is EPCS16SI8N; The model that FPGA chip circuit 4 is selected is EP4CE10E22 programmable logic device.

Operation principle: in present embodiment, circuit shown in Fig. 1 both can serve as main website and also can serve as slave station.The course of work that 6 road RS485 turn MAC layer Frame is as follows: when receiving driver and sending the instruction of data, main website FPGA chip circuit 4 starts that the data received are existed in the register of FPGA chip circuit 4 correspondence, deposit data in register is assembled in the data bit that MAC data frame is corresponding the form of MAC data frame after receiving the instruction that whole six drivers send, then data is passed to slave station circuit by the RJ45 socket J1 of PHY chip circuit U 1, band isolating transformer and netting twine successively.FPGA chip circuit 4 in slave station passes through to be with the RJ45 socket J1 of isolating transformer, PHY chip circuit U 1 receives data, and the data of MAC layer data frame data position are sent to 485 corresponding transceiver U8 ~ U13 according to the order of correspondence respectively by digital light electric coupling U2 ~ U7 by FPGA chip circuit 4 after receiving MAC layer Frame.Corresponding data is sent to FPGA chip circuit 4 according to the order of correspondence respectively by 485 transceiver U8 ~ U13 and digital light electric coupling U2 ~ U7 by the data delay of encoder circuit through 3us after receiving transmission data command.Receiving after data until FPGA chip circuit 4 is stored in register corresponding in FPGA chip circuit 4 by data, register addresses according to the number of axle of correspondence, after all data receivers complete, the deposit data in register is started to assemble MAC data frame to the position that MAC data frame is corresponding, after MAC data frame has been assembled by data successively by PHY chip circuit U 1, the band RJ45 socket J1 of isolating transformer and network cable transmission to main website circuit.Main website FPGA chip circuit 4 by netting twine, the band RJ45 socket J1 of isolating transformer and the return value of PHY chip circuit U 1 received code device, sends driver corresponding to each encoder to after the numerical value returned being sent to 485 corresponding transceiver U8 ~ U13 by digital light electric coupling U2 ~ U7 according to the order of data bit in MAC data frame successively.Circuit stores realization for the driver of each axle and the register that is identified by of encoder, and the register of each axle corresponds to fixing MAC layer data bit.

The course of work of RS232 part is as follows: send its transmission message format of self-defining message by host computer and comprise the part compositions such as circuit board ID, read-write state, phy address, phy register address, register data.Start the control register of SMI protocol configuration PHY chip circuit U 1 when FPGA chip circuit 4 receives corresponding phy chip register read write command and control extended register, thus reaching the object controlling PHY chip circuit U 1 mode of operation, its default mode of operation is full duplex 100Mbps forked working pattern.

Claims

1., based on a circuit for 6 road code device signal transmission of MAC layer, it is characterized in that it comprises RJ45 socket J1,232 transceivers (1), EPCS configuring chip circuit (2), Jtag interface (3), FPGA chip circuit (4), the SM-6P-PCB socket J2 ~ J7 of PHY chip circuit U 1, digital light electric coupling U2 ~ U7,485 transceiver U8 ~ U13, band isolating transformer;

The MII digital signal I/O of FPGA chip circuit (4) is connected with the MII digital signal input/output terminal of PHY chip circuit U 1; The difference MAC data frame I/O of PHY chip circuit U 1 is connected on the RJ45 socket J1 of band isolating transformer; the first via 485 digital signal input/output terminal of FPGA chip circuit (4) is connected with the digital signal I/O of 485 transceiver U8 by digital light electric coupling U2, second tunnel 485 digital signal input/output terminal of FPGA chip circuit (4) is connected with the digital signal I/O of 485 transceiver U9 by digital light electric coupling U3,3rd tunnel 485 digital signal input/output terminal of FPGA chip circuit (4) is connected with the digital signal I/O of 485 transceiver U10 by digital light electric coupling U4,4th tunnel 485 digital signal input/output terminal of FPGA chip circuit (4) is connected with the digital signal I/O of 485 transceiver U11 by digital light electric coupling U5,5th tunnel 485 digital signal input/output terminal of FPGA chip circuit (4) is connected with the digital signal I/O of 485 transceiver U12 by digital light electric coupling U6,6th tunnel 485 digital signal input/output terminal of FPGA chip circuit (4) is connected with the digital signal I/O of 485 transceiver U13 by digital light electric coupling U7, the serial date transfer output of FPGA chip circuit (4) is connected with the serial data I/O of EPCS configuring chip circuit (2), 232 data-signal input/output bus ends of FPGA chip circuit (4) export input bus end with the data of 232 transceivers (1) and are connected, the Jtag test data I/O of FPGA chip circuit (4) is connected on Jtag interface (3), the 485 communication data I/Os of 485 transceiver U8 ~ U13 connect SM-6P-PCB socket J2 ~ J7 respectively, 485 transceiver U8 ~ U13 adopt insulating power supply independently-powered.