CN104935587B - A kind of circuit of the 6 road code device signal transmission based on MAC layer - Google Patents
A kind of circuit of the 6 road code device signal transmission based on MAC layer Download PDFInfo
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- CN104935587B CN104935587B CN201510304000.5A CN201510304000A CN104935587B CN 104935587 B CN104935587 B CN 104935587B CN 201510304000 A CN201510304000 A CN 201510304000A CN 104935587 B CN104935587 B CN 104935587B
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- 230000008054 signal transmission Effects 0.000 title claims abstract description 6
- 230000005540 biological transmission Effects 0.000 claims abstract description 11
- 238000004891 communication Methods 0.000 claims abstract description 5
- 238000006243 chemical reaction Methods 0.000 abstract 1
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 238000004549 pulsed laser deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
- H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
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- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Small-Scale Networks (AREA)
Abstract
A kind of circuit of the 6 road code device signal transmission based on MAC layer, it belongs to the technical field of the data communication protocol conversion of robot.The MII data signals I/O of FPGA chip circuit is connected with the MII data signal input/output terminals of PHY chip circuit U 1；The difference MAC data frame I/O of PHY chip circuit U 1 is connected on the RJ45 sockets J1 with isolating transformer, the first via of FPGA chip circuit is connected by digital photoelectrical coupler U2~U7 with 485 transceiver U8~U13 data signal I/O respectively to the data signal input/output terminal of the 6th tunnel 485, and the serial date transfer output end of FPGA chip circuit is connected with the serial data I/O of EPCS configuration chip circuits.The RS485 signals of absolute value encoder stably can be converted into MAC data frame and are transmitted by the present invention.Add the transmission range and stability of encoder data.It is modified on the basis of MAC layer data frame, increase data use the utilization rate of frame, ensure that the real-time that data send and receive.
Description
Technical field
The invention belongs to the technical field that the data communication protocol of robot is changed.
Background technology
Miscellaneous encoder is inevitably used in industrial robot system, due to most industrial robots
Working environment it is how poor, electromagnetic interference is serious.So that RS485, Modbus or common digital signal class of traditional type
The encoder of type can not carry out the transmission of relatively long distance in the serious environment of noise.In addition the encoder number of traditional type interface
According to transmission（Such as the encoder of RS485 agreements, Mdobus or pulse interface）Each encoder needs to take 4 even
More signal wires.Electrical control cubicles apart from basic machine farther out when corresponding cable expense can increase, add cost.It is and industrial
Ethernet network transmission range is longer, and speed can be very good to solve the above problems.Therefore in actual robot application
Such a circuit is proposed to meet that industrial robot is wanted under complicated electric circumstance to the stable transmission over long distances of encoder data
Ask.
The content of the invention
It is existing in order to solve it is an object of the invention to provide a kind of circuit of the 6 road code device signal transmission based on MAC layer
There is robot make it that RS485, Modbus of traditional type or the encoder of common digital signal type can not be serious in noise
Environment in carry out the transmission of relatively long distance and the problem of too high data cable cost.
Described purpose is realized by following scheme：A kind of described 6 road code device signal transmission based on MAC layer
Circuit, it include PHY chip circuit U 1, digital photoelectrical coupler U2~U7,485 transceiver U8~U13, band isolating transformer
RJ45 sockets J1,232 transceivers 1, EPCS configurations chip circuit 2, Jtag interfaces 3, FPGA chip circuit 4, SM-6P-PCB insert
Seat J2~J7；
The MII data signals I/O of FPGA chip circuit 4 inputs with the MII data signals of PHY chip circuit U 1
Output end connects；The difference MAC data frame I/O of PHY chip circuit U 1 is connected to the RJ45 sockets with isolating transformer
On J1；The data signal input/output terminal of the first via 485 of FPGA chip circuit 4 is received and dispatched by digital photoelectrical coupler U2 and 485
Device U8 data signal I/O connection, the data signal input/output terminal of the second tunnel 485 of FPGA chip circuit 4 pass through number
Word photoelectrical coupler U3 is connected with 485 transceiver U9 data signal I/O, the 3rd tunnel 485 of FPGA chip circuit 4
Data signal input/output terminal is connected by digital photoelectrical coupler U4 with 485 transceiver U10 data signal I/O,
The data signal input/output terminal of the 4th tunnel 485 of FPGA chip circuit 4 passes through digital photoelectrical coupler U5 and 485 transceiver U11
The connection of data signal I/O, the data signal input/output terminal of the 5th tunnel 485 of FPGA chip circuit 4 passes through digital light
Electric coupler U6 is connected with 485 transceiver U12 data signal I/O, the numeral of the 6th tunnel 485 of FPGA chip circuit 4
Signal input output end is connected by digital photoelectrical coupler U7 with 485 transceiver U13 data signal I/O, FPGA
The serial date transfer output end of chip circuit 4 is connected with the serial data I/O of EPCS configuration chip circuits 2, FPGA
232 data-signal input/output bus ends of chip circuit 4 are connected with the data output input bus end of 232 transceivers 1, FPGA
The Jtag test data I/Os of chip circuit 4 are connected on Jtag interfaces 3；485 transceiver U8~U13 485 communications
Data output input connects SM-6P-PCB sockets J2~J7 respectively；485 transceiver U8~U13 are independently supplied using insulating power supply
Electricity.
The RS485 signals of absolute value encoder stably can be converted into MAC data frame and are transmitted by the present invention.Increase
The transmission range and stability of encoder data.It is modified on the basis of MAC layer data frame, increase data use frame
Utilization rate, it ensure that the real-time that data send and receive.
Brief description of the drawings
Fig. 1 is the integrated circuit structural representation of the present invention.
Embodiment
Embodiment one：With reference to shown in Fig. 1, it include PHY chip circuit U 1, digital photoelectrical coupler U2~U7,
485 transceiver U8~U13, the RJ45 sockets J1 with isolating transformer, 232 transceivers 1, EPCS configurations chip circuit 2, Jtag connect
Mouth 3, FPGA chip circuit 4, SM-6P-PCB sockets J2~J7；
The MII data signals I/O of FPGA chip circuit 4 inputs with the MII data signals of PHY chip circuit U 1
Output end connects；The difference MAC data frame I/O of PHY chip circuit U 1 is connected to the RJ45 sockets with isolating transformer
On J1；The data signal input/output terminal of the first via 485 of FPGA chip circuit 4 is received and dispatched by digital photoelectrical coupler U2 and 485
Device U8 data signal I/O connection, the data signal input/output terminal of the second tunnel 485 of FPGA chip circuit 4 pass through number
Word photoelectrical coupler U3 is connected with 485 transceiver U9 data signal I/O, the 3rd tunnel 485 of FPGA chip circuit 4
Data signal input/output terminal is connected by digital photoelectrical coupler U4 with 485 transceiver U10 data signal I/O,
The data signal input/output terminal of the 4th tunnel 485 of FPGA chip circuit 4 passes through digital photoelectrical coupler U5 and 485 transceiver U11
The connection of data signal I/O, the data signal input/output terminal of the 5th tunnel 485 of FPGA chip circuit 4 passes through digital light
Electric coupler U6 is connected with 485 transceiver U12 data signal I/O, the numeral of the 6th tunnel 485 of FPGA chip circuit 4
Signal input output end is connected by digital photoelectrical coupler U7 with 485 transceiver U13 data signal I/O, FPGA
The serial date transfer output end of chip circuit 4 is connected with the serial data I/O of EPCS configuration chip circuits 2, FPGA
232 data-signal input/output bus ends of chip circuit 4 are connected with the data output input bus end of 232 transceivers 1, FPGA
The Jtag test data I/Os of chip circuit 4 are connected on Jtag interfaces 3；485 transceiver U8~U13 485 communications
Data output input connects SM-6P-PCB sockets J2~J7 respectively；485 transceiver U8~U13 are independently supplied using insulating power supply
Electricity.
The model 88E1111 that the PHY chip circuit U 1 is selected, the model that digital photoelectrical coupler U2~U7 is selected
ACPL-064L/K64L low-power consumption 10MBd digital CMOS photoelectrical coupler；The model that 485 transceiver U8~U13 are selected
ADM485；The model HR911102A that RJ45 sockets J1 with isolating transformer is selected, the model that 232 transceivers 1 are selected
MAX3232CUE；The model EPCS16SI8N that EPCS configuration chip circuits 2 are selected；The model that FPGA chip circuit 4 is selected
EP4CE10E22 PLDs.
Operation principle：Circuit shown in Fig. 1 can serve as main website or serve as slave station in present embodiment.6 road RS485
The course of work for turning MAC layer data frame is as follows：Main website FPGA chip circuit 4 is opened when receiving driver and sending the instruction of data
Beginning is present the data received in register corresponding to FPGA chip circuit 4, when the instruction for receiving all six driver transmissions
Data in register are stored in data bit corresponding to MAC data frame to the form for being assembled into MAC data frame afterwards, then by number
Slave station circuit is transmitted to according to PHY chip circuit U 1, the RJ45 sockets J1 with isolating transformer and netting twine is passed sequentially through.In slave station
FPGA chip circuit 4 receives data, FPGA chip circuit 4 by the RJ45 sockets J1 with isolating transformer, PHY chip circuit U 1
The data of MAC layer data frame data position are passed through into digital photoelectricity respectively according to corresponding order after MAC layer data frame has been received
Coupler U2~U7 is sent to 485 corresponding transceiver U8~U13.Encoder circuit receive send data command after by
Corresponding data is passed through 485 transceiver U8~U13 and digital photoelectrical coupler by 3us data delay respectively according to corresponding order
U2~U7 is sent to FPGA chip circuit 4.FPGA chip circuit is stored data into after FPGA chip circuit 4 receives data
In 4 in corresponding register, register is addressed according to the corresponding number of axle, by register after the completion of all data receivers
Data be stored in MAC data frame corresponding to position start assemble MAC data frame, by data after MAC data frame is completed
Pass sequentially through PHY chip circuit U 1, the RJ45 sockets J1 with isolating transformer and network cable transmission and give main website circuit.Main website FPGA cores
Piece circuit 4 passes sequentially through the return that netting twine, the RJ45 sockets J1 with isolating transformer and PHY chip circuit U 1 receive encoder
The numerical value of return, is sent to relatively by value according to the order of data bit in MAC data frame by digital photoelectrical coupler U2~U7
Driver corresponding to each encoder is sent to after the 485 transceiver U8~U13 answered.Driver and volume of the circuit for each axle
The register storage that is identified by of code device is realized, and the register of each axle corresponds to fixed MAC layer data bit.
The course of work of RS232 parts is as follows：By host computer send customized message its send message format include
The part such as circuit board ID, read-write state, phy address, phy register address, register data forms.When
FPGA chip circuit 4 starts SMI protocol configuration PHY chips circuit U 1 when receiving corresponding phy chip register read write commands
Control register and control extended register, so as to reach the purpose of the mode of operation of control PHY chip circuit U 1, it gives tacit consent to work
Operation mode is full duplex 100Mbps forked working patterns.
Claims (1)
1. a kind of circuit of the 6 road code device signal transmission based on MAC layer, it is characterised in that it includes PHY chip circuit U 1, number
Word photoelectrical coupler U2~U7,485 transceiver U8~U13, RJ45 sockets J1,232 transceivers with isolating transformer（1）、
EPCS configures chip circuit（2）, Jtag interfaces（3）, FPGA chip circuit（4）, SM-6P-PCB sockets J2~J7；
FPGA chip circuit（4）MII data signals I/O and PHY chip circuit U 1 MII data signals input it is defeated
Go out end connection；The difference MAC data frame I/O of PHY chip circuit U 1 is connected to the RJ45 sockets J1 with isolating transformer
On；FPGA chip circuit（4）The data signal input/output terminal of the first via 485 pass through digital photoelectrical coupler U2 and 485 transmitting-receiving
Device U8 data signal I/O connection, FPGA chip circuit（4）The data signal input/output terminal of the second tunnel 485 pass through
Digital photoelectrical coupler U3 is connected with 485 transceiver U9 data signal I/O, FPGA chip circuit（4）The 3rd tunnel
485 data signal input/output terminals are connected by digital photoelectrical coupler U4 and 485 transceiver U10 data signal I/O
Connect, FPGA chip circuit（4）The data signal input/output terminal of the 4th tunnel 485 pass through digital photoelectrical coupler U5 and 485 transmitting-receiving
Device U11 data signal I/O connection, FPGA chip circuit（4）The data signal input/output terminal of the 5th tunnel 485 lead to
The data signal I/O that digital photoelectrical coupler U6 is crossed with 485 transceiver U12 is connected, FPGA chip circuit（4）
The data signal input/output terminal of six tunnel 485 is exported by digital photoelectrical coupler U7 and 485 transceiver U13 data signal and inputted
End connection, FPGA chip circuit（4）Serial date transfer output end and EPCS configuration chip circuit（2）Serial data output
Input connects, FPGA chip circuit（4）232 data-signal input/output bus ends and 232 transceivers（1）Data output
Input bus end connects, FPGA chip circuit（4）Jtag test data I/Os be connected to Jtag interfaces（3）On；485
Transceiver U8~U13 485 communication data I/Os connect SM-6P-PCB sockets J2~J7 respectively；485 transceiver U8~
U13 is independently-powered using insulating power supply；Wherein, main website FPGA chip circuit（4）Receiving the instruction of driver transmission data
When start that the data received are had FPGA chip circuit（4）In corresponding register, sent when receiving all six drivers
Instruction after the data in register are stored in data bit corresponding to MAC data frame to the form for being assembled into MAC data frame, so
Data are passed sequentially through into PHY chip circuit U 1, the RJ45 sockets J1 with isolating transformer and netting twine afterwards and are transmitted to slave station circuit；Slave station
In FPGA chip circuit（4）Data, FPGA cores are received by the RJ45 sockets J1 with isolating transformer, PHY chip circuit U 1
Piece circuit（4）The data of MAC layer data frame data position are passed through respectively according to corresponding order after MAC layer data frame has been received
Digital photoelectrical coupler U2~U7 is sent to 485 corresponding transceiver U8~U13；Encoder circuit receive send data refer to
Corresponding data is passed through into 485 transceiver U8~U13 and digital light respectively according to corresponding order by 3us data delay after order
Electric coupler U2~U7 is sent to FPGA chip circuit（4）；Treat FPGA chip circuit（4）Stored data into after receiving data
FPGA chip circuit（4）In in corresponding register, register is addressed according to the corresponding number of axle, complete in all data receivers
After by the data in register be stored in MAC data frame corresponding to position start assemble MAC data frame, in MAC data frame group
Data are passed sequentially through into PHY chip circuit U 1, the RJ45 sockets J1 with isolating transformer and network cable transmission to main website after the completion of dress
Circuit；Main website FPGA chip circuit（4）Pass sequentially through netting twine, the RJ45 sockets J1 with isolating transformer and PHY chip circuit U 1
The return value of encoder is received, the numerical value of return is passed through into digital photoelectrical coupler according to the order of data bit in MAC data frame
U2~U7 sends driver corresponding to each encoder to after being sent to 485 corresponding transceiver U8~U13；Circuit is for each
The register storage that is identified by of the driver and encoder of individual axle is realized, and the register of each axle corresponds to fixed MAC layer
Data bit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510304000.5A CN104935587B (en) | 2015-06-05 | 2015-06-05 | A kind of circuit of the 6 road code device signal transmission based on MAC layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510304000.5A CN104935587B (en) | 2015-06-05 | 2015-06-05 | A kind of circuit of the 6 road code device signal transmission based on MAC layer |
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| CN104935587A CN104935587A (en) | 2015-09-23 |
| CN104935587B true CN104935587B (en) | 2018-04-10 |
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| CN201510304000.5A Expired - Fee Related CN104935587B (en) | 2015-06-05 | 2015-06-05 | A kind of circuit of the 6 road code device signal transmission based on MAC layer |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105554034A (en) * | 2016-02-05 | 2016-05-04 | 哈尔滨博强机器人技术有限公司 | Transmission system for converting 9-channel coder signals into 1000Mbps PHY signals |
| WO2017132785A1 (en) * | 2016-02-05 | 2017-08-10 | 哈尔滨博强机器人技术有限公司 | Transmission system converting a signal of 9-channel encoder into 1000-mbps phy signal |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101976074A (en) * | 2010-11-03 | 2011-02-16 | 浙江工业大学 | Industrial control system based on field bus and control network |
| CN103135533A (en) * | 2013-01-08 | 2013-06-05 | 西安电子科技大学 | Master control devices for remote terminal control system |
| CN204231387U (en) * | 2014-11-12 | 2015-03-25 | 天津瑞能电气有限公司 | A kind of intelligent micro-grid control system realizing high-speed communication based on FPGA |
| CN204615855U (en) * | 2015-06-05 | 2015-09-02 | 哈尔滨博强机器人技术有限公司 | A kind of circuit of the 6 road code device signal transmission based on MAC layer |
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2015
- 2015-06-05 CN CN201510304000.5A patent/CN104935587B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101976074A (en) * | 2010-11-03 | 2011-02-16 | 浙江工业大学 | Industrial control system based on field bus and control network |
| CN103135533A (en) * | 2013-01-08 | 2013-06-05 | 西安电子科技大学 | Master control devices for remote terminal control system |
| CN204231387U (en) * | 2014-11-12 | 2015-03-25 | 天津瑞能电气有限公司 | A kind of intelligent micro-grid control system realizing high-speed communication based on FPGA |
| CN204615855U (en) * | 2015-06-05 | 2015-09-02 | 哈尔滨博强机器人技术有限公司 | A kind of circuit of the 6 road code device signal transmission based on MAC layer |
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Address after: Yellow Sea zone haping road centralized development zone in Harbin City, Heilongjiang province 150000 No. 25 1 floor East Applicant after: HARBIN BOQIANG ROBOT TECHNOLOGY Co.,Ltd. Address before: 150000 room 368, 1508 Changjiang Road, Nangang District, Harbin City, Heilongjiang Province Applicant before: HARBIN BOQIANG ROBOT TECHNOLOGY Co.,Ltd. |
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Inventor after: Liang Xunxing Inventor after: Zhou Wenbiao Inventor after: Zhang Yanqin Inventor after: Kong Minxiu Inventor before: Zhou Wenbiao Inventor before: Zhang Yanqin Inventor before: Kong Minxiu |
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Effective date of registration: 20210115 Address after: 212000 No.6, Shengdan Road, Dantu District, Zhenjiang City, Jiangsu Province Patentee after: Chen Weidi Address before: East area, 1st floor, building 1, No.25, Huanghai Road, Harbin Development Zone, Heilongjiang Province Patentee before: HARBIN BOQIANG ROBOT TECHNOLOGY Co.,Ltd. |
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Effective date of registration: 20210906 Address after: 251800 north of West first road, industrial Second Road, Yangxin County Economic Development Zone, Binzhou City, Shandong Province Patentee after: SHANDONG YANGXIN MINGTAI ELECTRIC Co.,Ltd. Address before: 212000 No.6, Shengdan Road, Dantu District, Zhenjiang City, Jiangsu Province Patentee before: Chen Weidi |
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