CN204578815U - Power down memory circuit - Google Patents
Power down memory circuit Download PDFInfo
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- CN204578815U CN204578815U CN201520086737.XU CN201520086737U CN204578815U CN 204578815 U CN204578815 U CN 204578815U CN 201520086737 U CN201520086737 U CN 201520086737U CN 204578815 U CN204578815 U CN 204578815U
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- electrically connected
- triode
- storage element
- oxide
- field effect
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The utility model discloses a kind of power down memory circuit, it comprises power subsystem, switch diagnosis unit, storage element and output unit, described power subsystem input is electrically connected switch diagnosis unit, described power subsystem output is electrically connected storage element, and described storage element is electrically connected output unit; Described output unit is metal-oxide-semiconductor field effect transistor, and grid and the described storage element output of described metal-oxide-semiconductor field effect transistor are electrically connected, the source ground of described metal-oxide-semiconductor field effect transistor, and the drain electrode of described metal-oxide-semiconductor field effect transistor is electrically connected reference voltage.The utility model is by being electrically connected the grid of storage element and metal-oxide-semiconductor field effect transistor; power subsystem is coordinated to charge to storage element; after power subsystem disconnects; storage element still can make metal-oxide-semiconductor field effect transistor be in conducting state; the drain electrode of metal-oxide-semiconductor field effect transistor is made to be in low level state; and then make the diagnostic signal exporting storage still can maintain low level for a long time, realize long power down protection, and effectively reduce the cost of power down protection.
Description
Technical field
The utility model relates to a kind of automobile lamp drive system, especially relates to a kind of power down memory circuit.
Background technology
The LED car lamp of existing automobile needs LED drive circuit cooperation to connect, and when a situation arises for LED car lamp, LED drive circuit generally needs to close all LED car lamp, and reports to the police to BCM (BCM Body Control Module); Meanwhile, LED car lamp a situation arises and produce diagnostic signal need store, upper once supply voltage powers on time, LED drive circuit can read this diagnostic signal, does not light all LED car lamp.
Power down at present for diagnostic signal stores, and is generally realized by MCU; Before supply voltage power down, diagnostic signal is stored in MCU internal flash FLASH by MCU fast, and the power down of FLASH is general all long for memory time.
The shortcoming of aforesaid way is that the access time of MCU is usually long, when power supply is pwm signal and is non-constant time, MCU needs to store this signal rapidly before supply voltage power down, when next supply voltage powers on, promptly read this signal, will be there are some restrictions in MCU, in addition, MCU is also device somewhat expensive in circuit in the application.
Another mode is that diagnostic signal is issued MCU, stores this signal by MCU, but so, BCM just needs an extra interface circuit.
Utility model content
Based on this, be necessary, for above-mentioned background technology Problems existing, to provide a kind of power down memory circuit, to realize long power down protection, and reduce the cost of power down protection.
For achieving the above object, the utility model discloses a kind of power down memory circuit, it comprises power subsystem, switch diagnosis unit, storage element and output unit, described power subsystem input is electrically connected switch diagnosis unit, described power subsystem output is electrically connected storage element, and described storage element is electrically connected output unit; Described output unit is metal-oxide-semiconductor field effect transistor, and grid and the described storage element output of described metal-oxide-semiconductor field effect transistor are electrically connected, the source ground of described metal-oxide-semiconductor field effect transistor, and the drain electrode of described metal-oxide-semiconductor field effect transistor is electrically connected reference voltage.
Wherein in an embodiment, described power subsystem comprises the first triode, described first transistor emitter is electrically connected reference voltage, and the base stage of described first triode is electrically connected described switch diagnosis unit, and the collector electrode of described first triode is electrically connected described storage element.
Wherein in an embodiment, described switch diagnosis unit comprises the second triode, the base stage of described second triode is for inputting external diagnostic signal, and the collector electrode of described second triode and the base stage of described first triode are electrically connected, the grounded emitter of described second triode.
Wherein in an embodiment, described storage element comprises electric capacity, and the collector electrode of described electric capacity one end and described first triode is electrically connected, described electric capacity other end ground connection.
Wherein in an embodiment, between described first triode and described electric capacity, electrical series has diode.
Wherein in an embodiment, be also electrically connected between described first triode and described electric capacity and discharge resistance one end, described release resistance other end ground connection.
In sum; the utility model power down memory circuit is by being electrically connected the grid of storage element and metal-oxide-semiconductor field effect transistor; power subsystem is coordinated to charge to storage element; after power subsystem disconnects; storage element still can make metal-oxide-semiconductor field effect transistor be in conducting state, makes the drain electrode of metal-oxide-semiconductor field effect transistor be in low level state, and then makes the diagnostic signal exporting storage still can maintain low level for a long time; realize long power down protection, and effectively reduce the cost of power down protection.
Accompanying drawing explanation
Fig. 1 is the schematic block circuit diagram of a kind of embodiment of the utility model power down memory circuit;
Fig. 2 is the circuit theory diagrams of a kind of embodiment of the utility model power down memory circuit.
Embodiment
As depicted in figs. 1 and 2, the utility model power down memory circuit comprises power subsystem 10, switch diagnosis unit 20, storage element 30 and output unit 40, described power subsystem 10 input is electrically connected switch diagnosis unit 20, described power subsystem 10 output is electrically connected storage element 30, and described storage element 30 is electrically connected output unit 40.
Described switch diagnosis unit 20 is in order to control power subsystem 10 and storage element 30 conducting, and described power subsystem 10 provides reference voltage V CC, and described power subsystem 10 charges for giving described storage element 30; Described storage element 30 is for being supplied to described output unit 40 conduction level, described output unit 40 is metal-oxide-semiconductor field effect transistor Q3, grid and described storage element 30 output of described metal-oxide-semiconductor field effect transistor Q3 are electrically connected, the source ground of described metal-oxide-semiconductor field effect transistor Q3, the drain electrode of described metal-oxide-semiconductor field effect transistor Q3 is electrically connected the reference voltage V CC of power subsystem 10.
Particularly, the input of described switch diagnosis unit 20 is for inputting external diagnostic signal, and the output of described output unit 40 is for exporting the diagnostic signal of storage, and the output of described output unit 40 corresponds to the drain electrode of metal-oxide-semiconductor field effect transistor Q3.
Wherein in an embodiment, described power subsystem 10 comprises the first triode Q1, described first triode Q1 emitter is electrically connected reference voltage V CC, the base stage of described first triode Q1 is electrically connected described switch diagnosis unit 20, and the collector electrode of described first triode Q1 is electrically connected described storage element 30.
Described switch diagnosis unit 20 comprises the second triode Q2, the base stage of described second triode Q2 is for inputting external diagnostic signal, the collector electrode of described second triode Q2 and the base stage of described first triode Q1 are electrically connected, the grounded emitter of described second triode Q2; When break signal of seeing and treating patients outside is high level, the second triode Q2 is in conducting state, and now, the electric current of the base-emitter of the first triode Q1 rises, and the first triode Q1 is also in conducting state, and power subsystem 10 starts to charge to described storage element 30.
Described storage element 30 comprises electric capacity C1, and the collector electrode of described electric capacity C1 one end and described first triode Q1 is electrically connected, described electric capacity C1 other end ground connection, and when the first triode Q1 is in conducting state, power subsystem 10 charges to described electric capacity C1; Particularly, between the first triode Q1 and described electric capacity C1, electrical series has diode D1, and after the connection that described power subsystem 10 disconnects with electric capacity C1, diode D1 can prevent electric capacity C1 from carrying out self discharging.
Wherein in an embodiment, also be electrically connected between described first triode Q1 and described electric capacity C1 and discharge resistance R2 one end, described release resistance R2 other end ground connection, described release resistance R2 is used for leakage current release path of described first triode Q1, prevents the leakage current of the first triode Q1 to charge to electric capacity C1.
During the utility model specific works, when external diagnostic signal is high level, second triode Q2 is in conducting state, the electric current of the base-emitter of the first triode Q1 is made to increase, and then first triode Q1 be also in conducting state, the reference voltage V CC of power subsystem 10 is charged to electric capacity C1 by diode D1, when the voltage on electric capacity C1 reaches a timing, metal-oxide-semiconductor field effect transistor Q3 can be in conducting state, due to the source ground of metal-oxide-semiconductor field effect transistor Q3, the drain electrode end of metal-oxide-semiconductor field effect transistor Q3 is made to export as low level, and then make the diagnostic signal exporting storage be low level.
LED car lamp a situation arises and produce diagnostic signal time, external diagnostic signal and reference voltage V CC are zero, because the voltage on electric capacity C1 maintains high level, diode D1 prevents the release of the electric charge that electric capacity C1 stores, the grid of metal-oxide-semiconductor field effect transistor Q3 maintains high level state, metal-oxide-semiconductor field effect transistor Q3 is just in conducting state always, the drain electrode end of metal-oxide-semiconductor field effect transistor Q3 is made to export as low level, and then make the diagnostic signal exporting storage maintain low level always, so, after supply voltage unit disconnects, export the diagnostic signal stored and still can maintain low level state for a long time, achieve long power down protection, and effectively reduce the cost of power down protection.
In sum; the utility model power down memory circuit is by being electrically connected the grid of storage element 30 with metal-oxide-semiconductor field effect transistor Q3; power subsystem 10 is coordinated to charge to storage element 30; after power subsystem 10 disconnects; storage element 30 still can make metal-oxide-semiconductor field effect transistor Q3 be in conducting state; the drain electrode of metal-oxide-semiconductor field effect transistor Q3 is made to be in low level state; and then make the diagnostic signal exporting storage still can maintain low level for a long time; realize long power down protection, and effectively reduce the cost of power down protection.
The above embodiment only have expressed several execution mode of the present utility model, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the utility model the scope of the claims.It should be pointed out that for the person of ordinary skill of the art, without departing from the concept of the premise utility, can also make some distortion and improvement, these all belong to protection range of the present utility model.Therefore, the protection range of the utility model patent should be as the criterion with claims.
Claims (6)
1. a power down memory circuit, it is characterized in that: comprise power subsystem (10), switch diagnosis unit (20), storage element (30) and output unit (40), described power subsystem (10) input is electrically connected switch diagnosis unit (20), described power subsystem (10) output is electrically connected storage element (30), and described storage element (30) is electrically connected output unit (40); Described output unit (40) is metal-oxide-semiconductor field effect transistor (Q3), grid and described storage element (30) output of described metal-oxide-semiconductor field effect transistor (Q3) are electrically connected, the source ground of described metal-oxide-semiconductor field effect transistor (Q3), the drain electrode of described metal-oxide-semiconductor field effect transistor (Q3) is electrically connected reference voltage (VCC).
2. power down memory circuit according to claim 1, it is characterized in that: described power subsystem (10) comprises the first triode (Q1), described first triode (Q1) emitter is electrically connected reference voltage (VCC), the base stage of described first triode (Q1) is electrically connected described switch diagnosis unit (20), and the collector electrode of described first triode (Q1) is electrically connected described storage element (30).
3. power down memory circuit according to claim 2, it is characterized in that: described switch diagnosis unit (20) comprises the second triode (Q2), the base stage of described second triode (Q2) is for inputting external diagnostic signal, the collector electrode of described second triode (Q2) and the base stage of described first triode (Q1) are electrically connected, the grounded emitter of described second triode (Q2).
4. according to claim 2 described power down memory circuit, it is characterized in that: described storage element (30) comprises electric capacity (C1), the collector electrode of described electric capacity (C1) one end and described first triode (Q1) is electrically connected, described electric capacity (C1) other end ground connection.
5. according to claim 4 described power down memory circuit, it is characterized in that: between described first triode (Q1) and described electric capacity (C1), electrical series has diode (D1).
6. according to claim 4 described power down memory circuit, it is characterized in that: be also electrically connected between described first triode (Q1) and described electric capacity (C1) and discharge resistance (R2) one end, described release resistance (R2) other end ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520086737.XU CN204578815U (en) | 2015-02-06 | 2015-02-06 | Power down memory circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520086737.XU CN204578815U (en) | 2015-02-06 | 2015-02-06 | Power down memory circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204578815U true CN204578815U (en) | 2015-08-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520086737.XU Expired - Fee Related CN204578815U (en) | 2015-02-06 | 2015-02-06 | Power down memory circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN204578815U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105322930A (en) * | 2015-12-02 | 2016-02-10 | 上海航空电器有限公司 | Short-time power down retaining circuit for direct-current solid-state power controller |
| CN113109738A (en) * | 2021-03-15 | 2021-07-13 | 苏州汇川技术有限公司 | Power-down time detection circuit and power-down time detection system |
-
2015
- 2015-02-06 CN CN201520086737.XU patent/CN204578815U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105322930A (en) * | 2015-12-02 | 2016-02-10 | 上海航空电器有限公司 | Short-time power down retaining circuit for direct-current solid-state power controller |
| CN113109738A (en) * | 2021-03-15 | 2021-07-13 | 苏州汇川技术有限公司 | Power-down time detection circuit and power-down time detection system |
| CN113109738B (en) * | 2021-03-15 | 2023-08-04 | 苏州汇川技术有限公司 | Power-down time detection circuit and power-down time detection system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150819 Termination date: 20190206 |