CN207573235U

CN207573235U - A kind of pure hardware switch off delay circuit

Info

Publication number: CN207573235U
Application number: CN201721556033.XU
Authority: CN
Inventors: 金定兴
Original assignee: Shanghai Xin Guo Power Science And Technology Ltd
Current assignee: Shanghai Xin Guo Power Science And Technology Ltd
Priority date: 2017-11-20
Filing date: 2017-11-20
Publication date: 2018-07-03
Anticipated expiration: 2027-11-20

Abstract

The utility model discloses a kind of pure hardware switch off delay circuit, the key signal of input is connect by being divided into two-way after a delay circuit with key controller module and inverter internal microcontroller respectively, and the delay circuit includes first, second, third, fourth resistance, the first capacitance, first, second diode, buffer, triode, p-type metal-oxide half field effect transistor and battery.The utility model simplifies inverter system internal circuit, is simple and efficient Master control chip inter-process, and using general electronic component in circuit, simple in structure, use cost is low.

Description

A kind of pure hardware switch off delay circuit

Technical field

The utility model is related to a kind of long-time delay circuits of digital signal, more particularly to a kind of to be applied to new energy vapour The switch off delay circuit of vehicle inverter.

Background technology

At present.For general new-energy automobile after key signal shutdown, inverter internal microcontroller (MCU) will enter number According to tupe, controller also needs to externally fed to maintain operation for a period of time (generally within 10 seconds), but inverter Internal power supply Support Capacitor cannot meet this requirement substantially.

With reference to shown in Fig. 1, general processing method is：The state (height) of system acquisition key signal (K1) is believed in key After number (K1) is disconnected, inverter internal continues to output a key controller signal (K2), and system is made to continue by external accumulator Power supply, system enters data processing mode, and after pending completion, system disconnects key controller signal (K2) automatically, under system Electricity is completed.

The disadvantage of general processing method:First is cost disadvantage, this system is needed with two buffer buff (level turn It changes)；Second is to occupy MCU resources.

Utility model content

The purpose of this utility model is that for the above-mentioned insufficient and defect of the prior art, a kind of pure hardware shutdown is provided and is prolonged Slow circuit is directly built by simple circuit devcie, can delay switch shutdown, reduce three-phase inverter system cost, Simplified system reduces the resource consumption of master chip.

Following technical scheme may be used to realize in the technical issues of the utility model solves：

A kind of pure hardware switch off delay circuit, which is characterized in that the key signal of input after a delay circuit by being divided into Two-way is connect respectively with key controller module and inverter internal microcontroller, and the delay circuit includes first, second, the 3rd, the 4th resistance, the first capacitance, first, second diode, buffer, triode, p-type metal-oxide half field effect transistor and battery, The key signal of input connects one end of the first resistor, the sun of another termination first diode of the first resistor Pole, the cathode of first diode connect one end of first capacitance, and the other end of first capacitance is grounded, and described first The cathode of diode connects one end of the second resistance, and the base stage of another termination triode of the second resistance is described The emitter ground connection of triode, the collector of the triode connect one end of the 4th resistance, the 4th resistance it is another The gate pole of the p-type metal-oxide half field effect transistor is terminated, the gate pole of the p-type metal-oxide half field effect transistor connects the third electricity again One end of resistance, another termination of the 3rd resistor input the anode of the battery, and the anode of the battery connects the p-type gold oxygen The source electrode of half field effect transistor, the drain electrode of the p-type metal-oxide half field effect transistor connect the key controller module, and the described 2nd 2 The anode of pole pipe connects the other end of the first resistor, and the cathode of second diode is conveyed to described by the buffer Inverter internal microcontroller.

As a result of technical solution as above, the utility model simplifies inverter system internal circuit, makes main control Chip interior processing is simple and efficient, and using general electronic component in circuit, simple in structure, use cost is low.

Description of the drawings

It in order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor Under, it can also be obtained according to these attached drawings other attached drawings.

Fig. 1 is the signal flow graph of traditional scheme.

Fig. 2 is the signal flow graph of the utility model.

Fig. 3 is the circuit diagram of the utility model.

Specific embodiment

In order to be easy to understand technical means, creative features, achievable purpose and effectiveness of the utility model, under The utility model is expanded on further in face.

Referring to Fig. 2 and a kind of pure hardware switch off delay circuit shown in Fig. 3, the key signal K1 of input passes through a deferred telegram It is divided into two-way behind road to connect with key controller module and inverter internal microcontroller respectively.

Delay circuit includes first, second, third, fourth resistance R1, R2, R3, R4, the first capacitance C1, first, second 2 Pole pipe D1, D2, buffer Buff, triode Q1, p-type metal-oxide half field effect transistor Q2 and battery BATT.The key signal of input K1 connects one end of first resistor R1, the anode of the first diode of another termination D1 of first resistor R1, the moon of the first diode D1 Pole connects one end of the first capacitance C1, the other end ground connection of the first capacitance C1, and the cathode of the first diode D1 connects second resistance R2's One end, the base stage of another termination triode Q1 of second resistance R2, the emitter ground connection of triode Q1, the collector of triode Q1 Connect one end of the 4th resistance R4, the gate pole of another termination p-type metal-oxide half field effect transistor Q2 of the 4th resistance R4, p-type gold oxygen half The gate pole of field-effect transistor Q2 connects one end of 3rd resistor R3 again, and another termination input battery BATT of 3rd resistor R3 is just Pole, the anode of battery BATT connect the source electrode of p-type metal-oxide half field effect transistor Q2, and the drain electrode of p-type metal-oxide half field effect transistor Q2 connects Key controller module.The anode of second diode D2 connects the other end of first resistor R1, and the cathode of the second diode D2, which passes through, to be delayed It rushes device Buff and is conveyed to the progress key signal K1 monitoring of inverter internal microcontroller.

The operation principle of the utility model is as follows：

In a flash, from low to high, electric current charges key signal K1 system electrification by first resistor R1 to the first capacitance C1； The base stage of triode Q1 is switched on by second resistance R2, after the 4th resistance R4,3rd resistor R3 partial pressure, p-type OH The gate pole conducting of transistor Q2, a high level are input in key controller module.It is lower electricity moment, key signal K1 by height to It is low, key signal K1 by MCU being given to monitor after the second diode D2 and buffer Buff, the charges of the first capacitance C1 memory storages after Continue and provide electric current to the base stage of triode Q1, keep triode Q1 in the conduction state, the 4th resistance R4,3rd resistor R3 continue Partial pressure ensures that p-type metal-oxide half field effect transistor Q2 is in the conduction state, and p-type metal-oxide half field effect transistor Q2 electric discharges pass through second Resistance R2 and the first diode D1 reverse blocking currents, thus discharge time can be 4*R2*C2=T, when by T time with Afterwards, triode Q1 is closed, and p-type metal-oxide half field effect transistor Q2 is closed.

The basic principle of the utility model and main feature and the advantages of the utility model has been shown and described above.One's own profession The technical staff of industry is it should be appreciated that the present utility model is not limited to the above embodiments, described in above embodiments and description Only illustrate the principle of the utility model, on the premise of not departing from the spirit and scope of the utility model, the utility model is also Various changes and modifications are had, these various changes and improvements fall within the scope of the claimed invention.The utility model Claimed range is defined by the appending claims and its equivalent thereof.

Claims

1. a kind of pure hardware switch off delay circuit, which is characterized in that the key signal of input after a delay circuit by being divided into two Road is connect respectively with key controller module and inverter internal microcontroller, and the delay circuit includes first, second, the 3rd, the 4th resistance, the first capacitance, first, second diode, buffer, triode, p-type metal-oxide half field effect transistor and battery, The key signal of input connects one end of the first resistor, the sun of another termination first diode of the first resistor Pole, the cathode of first diode connect one end of first capacitance, and the other end of first capacitance is grounded, and described first The cathode of diode connects one end of the second resistance, and the base stage of another termination triode of the second resistance is described The emitter ground connection of triode, the collector of the triode connect one end of the 4th resistance, the 4th resistance it is another The gate pole of the p-type metal-oxide half field effect transistor is terminated, the gate pole of the p-type metal-oxide half field effect transistor connects the third electricity again One end of resistance, another termination of the 3rd resistor input the anode of the battery, and the anode of the battery connects the p-type gold oxygen The source electrode of half field effect transistor, the drain electrode of the p-type metal-oxide half field effect transistor connect the key controller module, and the described 2nd 2 The anode of pole pipe connects the other end of the first resistor, and the cathode of second diode is conveyed to described by the buffer Inverter internal microcontroller.