CN204375732U - The superimposed designing semiconductor device encapsulating structure of a kind of Double-lead-frame - Google Patents
The superimposed designing semiconductor device encapsulating structure of a kind of Double-lead-frame Download PDFInfo
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- CN204375732U CN204375732U CN201420768716.1U CN201420768716U CN204375732U CN 204375732 U CN204375732 U CN 204375732U CN 201420768716 U CN201420768716 U CN 201420768716U CN 204375732 U CN204375732 U CN 204375732U
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Abstract
The utility model discloses the superimposed designing semiconductor device encapsulating structure of a kind of Double-lead-frame, comprise: the first lead frame and the second lead frame, during encapsulation, described second lead frame overlays on described first lead frame, described first lead frame comprises: the first chip carrier, at least one first chip gate pin, second chip carrier, at least one second chip drain pin, at least one second chip gate pin and the first lead frame housing, described second lead frame comprises: copper bridge, at least one second lead frame pin and the second lead frame housing.The superimposed designing semiconductor device encapsulating structure of Double-lead-frame described in the utility model utilizes the copper bridge on the second lead frame directly to be coupled together by the source electrode of the drain electrode of the first chip and the second chip, wire is instead of with copper bridge, improve the current carrying capacity of semiconductor device, and copper bridge can absorb the heat of the instantaneous generation of chip.
Description
Technical field
The utility model relates to technical field of semiconductors, particularly relates to the superimposed designing semiconductor device encapsulating structure of a kind of Double-lead-frame.
Background technology
Along with the development of semiconductor technology, require that the size of semiconductor device is more and more less, power is more and more higher, but the subject matter that size is little, high high electric current, the high thermal resistance caused of power is puzzlement semiconductor device.In order to address this problem, Double-lead-frame during encapsulation, is adopted to become increasing selection.In prior art, with more wire can be adopted during Double-lead-frame encapsulated semiconductor device to connect, more wire can produce extra heat, increases the burden of semiconductor device, and the current carrying capacity of wire is limited, cause the current carrying capacity of semiconductor device limited.
Utility model content
The utility model completes to solve above-mentioned deficiency of the prior art, the purpose of this utility model is to propose the superimposed designing semiconductor device encapsulating structure of a kind of Double-lead-frame, this structure can solve when encapsulating in prior art and adopt more wire to produce extra heat, and the problem causing semiconductor device current carrying capacity limited.
For reaching this object, the utility model by the following technical solutions:
The superimposed designing semiconductor device encapsulating structure of a kind of Double-lead-frame, comprising:
First lead frame and the second lead frame,
Described first lead frame comprises:
First chip carrier, for upside-down mounting first chip, during encapsulation, described first chip carrier is connected with the source electrode of described first chip;
At least one first chip gate pin, for connecting the grid of described first chip;
Second chip carrier, for formal dress second chip, during encapsulation, described second chip carrier is connected with the drain electrode of described second chip;
At least one second chip drain pin, described second chip drain pin is connected with described second chip carrier;
At least one second chip gate pin, for connecting the grid of described second chip;
First lead frame housing, described first chip carrier is connected with described first lead frame housing respectively by least one connecting rod with described second chip carrier, described first chip gate pin, described second chip drain pin are connected with described first lead frame housing respectively with described second chip gate pin
Described second lead frame comprises:
Copper bridge, during encapsulation, described second lead frame overlays on described first lead frame, and described copper bridging connects the drain electrode of described first chip and the source electrode of described second chip;
At least one second lead frame pin, described second lead frame pin and described copper bridging connect;
Second lead frame housing, described second lead frame pin is connected with described second lead frame housing.
Further, described Tong Qiao edge is provided with at least one and measures peephole.
Further, the copper bridge inside described measurement peephole is provided with at least one spout hole.
Further, described first chip carrier offers a kerf, described first chip gate pin extends to described incision.
Further, the lower surface of described first chip gate pin, described second chip drain pin, described second chip gate pin, the first chip carrier and the second chip carrier all at grade.
Further, the upper surface of described first chip gate pin, described second chip drain pin, described second chip gate pin, the first chip carrier and the second chip carrier all at grade.
Further, described second lead frame pin curves inwardly near the part of described copper bridge, make when described second lead frame overlays on described first lead frame, the lower surface of described second lead frame pin and the lower surface of described first chip gate pin are at grade.
The superimposed designing semiconductor device encapsulating structure of Double-lead-frame described in the utility model utilizes the copper bridge on the second lead frame directly to be coupled together by the source electrode of the drain electrode of the first chip and the second chip when encapsulating, wire is instead of with copper bridge, improve the current carrying capacity of semiconductor device, and copper bridge can absorb the heat of the instantaneous generation of chip.
Accompanying drawing explanation
In order to the technical scheme of the utility model exemplary embodiment is clearly described, one is done to the accompanying drawing used required for describing in embodiment below and simply introduce.Obviously, the accompanying drawing introduced is the accompanying drawing of a part of embodiment that the utility model will describe, instead of whole accompanying drawings, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the overall structure figure of the superimposed designing semiconductor device encapsulating structure of Double-lead-frame that the utility model embodiment one provides.
Fig. 2 is the structure chart of the first lead frame of the superimposed designing semiconductor device encapsulating structure of Double-lead-frame that the utility model embodiment one provides.
Fig. 3 is the structure chart of the second lead frame of the superimposed designing semiconductor device encapsulating structure of Double-lead-frame that the utility model embodiment one provides.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearly, below with reference to the accompanying drawing in the utility model embodiment, by embodiment, intactly the technical solution of the utility model is described.Obviously; described embodiment is a part of embodiment of the present utility model; instead of whole embodiments; based on embodiment of the present utility model; the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making creative work, all falls within protection range of the present utility model.
Embodiment one:
Fig. 1 is the overall structure figure of the superimposed designing semiconductor device encapsulating structure of Double-lead-frame that the utility model embodiment one provides.As shown in Figure 1, this encapsulating structure comprises:
First lead frame 100 and the second lead frame 200, when adopting this encapsulating structure to encapsulate semiconductor device, the second lead frame overlays on the first lead frame, and during encapsulation, the lower surface of the first lead frame be naked leakage outside.
Fig. 2 is the structure chart of the first lead frame of the superimposed designing semiconductor device encapsulating structure of Double-lead-frame that the utility model embodiment one provides.Wherein, the upper surface of the first lead frame in Fig. 2 is the contact-making surface of the first lead frame and the second lead frame.As shown in Figure 2, the first lead frame comprises:
First chip carrier 101, for upside-down mounting first chip, during encapsulation, the first chip carrier 101 is connected with the source electrode of the first chip.
When utilizing this encapsulating structure to encapsulate semiconductor device, the first chip carrier is the source electrode of the first chip of the semiconductor device after encapsulation.
At least one first chip gate pin one 02, for connecting the grid of the first chip.
When utilizing this encapsulating structure to encapsulate semiconductor device, the first chip gate pin is the grid of the first chip of the semiconductor device after encapsulation.
In the present embodiment, the first chip gate pin and the first chip carrier disconnect.First chip carrier can offer a kerf, and the first chip gate pin can extend to incision.When utilizing the encapsulating structure with this kind of structure to encapsulate semiconductor, the position of the first chip gate pin just corresponds to the gate location of the first chip, when the grid of connection first chip gate pin and the first chip, can directly by preparing in conjunction with material on the first chip gate pin, coupled together by the grid of solder reflow techniques by the first chip gate pin and the first chip again, avoid and utilize wire to connect, make encapsulation more convenient.
Second chip carrier 103, for formal dress second chip, during encapsulation, the second chip carrier 103 is connected with the drain electrode of the second chip.
In the present embodiment, the second chip carrier and the first chip carrier disconnect.
At least one second chip drain pin 104, second chip drain pin 104 is connected with the second chip carrier 103.
When utilizing this encapsulating structure to encapsulate semiconductor device, the second chip drain pin is the drain electrode of the second chip of the semiconductor device after encapsulation.
At least one second chip gate pin one 05, for connecting the grid of the second chip.
When utilizing this encapsulating structure to encapsulate semiconductor device, with wire, the second chip gate pin need be connected with the grid of the second chip.Second chip gate pin is the grid of the second chip of the semiconductor device after encapsulation.
In the present embodiment, the second chip gate pin and the second chip carrier disconnect.
First lead frame housing 106, first chip carrier 101 is connected with the first lead frame housing 106 with 108 respectively by least one connecting rod 107 with the second chip carrier 103, and the first chip gate pin one 02, second chip drain pin 104 is connected with the first lead frame housing 106 respectively with the second chip gate pin one 05.
When utilizing this encapsulating structure to encapsulate semiconductor device, after having encapsulated, also need to cut it, the first lead frame housing is removed.
Fig. 3 is the structure chart of the second lead frame of the superimposed designing semiconductor device encapsulating structure of Double-lead-frame that the utility model embodiment one provides.Wherein, the upper surface of the second lead frame in Fig. 3 is the contact-making surface of the second lead frame and the first lead frame.As shown in Figure 3, the second lead frame comprises:
Copper bridge 201, during encapsulation, copper bridge 201 connects the drain electrode of the first chip and the source electrode of the second chip.
When utilizing this encapsulating structure to encapsulate semiconductor device, the source electrode of the drain electrode of the first chip and the second chip couples together by copper bridge, avoid use wire, improve the current carrying capacity of semiconductor device, and copper bridge can absorb the heat of the instantaneous generation of chip, the high thermal resistance effect of semiconductor device can be reduced.
In the present embodiment, copper bridge 201 edge can be provided with at least one and measure peephole 204.After utilizing the encapsulating structure with this structure to encapsulate semiconductor, can solve the first lead frame and the second lead frame in prior art superimposed after, two-layer in conjunction with material owing to having, the height of semiconductor device is made to be difficult to control, and in the quality management and control stage in later stage, the copper bridge meeting block vision of the second lead frame, make to measure the problem of chip surface to the height of the first lead frame surface, the height of chip surface to the first lead frame surface can be measured easily by the measurement peephole that copper bridge is arranged.
Measure on the copper bridge inside peephole 204 and can be provided with at least one spout hole 205.When utilizing the encapsulating structure with this structure to encapsulate semiconductor, on the first lead frame, unnecessary climbing to copper bridge upper surface by spout hole is counter in conjunction with material, makes the combination of the first lead frame and the second lead frame tightr.
At least one second lead frame pin two 02, second lead frame pin two 02 is connected with copper bridge 201.
When utilizing this encapsulating structure to encapsulate semiconductor device, the second lead frame pin is the drain electrode of the first chip of the semiconductor device after encapsulation and the source electrode of the second chip.
Second lead frame housing 203, second lead frame pin two 02 is connected with the second lead frame housing 203.
When utilizing this encapsulating structure to encapsulate semiconductor device, after having encapsulated, also need to cut it, the second lead frame housing is removed.
In the present embodiment, first chip gate pin, second chip drain pin, second chip gate pin, the lower surface of the first chip carrier and the second chip carrier can all at grade, first chip gate pin, second chip drain pin, second chip gate pin, the upper surface of the first chip carrier and the second chip carrier all at grade, second lead frame pin curves inwardly near the part of copper bridge, as shown in 206 in Fig. 3, make when the second lead frame overlays on the first lead frame, the lower surface of the second lead frame pin and the lower surface of the first chip gate pin are at grade.When utilizing the encapsulating structure with this structure to encapsulate semiconductor device, various piece in encapsulation process is all at same plane, make encapsulation process simpler, convenient, and each pin of semiconductor device after having encapsulated is all at same plane, is convenient to the use in later stage.
The superimposed designing semiconductor device encapsulating structure of Double-lead-frame described in the utility model embodiment one at least has the following advantages when encapsulating: one is utilize the copper bridge on the second lead frame directly to be coupled together by the source electrode of the drain electrode of the first chip and the second chip, wire is instead of with copper bridge, improve the current carrying capacity of semiconductor device, and copper bridge can absorb the heat of the instantaneous generation of chip; Two is that measurement peephole by copper bridge is arranged can measure the height of chip surface to the first lead frame surface easily; Three is when assembling the second lead frame, and on the first lead frame, unnecessary climbing to copper bridge upper surface by spout hole is counter in conjunction with material, makes the combination of the first lead frame and the second lead frame tightr; Four is are all planes by the upper and lower faces of the first lead frame and the second lead frame, fairly simple in encapsulation process, convenient, and each pin of semiconductor device after encapsulation is all at same plane, is convenient to the use in later stage.
The know-why that above are only preferred embodiment of the present utility model and use.The utility model is not limited to specific embodiment described here, the various significant changes can carried out for a person skilled in the art, readjust and substitute all can not depart from protection range of the present utility model.Therefore, although be described in further detail the utility model by above embodiment, but the utility model is not limited only to above embodiment, when not departing from the utility model design, can also comprise other Equivalent embodiments more, and scope of the present utility model is determined by the scope of claim.
Claims (7)
1. the superimposed designing semiconductor device encapsulating structure of Double-lead-frame, is characterized in that, comprising:
First lead frame and the second lead frame,
Described first lead frame comprises:
First chip carrier, for upside-down mounting first chip, during encapsulation, described first chip carrier is connected with the source electrode of described first chip;
At least one first chip gate pin, for connecting the grid of described first chip;
Second chip carrier, for formal dress second chip, during encapsulation, described second chip carrier is connected with the drain electrode of described second chip;
At least one second chip drain pin, described second chip drain pin is connected with described second chip carrier;
At least one second chip gate pin, for connecting the grid of described second chip;
First lead frame housing, described first chip carrier is connected with described first lead frame housing respectively by least one connecting rod with described second chip carrier, described first chip gate pin, described second chip drain pin are connected with described first lead frame housing respectively with described second chip gate pin
Described second lead frame comprises:
Copper bridge, during encapsulation, described second lead frame overlays on described first lead frame, and described copper bridging connects the drain electrode of described first chip and the source electrode of described second chip;
At least one second lead frame pin, described second lead frame pin and described copper bridging connect;
Second lead frame housing, described second lead frame pin is connected with described second lead frame housing.
2. the superimposed designing semiconductor device encapsulating structure of Double-lead-frame according to claim 1, is characterized in that, described Tong Qiao edge is provided with at least one and measures peephole.
3. the superimposed designing semiconductor device encapsulating structure of Double-lead-frame according to claim 2, is characterized in that, the copper bridge inside described measurement peephole is provided with at least one spout hole.
4., according to the arbitrary described superimposed designing semiconductor device encapsulating structure of Double-lead-frame of claim 1-3, it is characterized in that, described first chip carrier offers a kerf, described first chip gate pin extends to described incision.
5. the superimposed designing semiconductor device encapsulating structure of Double-lead-frame according to claim 4, it is characterized in that, the lower surface of described first chip gate pin, described second chip drain pin, described second chip gate pin, the first chip carrier and the second chip carrier all at grade.
6. the superimposed designing semiconductor device encapsulating structure of Double-lead-frame according to claim 5, it is characterized in that, the upper surface of described first chip gate pin, described second chip drain pin, described second chip gate pin, the first chip carrier and the second chip carrier all at grade.
7. the superimposed designing semiconductor device encapsulating structure of the Double-lead-frame according to claim 5 or 6, it is characterized in that, described second lead frame pin curves inwardly near the part of described copper bridge, make when described second lead frame overlays on described first lead frame, the lower surface of described second lead frame pin and the lower surface of described first chip gate pin are at grade.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420768716.1U CN204375732U (en) | 2014-12-08 | 2014-12-08 | The superimposed designing semiconductor device encapsulating structure of a kind of Double-lead-frame |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420768716.1U CN204375732U (en) | 2014-12-08 | 2014-12-08 | The superimposed designing semiconductor device encapsulating structure of a kind of Double-lead-frame |
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| Publication Number | Publication Date |
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| CN204375732U true CN204375732U (en) | 2015-06-03 |
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| CN201420768716.1U Active CN204375732U (en) | 2014-12-08 | 2014-12-08 | The superimposed designing semiconductor device encapsulating structure of a kind of Double-lead-frame |
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